-- The Potato Processor - A simple processor for FPGAs
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-- The Potato Processor - A simple processor for FPGAs
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-- (c) Kristian Klomsten Skordal 2014 <kristian.skordal@wafflemail.net>
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-- (c) Kristian Klomsten Skordal 2014 <kristian.skordal@wafflemail.net>
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-- Report bugs and issues on <https://github.com/skordal/potato/issues>
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-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.pp_types.all;
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use work.pp_types.all;
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--! @brief Multiplexer used to choose between ALU inputs.
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--! @brief Multiplexer used to choose between ALU inputs.
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entity pp_alu_mux is
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entity pp_alu_mux is
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port(
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port(
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source : in alu_operand_source;
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source : in alu_operand_source;
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register_value : in std_logic_vector(31 downto 0);
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register_value : in std_logic_vector(31 downto 0);
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immediate_value : in std_logic_vector(31 downto 0);
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immediate_value : in std_logic_vector(31 downto 0);
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shamt_value : in std_logic_vector( 4 downto 0);
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shamt_value : in std_logic_vector( 4 downto 0);
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pc_value : in std_logic_vector(31 downto 0);
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pc_value : in std_logic_vector(31 downto 0);
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csr_value : in std_logic_vector(31 downto 0);
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csr_value : in std_logic_vector(31 downto 0);
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output : out std_logic_vector(31 downto 0)
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output : out std_logic_vector(31 downto 0)
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);
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);
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end entity pp_alu_mux;
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end entity pp_alu_mux;
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architecture behaviour of pp_alu_mux is
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architecture behaviour of pp_alu_mux is
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begin
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begin
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mux: process(source, register_value, immediate_value, shamt_value, pc_value, csr_value)
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mux: process(source, register_value, immediate_value, shamt_value, pc_value, csr_value)
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begin
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begin
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case source is
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case source is
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when ALU_SRC_REG =>
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when ALU_SRC_REG =>
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output <= register_value;
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output <= register_value;
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when ALU_SRC_IMM =>
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when ALU_SRC_IMM =>
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output <= immediate_value;
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output <= immediate_value;
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when ALU_SRC_PC =>
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when ALU_SRC_PC =>
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output <= pc_value;
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output <= pc_value;
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when ALU_SRC_PC_NEXT =>
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when ALU_SRC_PC_NEXT =>
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output <= std_logic_vector(unsigned(pc_value) + 4);
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output <= std_logic_vector(unsigned(pc_value) + 4);
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when ALU_SRC_CSR =>
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when ALU_SRC_CSR =>
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output <= csr_value;
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output <= csr_value;
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when ALU_SRC_SHAMT =>
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when ALU_SRC_SHAMT =>
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output <= (31 downto 5 => '0') & shamt_value;
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output <= (31 downto 5 => '0') & shamt_value;
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when ALU_SRC_NULL =>
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when ALU_SRC_NULL =>
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output <= (others => '0');
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output <= (others => '0');
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end case;
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end case;
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end process mux;
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end process mux;
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end architecture behaviour;
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end architecture behaviour;
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