-- The Potato Processor - A simple processor for FPGAs
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-- The Potato Processor - A simple processor for FPGAs
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-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
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-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
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-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
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-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.pp_types.all;
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use work.pp_constants.all;
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use work.pp_constants.all;
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use work.pp_csr.all;
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use work.pp_csr.all;
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use work.pp_types.all;
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use work.pp_utilities.all;
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--! @brief Unit decoding instructions and setting control signals apropriately.
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--! @brief Unit decoding instructions and setting control signals apropriately.
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entity pp_control_unit is
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entity pp_control_unit is
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port(
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port(
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-- Inputs, indices correspond to instruction word indices:
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-- Inputs, indices correspond to instruction word indices:
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opcode : in std_logic_vector( 4 downto 0);
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opcode : in std_logic_vector( 4 downto 0);
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funct3 : in std_logic_vector( 2 downto 0);
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funct3 : in std_logic_vector( 2 downto 0);
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funct7 : in std_logic_vector( 6 downto 0);
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funct7 : in std_logic_vector( 6 downto 0);
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funct12 : in std_logic_vectoR(11 downto 0);
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funct12 : in std_logic_vectoR(11 downto 0);
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-- Control signals:
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-- Control signals:
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rd_write : out std_logic;
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rd_write : out std_logic;
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branch : out branch_type;
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branch : out branch_type;
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-- Exception signals:
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-- Exception signals:
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decode_exception : out std_logic;
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decode_exception : out std_logic;
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decode_exception_cause : out std_logic_vector(4 downto 0);
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decode_exception_cause : out std_logic_vector(4 downto 0);
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-- Control register signals:
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-- Control register signals:
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csr_write : out csr_write_mode;
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csr_write : out csr_write_mode;
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csr_imm : out std_logic; --! Indicating an immediate variant of the csrr* instructions.
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csr_imm : out std_logic; --! Indicating an immediate variant of the csrr* instructions.
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-- Sources of operands to the ALU:
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-- Sources of operands to the ALU:
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alu_x_src, alu_y_src : out alu_operand_source;
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alu_x_src, alu_y_src : out alu_operand_source;
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-- ALU operation:
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-- ALU operation:
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alu_op : out alu_operation;
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alu_op : out alu_operation;
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-- Memory transaction parameters:
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-- Memory transaction parameters:
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mem_op : out memory_operation_type;
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mem_op : out memory_operation_type;
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mem_size : out memory_operation_size
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mem_size : out memory_operation_size
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);
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);
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end entity pp_control_unit;
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end entity pp_control_unit;
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architecture behaviour of pp_control_unit is
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architecture behaviour of pp_control_unit is
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signal exception : std_logic;
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signal exception_cause : std_logic_vector(4 downto 0);
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signal alu_op_temp : alu_operation;
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begin
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begin
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csr_imm <= funct3(2);
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csr_imm <= funct3(2);
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alu_op <= alu_op_temp;
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decode_exception <= exception or to_std_logic(alu_op_temp = ALU_INVALID);
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decode_exception_cause <= exception_cause when alu_op_temp /= ALU_INVALID
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else CSR_CAUSE_INVALID_INSTR;
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alu_control: entity work.pp_alu_control_unit
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alu_control: entity work.pp_alu_control_unit
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port map(
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port map(
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opcode => opcode,
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opcode => opcode,
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funct3 => funct3,
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funct3 => funct3,
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funct7 => funct7,
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funct7 => funct7,
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alu_x_src => alu_x_src,
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alu_x_src => alu_x_src,
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alu_y_src => alu_y_src,
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alu_y_src => alu_y_src,
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alu_op => alu_op
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alu_op => alu_op_temp
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);
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);
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decode_ctrl: process(opcode, funct3, funct12)
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decode_ctrl: process(opcode, funct3, funct12)
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begin
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begin
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case opcode is
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case opcode is
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when b"01101" => -- Load upper immediate
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when b"01101" => -- Load upper immediate
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rd_write <= '1';
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rd_write <= '1';
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decode_exception <= '0';
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exception <= '0';
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decode_exception_cause <= CSR_CAUSE_NONE;
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exception_cause <= CSR_CAUSE_NONE;
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branch <= BRANCH_NONE;
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branch <= BRANCH_NONE;
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when b"00101" => -- Add upper immediate to PC
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when b"00101" => -- Add upper immediate to PC
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rd_write <= '1';
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rd_write <= '1';
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decode_exception <= '0';
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exception <= '0';
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decode_exception_cause <= CSR_CAUSE_NONE;
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exception_cause <= CSR_CAUSE_NONE;
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branch <= BRANCH_NONE;
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branch <= BRANCH_NONE;
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when b"11011" => -- Jump and link
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when b"11011" => -- Jump and link
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rd_write <= '1';
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rd_write <= '1';
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decode_exception <= '0';
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exception <= '0';
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decode_exception_cause <= CSR_CAUSE_NONE;
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exception_cause <= CSR_CAUSE_NONE;
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branch <= BRANCH_JUMP;
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branch <= BRANCH_JUMP;
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when b"11001" => -- Jump and link register
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when b"11001" => -- Jump and link register
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rd_write <= '1';
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rd_write <= '1';
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decode_exception <= '0';
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exception <= '0';
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decode_exception_cause <= CSR_CAUSE_NONE;
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exception_cause <= CSR_CAUSE_NONE;
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branch <= BRANCH_JUMP_INDIRECT;
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branch <= BRANCH_JUMP_INDIRECT;
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when b"11000" => -- Branch operations
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when b"11000" => -- Branch operations
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rd_write <= '0';
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rd_write <= '0';
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decode_exception <= '0';
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exception <= '0';
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decode_exception_cause <= CSR_CAUSE_NONE;
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exception_cause <= CSR_CAUSE_NONE;
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branch <= BRANCH_CONDITIONAL;
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branch <= BRANCH_CONDITIONAL;
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when b"00000" => -- Load instructions
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when b"00000" => -- Load instructions
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rd_write <= '1';
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rd_write <= '1';
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decode_exception <= '0';
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exception <= '0';
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decode_exception_cause <= CSR_CAUSE_NONE;
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exception_cause <= CSR_CAUSE_NONE;
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branch <= BRANCH_NONE;
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branch <= BRANCH_NONE;
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when b"01000" => -- Store instructions
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when b"01000" => -- Store instructions
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rd_write <= '0';
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rd_write <= '0';
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decode_exception <= '0';
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exception <= '0';
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decode_exception_cause <= CSR_CAUSE_NONE;
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exception_cause <= CSR_CAUSE_NONE;
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branch <= BRANCH_NONE;
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branch <= BRANCH_NONE;
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when b"00100" => -- Register-immediate operations
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when b"00100" => -- Register-immediate operations
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rd_write <= '1';
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rd_write <= '1';
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decode_exception <= '0';
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exception <= '0';
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decode_exception_cause <= CSR_CAUSE_NONE;
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exception_cause <= CSR_CAUSE_NONE;
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branch <= BRANCH_NONE;
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branch <= BRANCH_NONE;
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when b"01100" => -- Register-register operations
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when b"01100" => -- Register-register operations
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rd_write <= '1';
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rd_write <= '1';
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decode_exception <= '0';
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exception <= '0';
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decode_exception_cause <= CSR_CAUSE_NONE;
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exception_cause <= CSR_CAUSE_NONE;
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branch <= BRANCH_NONE;
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branch <= BRANCH_NONE;
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when b"00011" => -- Fence instructions, ignored
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when b"00011" => -- Fence instructions, ignored
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rd_write <= '0';
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rd_write <= '0';
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decode_exception <= '0';
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exception <= '0';
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decode_exception_cause <= CSR_CAUSE_NONE;
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exception_cause <= CSR_CAUSE_NONE;
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branch <= BRANCH_NONE;
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branch <= BRANCH_NONE;
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when b"11100" => -- System instructions
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when b"11100" => -- System instructions
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if funct3 = b"000" then
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if funct3 = b"000" then
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rd_write <= '0';
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rd_write <= '0';
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if funct12 = x"000" then
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if funct12 = x"000" then
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decode_exception <= '1';
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exception <= '1';
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decode_exception_cause <= CSR_CAUSE_SYSCALL;
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exception_cause <= CSR_CAUSE_SYSCALL;
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branch <= BRANCH_NONE;
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branch <= BRANCH_NONE;
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elsif funct12 = x"001" then
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elsif funct12 = x"001" then
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decode_exception <= '1';
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exception <= '1';
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decode_exception_cause <= CSR_CAUSE_BREAKPOINT;
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exception_cause <= CSR_CAUSE_BREAKPOINT;
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branch <= BRANCH_NONE;
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branch <= BRANCH_NONE;
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elsif funct12 = x"800" then
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elsif funct12 = x"800" then
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decode_exception <= '0';
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exception <= '0';
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decode_exception_cause <= CSR_CAUSE_NONE;
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exception_cause <= CSR_CAUSE_NONE;
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branch <= BRANCH_SRET;
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branch <= BRANCH_SRET;
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else
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else
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decode_exception <= '1';
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exception <= '1';
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decode_exception_cause <= CSR_CAUSE_INVALID_INSTR;
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exception_cause <= CSR_CAUSE_INVALID_INSTR;
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branch <= BRANCH_NONE;
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branch <= BRANCH_NONE;
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end if;
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end if;
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else
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else
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rd_write <= '1';
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rd_write <= '1';
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decode_exception <= '0';
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exception <= '0';
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decode_exception_cause <= CSR_CAUSE_NONE;
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exception_cause <= CSR_CAUSE_NONE;
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branch <= BRANCH_NONE;
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branch <= BRANCH_NONE;
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end if;
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end if;
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when others =>
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when others =>
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rd_write <= '0';
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rd_write <= '0';
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decode_exception <= '1';
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exception <= '1';
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decode_exception_cause <= CSR_CAUSE_INVALID_INSTR;
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exception_cause <= CSR_CAUSE_INVALID_INSTR;
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branch <= BRANCH_NONE;
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branch <= BRANCH_NONE;
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end case;
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end case;
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end process decode_ctrl;
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end process decode_ctrl;
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decode_csr: process(opcode, funct3)
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decode_csr: process(opcode, funct3)
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begin
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begin
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if opcode = b"11100" then
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if opcode = b"11100" then
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case funct3 is
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case funct3 is
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when b"001" | b"101" => -- csrrw/i
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when b"001" | b"101" => -- csrrw/i
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csr_write <= CSR_WRITE_REPLACE;
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csr_write <= CSR_WRITE_REPLACE;
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when b"010" | b"110" => -- csrrs/i
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when b"010" | b"110" => -- csrrs/i
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csr_write <= CSR_WRITE_SET;
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csr_write <= CSR_WRITE_SET;
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when b"011" | b"111" => -- csrrc/i
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when b"011" | b"111" => -- csrrc/i
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csr_write <= CSR_WRITE_CLEAR;
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csr_write <= CSR_WRITE_CLEAR;
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when others =>
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when others =>
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csr_write <= CSR_WRITE_NONE;
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csr_write <= CSR_WRITE_NONE;
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end case;
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end case;
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else
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else
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csr_write <= CSR_WRITE_NONE;
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csr_write <= CSR_WRITE_NONE;
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end if;
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end if;
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end process decode_csr;
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end process decode_csr;
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decode_mem: process(opcode, funct3)
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decode_mem: process(opcode, funct3)
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begin
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begin
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case opcode is
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case opcode is
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when b"00000" => -- Load instructions
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when b"00000" => -- Load instructions
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case funct3 is
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case funct3 is
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when b"000" => -- lw
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when b"000" => -- lw
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mem_size <= MEMOP_SIZE_BYTE;
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mem_size <= MEMOP_SIZE_BYTE;
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mem_op <= MEMOP_TYPE_LOAD;
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mem_op <= MEMOP_TYPE_LOAD;
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when b"001" => -- lh
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when b"001" => -- lh
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mem_size <= MEMOP_SIZE_HALFWORD;
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mem_size <= MEMOP_SIZE_HALFWORD;
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mem_op <= MEMOP_TYPE_LOAD;
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mem_op <= MEMOP_TYPE_LOAD;
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when b"010" | b"110" => -- lw
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when b"010" | b"110" => -- lw
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mem_size <= MEMOP_SIZE_WORD;
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mem_size <= MEMOP_SIZE_WORD;
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mem_op <= MEMOP_TYPE_LOAD;
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mem_op <= MEMOP_TYPE_LOAD;
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when b"100" => -- lbu
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when b"100" => -- lbu
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mem_size <= MEMOP_SIZE_BYTE;
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mem_size <= MEMOP_SIZE_BYTE;
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mem_op <= MEMOP_TYPE_LOAD_UNSIGNED;
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mem_op <= MEMOP_TYPE_LOAD_UNSIGNED;
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when b"101" => -- lhu
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when b"101" => -- lhu
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mem_size <= MEMOP_SIZE_HALFWORD;
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mem_size <= MEMOP_SIZE_HALFWORD;
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mem_op <= MEMOP_TYPE_LOAD_UNSIGNED;
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mem_op <= MEMOP_TYPE_LOAD_UNSIGNED;
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when others => -- FIXME: Treat others as lw.
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when others => -- FIXME: Treat others as lw.
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mem_size <= MEMOP_SIZE_WORD;
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mem_size <= MEMOP_SIZE_WORD;
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mem_op <= MEMOP_TYPE_INVALID;
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mem_op <= MEMOP_TYPE_INVALID;
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end case;
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end case;
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when b"01000" => -- Store instructions
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when b"01000" => -- Store instructions
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case funct3 is
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case funct3 is
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when b"000" =>
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when b"000" =>
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mem_op <= MEMOP_TYPE_STORE;
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mem_op <= MEMOP_TYPE_STORE;
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mem_size <= MEMOP_SIZE_BYTE;
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mem_size <= MEMOP_SIZE_BYTE;
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when b"001" =>
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when b"001" =>
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mem_op <= MEMOP_TYPE_STORE;
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mem_op <= MEMOP_TYPE_STORE;
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mem_size <= MEMOP_SIZE_HALFWORD;
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mem_size <= MEMOP_SIZE_HALFWORD;
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when b"010" =>
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when b"010" =>
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mem_op <= MEMOP_TYPE_STORE;
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mem_op <= MEMOP_TYPE_STORE;
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mem_size <= MEMOP_SIZE_WORD;
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mem_size <= MEMOP_SIZE_WORD;
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when others =>
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when others =>
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mem_op <= MEMOP_TYPE_INVALID;
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mem_op <= MEMOP_TYPE_INVALID;
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mem_size <= MEMOP_SIZE_WORD;
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mem_size <= MEMOP_SIZE_WORD;
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end case;
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end case;
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when others =>
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when others =>
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mem_op <= MEMOP_TYPE_NONE;
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mem_op <= MEMOP_TYPE_NONE;
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mem_size <= MEMOP_SIZE_WORD;
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mem_size <= MEMOP_SIZE_WORD;
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end case;
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end case;
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end process decode_mem;
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end process decode_mem;
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end architecture behaviour;
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end architecture behaviour;
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