-- The Potato Processor - A simple processor for FPGAs
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-- The Potato Processor - A simple processor for FPGAs
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-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
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-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
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-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
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-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.pp_types.all;
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use work.pp_types.all;
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use work.pp_constants.all;
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use work.pp_constants.all;
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use work.pp_utilities.all;
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use work.pp_utilities.all;
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use work.pp_csr.all;
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use work.pp_csr.all;
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--! @brief The Potato Processor is a simple processor core for use in FPGAs.
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--! @brief The Potato Processor is a simple processor core for use in FPGAs.
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--! @details
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--! @details
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--! It implements the RV32I (RISC-V base integer subset) ISA with additional
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--! It implements the RV32I (RISC-V base integer subset) ISA with additional
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--! instructions for manipulation of control and status registers from the
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--! instructions for manipulation of control and status registers from the
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--! currently unpublished supervisor extension.
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--! currently unpublished supervisor extension.
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entity pp_core is
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entity pp_core is
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generic(
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generic(
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PROCESSOR_ID : std_logic_vector(31 downto 0) := x"00000000"; --! Processor ID.
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PROCESSOR_ID : std_logic_vector(31 downto 0) := x"00000000"; --! Processor ID.
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RESET_ADDRESS : std_logic_vector(31 downto 0) := x"00000000" --! Address of the first instruction to execute.
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RESET_ADDRESS : std_logic_vector(31 downto 0) := x"00000000" --! Address of the first instruction to execute.
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);
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);
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port(
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port(
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-- Control inputs:
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-- Control inputs:
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clk : in std_logic; --! Processor clock
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clk : in std_logic; --! Processor clock
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reset : in std_logic; --! Reset signal
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reset : in std_logic; --! Reset signal
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timer_clk : in std_logic; --! Clock used for the timer/counter
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timer_clk : in std_logic; --! Clock used for the timer/counter
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-- Instruction memory interface:
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-- Instruction memory interface:
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imem_address : out std_logic_vector(31 downto 0); --! Address of the next instruction
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imem_address : out std_logic_vector(31 downto 0); --! Address of the next instruction
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imem_data_in : in std_logic_vector(31 downto 0); --! Instruction input
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imem_data_in : in std_logic_vector(31 downto 0); --! Instruction input
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imem_req : out std_logic;
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imem_req : out std_logic;
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imem_ack : in std_logic;
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imem_ack : in std_logic;
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-- Data memory interface:
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-- Data memory interface:
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dmem_address : out std_logic_vector(31 downto 0); --! Data address
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dmem_address : out std_logic_vector(31 downto 0); --! Data address
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dmem_data_in : in std_logic_vector(31 downto 0); --! Input from the data memory
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dmem_data_in : in std_logic_vector(31 downto 0); --! Input from the data memory
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dmem_data_out : out std_logic_vector(31 downto 0); --! Ouptut to the data memory
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dmem_data_out : out std_logic_vector(31 downto 0); --! Ouptut to the data memory
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dmem_data_size : out std_logic_vector( 1 downto 0); --! Size of the data, 1 = 8 bits, 2 = 16 bits, 0 = 32 bits.
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dmem_data_size : out std_logic_vector( 1 downto 0); --! Size of the data, 1 = 8 bits, 2 = 16 bits, 0 = 32 bits.
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dmem_read_req : out std_logic; --! Data memory read request
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dmem_read_req : out std_logic; --! Data memory read request
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dmem_read_ack : in std_logic; --! Data memory read acknowledge
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dmem_read_ack : in std_logic; --! Data memory read acknowledge
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dmem_write_req : out std_logic; --! Data memory write request
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dmem_write_req : out std_logic; --! Data memory write request
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dmem_write_ack : in std_logic; --! Data memory write acknowledge
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dmem_write_ack : in std_logic; --! Data memory write acknowledge
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-- Tohost/fromhost interface:
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-- Tohost/fromhost interface:
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fromhost_data : in std_logic_vector(31 downto 0); --! Data from the host/simulator.
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fromhost_data : in std_logic_vector(31 downto 0); --! Data from the host/simulator.
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fromhost_write_en : in std_logic; --! Write enable signal from the host/simulator.
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fromhost_write_en : in std_logic; --! Write enable signal from the host/simulator.
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tohost_data : out std_logic_vector(31 downto 0); --! Data to the host/simulator.
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tohost_data : out std_logic_vector(31 downto 0); --! Data to the host/simulator.
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tohost_write_en : out std_logic; --! Write enable signal to the host/simulator.
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tohost_write_en : out std_logic; --! Write enable signal to the host/simulator.
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-- External interrupt input:
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-- External interrupt input:
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irq : in std_logic_vector(7 downto 0) --! IRQ inputs.
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irq : in std_logic_vector(7 downto 0) --! IRQ inputs.
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);
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);
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end entity pp_core;
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end entity pp_core;
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architecture behaviour of pp_core is
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architecture behaviour of pp_core is
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------- Flush signals -------
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------- Flush signals -------
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signal flush_if, flush_id, flush_ex : std_logic;
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signal flush_if, flush_id, flush_ex : std_logic;
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------- Stall signals -------
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------- Stall signals -------
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signal stall_if, stall_id, stall_ex, stall_mem : std_logic;
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signal stall_if, stall_id, stall_ex, stall_mem : std_logic;
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-- Signals used to determine if an instruction should be counted
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-- Signals used to determine if an instruction should be counted
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-- by the instret counter:
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-- by the instret counter:
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signal if_count_instruction, id_count_instruction : std_logic;
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signal if_count_instruction, id_count_instruction : std_logic;
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signal ex_count_instruction, mem_count_instruction : std_logic;
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signal ex_count_instruction, mem_count_instruction : std_logic;
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signal wb_count_instruction : std_logic;
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signal wb_count_instruction : std_logic;
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-- CSR read port signals:
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-- CSR read port signals:
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signal csr_read_data : std_logic_vector(31 downto 0);
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signal csr_read_data : std_logic_vector(31 downto 0);
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signal csr_read_writeable : boolean;
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signal csr_read_writeable : boolean;
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signal csr_read_address, csr_read_address_p : csr_address;
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-- Status register outputs:
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-- Status register outputs:
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signal status : csr_status_register;
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signal status : csr_status_register;
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signal evec : std_logic_vector(31 downto 0);
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signal evec : std_logic_vector(31 downto 0);
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-- Load hazard detected in the execute stage:
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-- Load hazard detected in the execute stage:
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signal load_hazard_detected : std_logic;
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signal load_hazard_detected : std_logic;
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-- Branch targets:
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-- Branch targets:
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signal exception_target, branch_target : std_logic_vector(31 downto 0);
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signal exception_target, branch_target : std_logic_vector(31 downto 0);
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signal branch_taken, exception_taken : std_logic;
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signal branch_taken, exception_taken : std_logic;
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-- Register file read ports:
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-- Register file read ports:
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signal rs1_address_p, rs2_address_p : register_address;
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signal rs1_address_p, rs2_address_p : register_address;
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signal rs1_address, rs2_address : register_address;
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signal rs1_address, rs2_address : register_address;
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signal rs1_data, rs2_data : std_logic_vector(31 downto 0);
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signal rs1_data, rs2_data : std_logic_vector(31 downto 0);
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-- Data memory signals:
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-- Data memory signals:
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signal dmem_address_p : std_logic_vector(31 downto 0);
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signal dmem_address_p : std_logic_vector(31 downto 0);
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signal dmem_data_size_p : std_logic_vector(1 downto 0);
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signal dmem_data_size_p : std_logic_vector(1 downto 0);
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signal dmem_data_out_p : std_logic_vector(31 downto 0);
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signal dmem_data_out_p : std_logic_vector(31 downto 0);
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signal dmem_read_req_p : std_logic;
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signal dmem_read_req_p : std_logic;
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signal dmem_write_req_p : std_logic;
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signal dmem_write_req_p : std_logic;
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-- Fetch stage signals:
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-- Fetch stage signals:
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signal if_instruction, if_pc : std_logic_vector(31 downto 0);
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signal if_instruction, if_pc : std_logic_vector(31 downto 0);
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signal if_instruction_ready : std_logic;
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signal if_instruction_ready : std_logic;
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-- Decode stage signals:
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-- Decode stage signals:
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signal id_funct3 : std_logic_vector(2 downto 0);
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signal id_funct3 : std_logic_vector(2 downto 0);
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signal id_rd_address : register_address;
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signal id_rd_address : register_address;
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signal id_rd_write : std_logic;
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signal id_rd_write : std_logic;
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signal id_rs1_address : register_address;
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signal id_rs1_address : register_address;
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signal id_rs2_address : register_address;
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signal id_rs2_address : register_address;
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signal id_csr_address : csr_address;
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signal id_csr_address : csr_address;
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signal id_csr_write : csr_write_mode;
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signal id_csr_write : csr_write_mode;
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signal id_csr_use_immediate : std_logic;
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signal id_csr_use_immediate : std_logic;
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signal id_shamt : std_logic_vector(4 downto 0);
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signal id_shamt : std_logic_vector(4 downto 0);
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signal id_immediate : std_logic_vector(31 downto 0);
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signal id_immediate : std_logic_vector(31 downto 0);
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signal id_branch : branch_type;
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signal id_branch : branch_type;
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signal id_alu_x_src, id_alu_y_src : alu_operand_source;
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signal id_alu_x_src, id_alu_y_src : alu_operand_source;
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signal id_alu_op : alu_operation;
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signal id_alu_op : alu_operation;
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signal id_mem_op : memory_operation_type;
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signal id_mem_op : memory_operation_type;
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signal id_mem_size : memory_operation_size;
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signal id_mem_size : memory_operation_size;
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signal id_pc : std_logic_vector(31 downto 0);
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signal id_pc : std_logic_vector(31 downto 0);
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signal id_exception : std_logic;
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signal id_exception : std_logic;
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signal id_exception_cause : csr_exception_cause;
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signal id_exception_cause : csr_exception_cause;
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-- Execute stage signals:
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-- Execute stage signals:
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signal ex_dmem_address : std_logic_vector(31 downto 0);
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signal ex_dmem_address : std_logic_vector(31 downto 0);
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signal ex_dmem_data_size : std_logic_vector(1 downto 0);
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signal ex_dmem_data_size : std_logic_vector(1 downto 0);
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signal ex_dmem_data_out : std_logic_vector(31 downto 0);
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signal ex_dmem_data_out : std_logic_vector(31 downto 0);
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signal ex_dmem_read_req : std_logic;
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signal ex_dmem_read_req : std_logic;
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signal ex_dmem_write_req : std_logic;
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signal ex_dmem_write_req : std_logic;
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signal ex_rd_address : register_address;
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signal ex_rd_address : register_address;
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signal ex_rd_data : std_logic_vector(31 downto 0);
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signal ex_rd_data : std_logic_vector(31 downto 0);
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signal ex_rd_write : std_logic;
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signal ex_rd_write : std_logic;
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signal ex_pc : std_logic_vector(31 downto 0);
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signal ex_pc : std_logic_vector(31 downto 0);
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signal ex_csr_address : csr_address;
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signal ex_csr_address : csr_address;
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signal ex_csr_write : csr_write_mode;
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signal ex_csr_write : csr_write_mode;
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signal ex_csr_data : std_logic_vector(31 downto 0);
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signal ex_csr_data : std_logic_vector(31 downto 0);
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signal ex_branch : branch_type;
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signal ex_branch : branch_type;
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signal ex_mem_op : memory_operation_type;
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signal ex_mem_op : memory_operation_type;
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signal ex_mem_size : memory_operation_size;
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signal ex_mem_size : memory_operation_size;
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signal ex_exception_context : csr_exception_context;
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signal ex_exception_context : csr_exception_context;
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-- Memory stage signals:
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-- Memory stage signals:
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signal mem_rd_write : std_logic;
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signal mem_rd_write : std_logic;
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signal mem_rd_address : register_address;
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signal mem_rd_address : register_address;
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signal mem_rd_data : std_logic_vector(31 downto 0);
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signal mem_rd_data : std_logic_vector(31 downto 0);
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signal mem_csr_address : csr_address;
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signal mem_csr_address : csr_address;
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signal mem_csr_write : csr_write_mode;
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signal mem_csr_write : csr_write_mode;
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signal mem_csr_data : std_logic_vector(31 downto 0);
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signal mem_csr_data : std_logic_vector(31 downto 0);
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signal mem_mem_op : memory_operation_type;
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signal mem_mem_op : memory_operation_type;
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signal mem_exception : std_logic;
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signal mem_exception : std_logic;
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signal mem_exception_context : csr_exception_context;
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signal mem_exception_context : csr_exception_context;
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-- Writeback signals:
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-- Writeback signals:
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signal wb_rd_address : register_address;
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signal wb_rd_address : register_address;
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signal wb_rd_data : std_logic_vector(31 downto 0);
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signal wb_rd_data : std_logic_vector(31 downto 0);
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signal wb_rd_write : std_logic;
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signal wb_rd_write : std_logic;
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signal wb_csr_address : csr_address;
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signal wb_csr_address : csr_address;
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signal wb_csr_write : csr_write_mode;
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signal wb_csr_write : csr_write_mode;
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signal wb_csr_data : std_logic_vector(31 downto 0);
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signal wb_csr_data : std_logic_vector(31 downto 0);
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signal wb_exception : std_logic;
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signal wb_exception : std_logic;
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signal wb_exception_context : csr_exception_context;
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signal wb_exception_context : csr_exception_context;
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begin
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begin
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stall_if <= stall_id;
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stall_if <= stall_id;
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stall_id <= stall_ex;
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stall_id <= stall_ex;
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stall_ex <= load_hazard_detected or stall_mem;
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stall_ex <= load_hazard_detected or stall_mem;
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stall_mem <= to_std_logic(memop_is_load(mem_mem_op) and dmem_read_ack = '0')
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stall_mem <= to_std_logic(memop_is_load(mem_mem_op) and dmem_read_ack = '0')
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or to_std_logic(mem_mem_op = MEMOP_TYPE_STORE and dmem_write_ack = '0');
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or to_std_logic(mem_mem_op = MEMOP_TYPE_STORE and dmem_write_ack = '0');
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flush_if <= (branch_taken or exception_taken) and not stall_if;
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flush_if <= (branch_taken or exception_taken) and not stall_if;
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flush_id <= (branch_taken or exception_taken) and not stall_id;
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flush_id <= (branch_taken or exception_taken) and not stall_id;
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flush_ex <= (branch_taken or exception_taken) and not stall_ex;
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flush_ex <= (branch_taken or exception_taken) and not stall_ex;
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------- Control and status module -------
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------- Control and status module -------
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csr_unit: entity work.pp_csr_unit
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csr_unit: entity work.pp_csr_unit
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generic map(
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generic map(
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PROCESSOR_ID => PROCESSOR_ID
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PROCESSOR_ID => PROCESSOR_ID
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) port map(
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) port map(
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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timer_clk => timer_clk,
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timer_clk => timer_clk,
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count_instruction => wb_count_instruction,
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count_instruction => wb_count_instruction,
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fromhost_data => fromhost_data,
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fromhost_data => fromhost_data,
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fromhost_updated => fromhost_write_en,
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fromhost_updated => fromhost_write_en,
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tohost_data => tohost_data,
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tohost_data => tohost_data,
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tohost_updated => tohost_write_en,
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tohost_updated => tohost_write_en,
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read_address => id_csr_address,
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read_address => csr_read_address,
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read_data_out => csr_read_data,
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read_data_out => csr_read_data,
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read_writeable => csr_read_writeable,
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read_writeable => csr_read_writeable,
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write_address => wb_csr_address,
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write_address => wb_csr_address,
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write_data_in => wb_csr_data,
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write_data_in => wb_csr_data,
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write_mode => wb_csr_write,
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write_mode => wb_csr_write,
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exception_context => wb_exception_context,
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exception_context => wb_exception_context,
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exception_context_write => wb_exception,
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exception_context_write => wb_exception,
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status_out => status,
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status_out => status,
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evec_out => evec
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evec_out => evec
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);
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);
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csr_read_address <= id_csr_address when stall_ex = '0' else csr_read_address_p;
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store_previous_csr_addr: process(clk, stall_ex)
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begin
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if rising_edge(clk) and stall_ex = '0' then
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csr_read_address_p <= id_csr_address;
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end if;
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end process store_previous_csr_addr;
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------- Register file -------
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------- Register file -------
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regfile: entity work.pp_register_file
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regfile: entity work.pp_register_file
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port map(
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port map(
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clk => clk,
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clk => clk,
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rs1_addr => rs1_address,
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rs1_addr => rs1_address,
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rs2_addr => rs2_address,
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rs2_addr => rs2_address,
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rs1_data => rs1_data,
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rs1_data => rs1_data,
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rs2_data => rs2_data,
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rs2_data => rs2_data,
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rd_addr => wb_rd_address,
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rd_addr => wb_rd_address,
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rd_data => wb_rd_data,
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rd_data => wb_rd_data,
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rd_write => wb_rd_write
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rd_write => wb_rd_write
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);
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);
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rs1_address <= id_rs1_address when stall_ex = '0' else rs1_address_p;
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rs1_address <= id_rs1_address when stall_ex = '0' else rs1_address_p;
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rs2_address <= id_rs2_address when stall_ex = '0' else rs2_address_p;
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rs2_address <= id_rs2_address when stall_ex = '0' else rs2_address_p;
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|
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store_previous_rsaddr: process(clk, stall_ex)
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store_previous_rsaddr: process(clk, stall_ex)
|
begin
|
begin
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if rising_edge(clk) and stall_ex = '0' then
|
if rising_edge(clk) and stall_ex = '0' then
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rs1_address_p <= id_rs1_address;
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rs1_address_p <= id_rs1_address;
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rs2_address_p <= id_rs2_address;
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rs2_address_p <= id_rs2_address;
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end if;
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end if;
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end process store_previous_rsaddr;
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end process store_previous_rsaddr;
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|
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------- Instruction Fetch (IF) Stage -------
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------- Instruction Fetch (IF) Stage -------
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fetch: entity work.pp_fetch
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fetch: entity work.pp_fetch
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generic map(
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generic map(
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RESET_ADDRESS => RESET_ADDRESS
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RESET_ADDRESS => RESET_ADDRESS
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) port map(
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) port map(
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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imem_address => imem_address,
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imem_address => imem_address,
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imem_data_in => imem_data_in,
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imem_data_in => imem_data_in,
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imem_req => imem_req,
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imem_req => imem_req,
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imem_ack => imem_ack,
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imem_ack => imem_ack,
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stall => stall_if,
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stall => stall_if,
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flush => flush_if,
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flush => flush_if,
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branch => branch_taken,
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branch => branch_taken,
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exception => exception_taken,
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exception => exception_taken,
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branch_target => branch_target,
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branch_target => branch_target,
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evec => exception_target,
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evec => exception_target,
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instruction_data => if_instruction,
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instruction_data => if_instruction,
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instruction_address => if_pc,
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instruction_address => if_pc,
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instruction_ready => if_instruction_ready
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instruction_ready => if_instruction_ready
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);
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);
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if_count_instruction <= if_instruction_ready;
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if_count_instruction <= if_instruction_ready;
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|
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------- Instruction Decode (ID) Stage -------
|
------- Instruction Decode (ID) Stage -------
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decode: entity work.pp_decode
|
decode: entity work.pp_decode
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generic map(
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generic map(
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RESET_ADDRESS => RESET_ADDRESS,
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RESET_ADDRESS => RESET_ADDRESS,
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PROCESSOR_ID => PROCESSOR_ID
|
PROCESSOR_ID => PROCESSOR_ID
|
) port map(
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) port map(
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clk => clk,
|
clk => clk,
|
reset => reset,
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reset => reset,
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flush => flush_id,
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flush => flush_id,
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stall => stall_id,
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stall => stall_id,
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instruction_data => if_instruction,
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instruction_data => if_instruction,
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instruction_address => if_pc,
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instruction_address => if_pc,
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instruction_ready => if_instruction_ready,
|
instruction_ready => if_instruction_ready,
|
instruction_count => if_count_instruction,
|
instruction_count => if_count_instruction,
|
funct3 => id_funct3,
|
funct3 => id_funct3,
|
rs1_addr => id_rs1_address,
|
rs1_addr => id_rs1_address,
|
rs2_addr => id_rs2_address,
|
rs2_addr => id_rs2_address,
|
rd_addr => id_rd_address,
|
rd_addr => id_rd_address,
|
csr_addr => id_csr_address,
|
csr_addr => id_csr_address,
|
shamt => id_shamt,
|
shamt => id_shamt,
|
immediate => id_immediate,
|
immediate => id_immediate,
|
rd_write => id_rd_write,
|
rd_write => id_rd_write,
|
branch => id_branch,
|
branch => id_branch,
|
alu_x_src => id_alu_x_src,
|
alu_x_src => id_alu_x_src,
|
alu_y_src => id_alu_y_src,
|
alu_y_src => id_alu_y_src,
|
alu_op => id_alu_op,
|
alu_op => id_alu_op,
|
mem_op => id_mem_op,
|
mem_op => id_mem_op,
|
mem_size => id_mem_size,
|
mem_size => id_mem_size,
|
count_instruction => id_count_instruction,
|
count_instruction => id_count_instruction,
|
pc => id_pc,
|
pc => id_pc,
|
csr_write => id_csr_write,
|
csr_write => id_csr_write,
|
csr_use_imm => id_csr_use_immediate,
|
csr_use_imm => id_csr_use_immediate,
|
decode_exception => id_exception,
|
decode_exception => id_exception,
|
decode_exception_cause => id_exception_cause
|
decode_exception_cause => id_exception_cause
|
);
|
);
|
|
|
------- Execute (EX) Stage -------
|
------- Execute (EX) Stage -------
|
execute: entity work.pp_execute
|
execute: entity work.pp_execute
|
port map(
|
port map(
|
clk => clk,
|
clk => clk,
|
reset => reset,
|
reset => reset,
|
stall => stall_ex,
|
stall => stall_ex,
|
flush => flush_ex,
|
flush => flush_ex,
|
irq => irq,
|
irq => irq,
|
dmem_address => ex_dmem_address,
|
dmem_address => ex_dmem_address,
|
dmem_data_size => ex_dmem_data_size,
|
dmem_data_size => ex_dmem_data_size,
|
dmem_data_out => ex_dmem_data_out,
|
dmem_data_out => ex_dmem_data_out,
|
dmem_read_req => ex_dmem_read_req,
|
dmem_read_req => ex_dmem_read_req,
|
dmem_write_req => ex_dmem_write_req,
|
dmem_write_req => ex_dmem_write_req,
|
rs1_addr_in => rs1_address,
|
rs1_addr_in => rs1_address,
|
rs2_addr_in => rs2_address,
|
rs2_addr_in => rs2_address,
|
rd_addr_in => id_rd_address,
|
rd_addr_in => id_rd_address,
|
rd_addr_out => ex_rd_address,
|
rd_addr_out => ex_rd_address,
|
rs1_data_in => rs1_data,
|
rs1_data_in => rs1_data,
|
rs2_data_in => rs2_data,
|
rs2_data_in => rs2_data,
|
shamt_in => id_shamt,
|
shamt_in => id_shamt,
|
immediate_in => id_immediate,
|
immediate_in => id_immediate,
|
funct3_in => id_funct3,
|
funct3_in => id_funct3,
|
pc_in => id_pc,
|
pc_in => id_pc,
|
pc_out => ex_pc,
|
pc_out => ex_pc,
|
csr_addr_in => id_csr_address,
|
csr_addr_in => csr_read_address,
|
csr_addr_out => ex_csr_address,
|
csr_addr_out => ex_csr_address,
|
csr_write_in => id_csr_write,
|
csr_write_in => id_csr_write,
|
csr_write_out => ex_csr_write,
|
csr_write_out => ex_csr_write,
|
csr_value_in => csr_read_data,
|
csr_value_in => csr_read_data,
|
csr_value_out => ex_csr_data,
|
csr_value_out => ex_csr_data,
|
csr_writeable_in => csr_read_writeable,
|
csr_writeable_in => csr_read_writeable,
|
csr_use_immediate_in => id_csr_use_immediate,
|
csr_use_immediate_in => id_csr_use_immediate,
|
alu_op_in => id_alu_op,
|
alu_op_in => id_alu_op,
|
alu_x_src_in => id_alu_x_src,
|
alu_x_src_in => id_alu_x_src,
|
alu_y_src_in => id_alu_y_src,
|
alu_y_src_in => id_alu_y_src,
|
rd_write_in => id_rd_write,
|
rd_write_in => id_rd_write,
|
rd_write_out => ex_rd_write,
|
rd_write_out => ex_rd_write,
|
rd_data_out => ex_rd_data,
|
rd_data_out => ex_rd_data,
|
branch_in => id_branch,
|
branch_in => id_branch,
|
branch_out => ex_branch,
|
branch_out => ex_branch,
|
mem_op_in => id_mem_op,
|
mem_op_in => id_mem_op,
|
mem_op_out => ex_mem_op,
|
mem_op_out => ex_mem_op,
|
mem_size_in => id_mem_size,
|
mem_size_in => id_mem_size,
|
mem_size_out => ex_mem_size,
|
mem_size_out => ex_mem_size,
|
count_instruction_in => id_count_instruction,
|
count_instruction_in => id_count_instruction,
|
count_instruction_out => ex_count_instruction,
|
count_instruction_out => ex_count_instruction,
|
status_in => status,
|
status_in => status,
|
evec_in => evec,
|
evec_in => evec,
|
evec_out => exception_target,
|
evec_out => exception_target,
|
decode_exception_in => id_exception,
|
decode_exception_in => id_exception,
|
decode_exception_cause_in => id_exception_cause,
|
decode_exception_cause_in => id_exception_cause,
|
exception_out => exception_taken,
|
exception_out => exception_taken,
|
exception_context_out => ex_exception_context,
|
exception_context_out => ex_exception_context,
|
jump_out => branch_taken,
|
jump_out => branch_taken,
|
jump_target_out => branch_target,
|
jump_target_out => branch_target,
|
mem_rd_write => mem_rd_write,
|
mem_rd_write => mem_rd_write,
|
mem_rd_addr => mem_rd_address,
|
mem_rd_addr => mem_rd_address,
|
mem_rd_value => mem_rd_data,
|
mem_rd_value => mem_rd_data,
|
mem_csr_addr => mem_csr_address,
|
mem_csr_addr => mem_csr_address,
|
mem_csr_value => mem_csr_data,
|
mem_csr_value => mem_csr_data,
|
mem_csr_write => mem_csr_write,
|
mem_csr_write => mem_csr_write,
|
mem_exception => mem_exception,
|
mem_exception => mem_exception,
|
mem_exception_context => mem_exception_context,
|
mem_exception_context => mem_exception_context,
|
wb_rd_write => wb_rd_write,
|
wb_rd_write => wb_rd_write,
|
wb_rd_addr => wb_rd_address,
|
wb_rd_addr => wb_rd_address,
|
wb_rd_value => wb_rd_data,
|
wb_rd_value => wb_rd_data,
|
wb_csr_addr => wb_csr_address,
|
wb_csr_addr => wb_csr_address,
|
wb_csr_value => wb_csr_data,
|
wb_csr_value => wb_csr_data,
|
wb_csr_write => wb_csr_write,
|
wb_csr_write => wb_csr_write,
|
wb_exception => wb_exception,
|
wb_exception => wb_exception,
|
wb_exception_context => wb_exception_context,
|
wb_exception_context => wb_exception_context,
|
mem_mem_op => mem_mem_op,
|
mem_mem_op => mem_mem_op,
|
hazard_detected => load_hazard_detected
|
hazard_detected => load_hazard_detected
|
);
|
);
|
|
|
dmem_address <= ex_dmem_address when stall_mem = '0' else dmem_address_p;
|
dmem_address <= ex_dmem_address when stall_mem = '0' else dmem_address_p;
|
dmem_data_size <= ex_dmem_data_size when stall_mem = '0' else dmem_data_size_p;
|
dmem_data_size <= ex_dmem_data_size when stall_mem = '0' else dmem_data_size_p;
|
dmem_data_out <= ex_dmem_data_out when stall_mem = '0' else dmem_data_out_p;
|
dmem_data_out <= ex_dmem_data_out when stall_mem = '0' else dmem_data_out_p;
|
dmem_read_req <= ex_dmem_read_req when stall_mem = '0' else dmem_read_req_p;
|
dmem_read_req <= ex_dmem_read_req when stall_mem = '0' else dmem_read_req_p;
|
dmem_write_req <= ex_dmem_write_req when stall_mem = '0' else dmem_write_req_p;
|
dmem_write_req <= ex_dmem_write_req when stall_mem = '0' else dmem_write_req_p;
|
|
|
store_previous_dmem_address: process(clk, stall_mem)
|
store_previous_dmem_address: process(clk, stall_mem)
|
begin
|
begin
|
if rising_edge(clk) and stall_mem = '0' then
|
if rising_edge(clk) and stall_mem = '0' then
|
dmem_address_p <= ex_dmem_address;
|
dmem_address_p <= ex_dmem_address;
|
dmem_data_size_p <= ex_dmem_data_size;
|
dmem_data_size_p <= ex_dmem_data_size;
|
dmem_data_out_p <= ex_dmem_data_out;
|
dmem_data_out_p <= ex_dmem_data_out;
|
dmem_read_req_p <= ex_dmem_read_req;
|
dmem_read_req_p <= ex_dmem_read_req;
|
dmem_write_req_p <= ex_dmem_write_req;
|
dmem_write_req_p <= ex_dmem_write_req;
|
end if;
|
end if;
|
end process store_previous_dmem_address;
|
end process store_previous_dmem_address;
|
|
|
------- Memory (MEM) Stage -------
|
------- Memory (MEM) Stage -------
|
memory: entity work.pp_memory
|
memory: entity work.pp_memory
|
port map(
|
port map(
|
clk => clk,
|
clk => clk,
|
reset => reset,
|
reset => reset,
|
stall => stall_mem,
|
stall => stall_mem,
|
dmem_data_in => dmem_data_in,
|
dmem_data_in => dmem_data_in,
|
dmem_read_ack => dmem_read_ack,
|
dmem_read_ack => dmem_read_ack,
|
dmem_write_ack => dmem_write_ack,
|
dmem_write_ack => dmem_write_ack,
|
pc => ex_pc,
|
pc => ex_pc,
|
rd_write_in => ex_rd_write,
|
rd_write_in => ex_rd_write,
|
rd_write_out => mem_rd_write,
|
rd_write_out => mem_rd_write,
|
rd_data_in => ex_rd_data,
|
rd_data_in => ex_rd_data,
|
rd_data_out => mem_rd_data,
|
rd_data_out => mem_rd_data,
|
rd_addr_in => ex_rd_address,
|
rd_addr_in => ex_rd_address,
|
rd_addr_out => mem_rd_address,
|
rd_addr_out => mem_rd_address,
|
branch => ex_branch,
|
branch => ex_branch,
|
mem_op_in => ex_mem_op,
|
mem_op_in => ex_mem_op,
|
mem_op_out => mem_mem_op,
|
mem_op_out => mem_mem_op,
|
mem_size_in => ex_mem_size,
|
mem_size_in => ex_mem_size,
|
count_instr_in => ex_count_instruction,
|
count_instr_in => ex_count_instruction,
|
count_instr_out => mem_count_instruction,
|
count_instr_out => mem_count_instruction,
|
exception_in => exception_taken,
|
exception_in => exception_taken,
|
exception_out => mem_exception,
|
exception_out => mem_exception,
|
exception_context_in => ex_exception_context,
|
exception_context_in => ex_exception_context,
|
exception_context_out => mem_exception_context,
|
exception_context_out => mem_exception_context,
|
csr_addr_in => ex_csr_address,
|
csr_addr_in => ex_csr_address,
|
csr_addr_out => mem_csr_address,
|
csr_addr_out => mem_csr_address,
|
csr_write_in => ex_csr_write,
|
csr_write_in => ex_csr_write,
|
csr_write_out => mem_csr_write,
|
csr_write_out => mem_csr_write,
|
csr_data_in => ex_csr_data,
|
csr_data_in => ex_csr_data,
|
csr_data_out => mem_csr_data
|
csr_data_out => mem_csr_data
|
);
|
);
|
|
|
------- Writeback (WB) Stage -------
|
------- Writeback (WB) Stage -------
|
writeback: entity work.pp_writeback
|
writeback: entity work.pp_writeback
|
port map(
|
port map(
|
clk => clk,
|
clk => clk,
|
reset => reset,
|
reset => reset,
|
count_instr_in => mem_count_instruction,
|
count_instr_in => mem_count_instruction,
|
count_instr_out => wb_count_instruction,
|
count_instr_out => wb_count_instruction,
|
exception_ctx_in => mem_exception_context,
|
exception_ctx_in => mem_exception_context,
|
exception_ctx_out => wb_exception_context,
|
exception_ctx_out => wb_exception_context,
|
exception_in => mem_exception,
|
exception_in => mem_exception,
|
exception_out => wb_exception,
|
exception_out => wb_exception,
|
csr_write_in => mem_csr_write,
|
csr_write_in => mem_csr_write,
|
csr_write_out => wb_csr_write,
|
csr_write_out => wb_csr_write,
|
csr_data_in => mem_csr_data,
|
csr_data_in => mem_csr_data,
|
csr_data_out => wb_csr_data,
|
csr_data_out => wb_csr_data,
|
csr_addr_in => mem_csr_address,
|
csr_addr_in => mem_csr_address,
|
csr_addr_out => wb_csr_address,
|
csr_addr_out => wb_csr_address,
|
rd_addr_in => mem_rd_address,
|
rd_addr_in => mem_rd_address,
|
rd_addr_out => wb_rd_address,
|
rd_addr_out => wb_rd_address,
|
rd_write_in => mem_rd_write,
|
rd_write_in => mem_rd_write,
|
rd_write_out => wb_rd_write,
|
rd_write_out => wb_rd_write,
|
rd_data_in => mem_rd_data,
|
rd_data_in => mem_rd_data,
|
rd_data_out => wb_rd_data
|
rd_data_out => wb_rd_data
|
);
|
);
|
|
|
end architecture behaviour;
|
end architecture behaviour;
|
|
|
|
|
