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[/] [potato/] [trunk/] [src/] [pp_counter.vhd] - Diff between revs 2 and 3
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-- The Potato Processor - A simple processor for FPGAs
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-- The Potato Processor - A simple processor for FPGAs
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-- (c) Kristian Klomsten Skordal 2014 -2015 <kristian.skordal@wafflemail.net>
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-- (c) Kristian Klomsten Skordal 2014 -2015 <kristian.skordal@wafflemail.net>
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-- Report bugs and issues on <https://github.com/skordal/potato/issues>
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-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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entity pp_counter is
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entity pp_counter is
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generic(
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generic(
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COUNTER_WIDTH : natural := 64;
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COUNTER_WIDTH : natural := 64;
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COUNTER_STEP : natural := 1
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COUNTER_STEP : natural := 1
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);
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);
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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count : out std_logic_vector(COUNTER_WIDTH - 1 downto 0);
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count : out std_logic_vector(COUNTER_WIDTH - 1 downto 0);
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increment : in std_logic
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increment : in std_logic
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);
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);
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end entity pp_counter;
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end entity pp_counter;
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architecture behaviour of pp_counter is
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architecture behaviour of pp_counter is
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signal current_count : std_logic_vector(COUNTER_WIDTH - 1 downto 0);
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signal current_count : std_logic_vector(COUNTER_WIDTH - 1 downto 0);
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begin
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begin
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count <= current_count;
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count <= current_count;
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counter: process(clk)
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counter: process(clk)
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if reset = '1' then
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if reset = '1' then
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current_count <= (others => '0');
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current_count <= (others => '0');
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elsif increment = '1' then
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elsif increment = '1' then
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current_count <= std_logic_vector(unsigned(current_count) + COUNTER_STEP);
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current_count <= std_logic_vector(unsigned(current_count) + COUNTER_STEP);
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end if;
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end if;
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end if;
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end if;
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end process counter;
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end process counter;
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end architecture behaviour;
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end architecture behaviour;
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