-- The Potato Processor - A simple processor for FPGAs
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-- The Potato Processor - A simple processor for FPGAs
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-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
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-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
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-- Report bugs and issues on <https://github.com/skordal/potato/issues>
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-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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--! @brief Package containing constants and utility functions relating to status and control registers.
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--! @brief Package containing constants and utility functions relating to status and control registers.
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package pp_csr is
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package pp_csr is
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--! Type used for specifying control and status register addresses.
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--! Type used for specifying control and status register addresses.
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subtype csr_address is std_logic_vector(11 downto 0);
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subtype csr_address is std_logic_vector(11 downto 0);
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--! Type used for exception cause values.
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--! Type used for exception cause values.
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subtype csr_exception_cause is std_logic_vector(4 downto 0);
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subtype csr_exception_cause is std_logic_vector(4 downto 0);
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function to_std_logic_vector(input : in csr_exception_cause) return std_logic_vector;
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function to_std_logic_vector(input : in csr_exception_cause) return std_logic_vector;
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--! Control/status register write mode:
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--! Control/status register write mode:
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type csr_write_mode is (
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type csr_write_mode is (
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CSR_WRITE_NONE, CSR_WRITE_SET, CSR_WRITE_CLEAR, CSR_WRITE_REPLACE
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CSR_WRITE_NONE, CSR_WRITE_SET, CSR_WRITE_CLEAR, CSR_WRITE_REPLACE
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);
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);
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-- Exception cause values:
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-- Exception cause values:
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constant CSR_CAUSE_INSTR_MISALIGN : csr_exception_cause := b"00000";
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constant CSR_CAUSE_INSTR_MISALIGN : csr_exception_cause := b"00000";
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constant CSR_CAUSE_INSTR_FETCH : csr_exception_cause := b"00001";
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constant CSR_CAUSE_INSTR_FETCH : csr_exception_cause := b"00001";
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constant CSR_CAUSE_INVALID_INSTR : csr_exception_cause := b"00010";
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constant CSR_CAUSE_INVALID_INSTR : csr_exception_cause := b"00010";
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constant CSR_CAUSE_SYSCALL : csr_exception_cause := b"00110";
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constant CSR_CAUSE_SYSCALL : csr_exception_cause := b"00110";
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constant CSR_CAUSE_BREAKPOINT : csr_exception_cause := b"00111";
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constant CSR_CAUSE_BREAKPOINT : csr_exception_cause := b"00111";
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constant CSR_CAUSE_LOAD_MISALIGN : csr_exception_cause := b"01000";
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constant CSR_CAUSE_LOAD_MISALIGN : csr_exception_cause := b"01000";
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constant CSR_CAUSE_STORE_MISALIGN : csr_exception_cause := b"01001";
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constant CSR_CAUSE_STORE_MISALIGN : csr_exception_cause := b"01001";
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constant CSR_CAUSE_LOAD_ERROR : csr_exception_cause := b"01010";
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constant CSR_CAUSE_LOAD_ERROR : csr_exception_cause := b"01010";
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constant CSR_CAUSE_STORE_ERROR : csr_exception_cause := b"01011";
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constant CSR_CAUSE_STORE_ERROR : csr_exception_cause := b"01011";
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constant CSR_CAUSE_FROMHOST : csr_exception_cause := b"11110";
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constant CSR_CAUSE_FROMHOST : csr_exception_cause := b"11110";
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constant CSR_CAUSE_NONE : csr_exception_cause := b"11111";
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constant CSR_CAUSE_NONE : csr_exception_cause := b"11111";
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constant CSR_CAUSE_IRQ_BASE : csr_exception_cause := b"10000";
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constant CSR_CAUSE_IRQ_BASE : csr_exception_cause := b"10000";
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-- Control register IDs, specified in the immediate of csr* instructions:
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-- Control register IDs, specified in the immediate of csr* instructions:
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constant CSR_STATUS : csr_address := x"50a";
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constant CSR_STATUS : csr_address := x"50a";
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constant CSR_HARTID : csr_address := x"50b";
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constant CSR_HARTID : csr_address := x"50b";
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constant CSR_SUP0 : csr_address := x"500";
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constant CSR_SUP0 : csr_address := x"500";
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constant CSR_SUP1 : csr_address := x"501";
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constant CSR_SUP1 : csr_address := x"501";
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constant CSR_BADVADDR : csr_address := x"503";
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constant CSR_BADVADDR : csr_address := x"503";
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constant CSR_TOHOST : csr_address := x"51e";
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constant CSR_TOHOST : csr_address := x"51e";
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constant CSR_FROMHOST : csr_address := x"51f";
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constant CSR_FROMHOST : csr_address := x"51f";
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constant CSR_CYCLE : csr_address := x"c00";
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constant CSR_CYCLE : csr_address := x"c00";
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constant CSR_CYCLEH : csr_address := x"c80";
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constant CSR_CYCLEH : csr_address := x"c80";
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constant CSR_TIME : csr_address := x"c01";
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constant CSR_TIME : csr_address := x"c01";
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constant CSR_TIMEH : csr_address := x"c81";
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constant CSR_TIMEH : csr_address := x"c81";
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constant CSR_INSTRET : csr_address := x"c02";
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constant CSR_INSTRET : csr_address := x"c02";
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constant CSR_INSTRETH : csr_address := x"c82";
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constant CSR_INSTRETH : csr_address := x"c82";
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constant CSR_EPC : csr_address := x"502";
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constant CSR_EPC : csr_address := x"502";
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constant CSR_EVEC : csr_address := x"508";
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constant CSR_EVEC : csr_address := x"508";
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constant CSR_CAUSE : csr_address := x"509";
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constant CSR_CAUSE : csr_address := x"509";
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-- Values used as control register IDs in SRET, SCALL and SBREAK:
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-- Values used as control register IDs in SRET, SCALL and SBREAK:
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constant CSR_EPC_SRET : csr_address := x"800";
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constant CSR_EPC_SRET : csr_address := x"800";
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-- Status register bit indices:
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-- Status register bit indices:
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constant CSR_SR_S : natural := 0;
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constant CSR_SR_S : natural := 0;
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constant CSR_SR_PS : natural := 1;
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constant CSR_SR_PS : natural := 1;
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constant CSR_SR_EI : natural := 2;
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constant CSR_SR_EI : natural := 2;
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constant CSR_SR_PEI : natural := 3;
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constant CSR_SR_PEI : natural := 3;
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-- Status register in Potato:
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-- Status register in Potato:
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-- * Bit 0, S: Supervisor mode, always 1
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-- * Bit 0, S: Supervisor mode, always 1
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-- * Bit 1, PS: Previous supervisor mode bit, always 1
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-- * Bit 1, PS: Previous supervisor mode bit, always 1
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-- * Bit 2, EI: Enable interrupts bit
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-- * Bit 2, EI: Enable interrupts bit
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-- * Bit 3, PEI: Previous enable interrupts bit
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-- * Bit 3, PEI: Previous enable interrupts bit
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-- * Bits 23 downto 16, IM: Interrupt mask
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-- * Bits 23 downto 16, IM: Interrupt mask
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-- * Bits 31 downto 24, PIM: Previous interrupt mask
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-- * Bits 31 downto 24, PIM: Previous interrupt mask
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-- Status register record:
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-- Status register record:
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type csr_status_register is
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type csr_status_register is
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record
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record
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ei, pei : std_logic;
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ei, pei : std_logic;
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im, pim : std_logic_vector(7 downto 0);
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im, pim : std_logic_vector(7 downto 0);
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end record;
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end record;
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-- Exception context; this record contains all state that is stored
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-- Exception context; this record contains all state that is stored
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-- when an exception is taken.
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-- when an exception is taken.
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type csr_exception_context is
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type csr_exception_context is
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record
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record
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status : csr_status_register;
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status : csr_status_register;
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cause : csr_exception_cause;
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cause : csr_exception_cause;
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badvaddr : std_logic_vector(31 downto 0);
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badvaddr : std_logic_vector(31 downto 0);
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end record;
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end record;
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-- Reset value of the status register:
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-- Reset value of the status register:
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constant CSR_SR_DEFAULT : csr_status_register := (ei => '0', pei => '0', im => x"00", pim => x"00");
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constant CSR_SR_DEFAULT : csr_status_register := (ei => '0', pei => '0', im => x"00", pim => x"00");
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-- Converts a status register record into an std_logic_vector:
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-- Converts a status register record into an std_logic_vector:
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function to_std_logic_vector(input : in csr_status_register)
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function to_std_logic_vector(input : in csr_status_register)
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return std_logic_vector;
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return std_logic_vector;
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-- Converts an std_logic_vector into a status register record:
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-- Converts an std_logic_vector into a status register record:
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function to_csr_status_register(input : in std_logic_vector(31 downto 0))
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function to_csr_status_register(input : in std_logic_vector(31 downto 0))
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return csr_status_register;
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return csr_status_register;
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--! Checks if a control register is writeable.
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--! Checks if a control register is writeable.
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function csr_is_writeable(csr : in csr_address) return boolean;
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function csr_is_writeable(csr : in csr_address) return boolean;
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end package pp_csr;
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end package pp_csr;
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package body pp_csr is
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package body pp_csr is
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function to_std_logic_vector(input : in csr_exception_cause)
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function to_std_logic_vector(input : in csr_exception_cause)
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return std_logic_vector is
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return std_logic_vector is
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begin
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begin
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return (31 downto 5 => '0') & input;
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return (31 downto 5 => '0') & input;
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end function to_std_logic_vector;
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end function to_std_logic_vector;
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function to_std_logic_vector(input : in csr_status_register)
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function to_std_logic_vector(input : in csr_status_register)
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return std_logic_vector is
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return std_logic_vector is
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begin
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begin
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return input.pim & input.im & (15 downto 4 => '0') & input.pei & input.ei & '1' & '1';
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return input.pim & input.im & (15 downto 4 => '0') & input.pei & input.ei & '1' & '1';
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end function to_std_logic_vector;
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end function to_std_logic_vector;
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function to_csr_status_register(input : in std_logic_vector(31 downto 0))
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function to_csr_status_register(input : in std_logic_vector(31 downto 0))
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return csr_status_register
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return csr_status_register
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is
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is
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variable retval : csr_status_register;
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variable retval : csr_status_register;
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begin
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begin
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retval.ei := input(CSR_SR_EI);
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retval.ei := input(CSR_SR_EI);
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retval.pei := input(CSR_SR_PEI);
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retval.pei := input(CSR_SR_PEI);
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retval.im := input(23 downto 16);
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retval.im := input(23 downto 16);
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retval.pim := input(31 downto 24);
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retval.pim := input(31 downto 24);
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return retval;
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return retval;
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end function to_csr_status_register;
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end function to_csr_status_register;
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function csr_is_writeable(csr : in csr_address) return boolean is
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function csr_is_writeable(csr : in csr_address) return boolean is
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begin
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begin
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case csr is
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case csr is
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when CSR_FROMHOST | CSR_CYCLE | CSR_CYCLEH | CSR_HARTID
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when CSR_FROMHOST | CSR_CYCLE | CSR_CYCLEH | CSR_HARTID
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| CSR_TIME | CSR_TIMEH | CSR_INSTRET | CSR_INSTRETH
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| CSR_TIME | CSR_TIMEH | CSR_INSTRET | CSR_INSTRETH
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| CSR_CAUSE | CSR_BADVADDR =>
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| CSR_CAUSE | CSR_BADVADDR =>
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return false;
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return false;
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when others =>
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when others =>
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return true;
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return true;
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end case;
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end case;
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end function csr_is_writeable;
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end function csr_is_writeable;
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end package body pp_csr;
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end package body pp_csr;
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