-- The Potato Processor - A simple processor for FPGAs
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-- The Potato Processor - A simple processor for FPGAs
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-- (c) Kristian Klomsten Skordal 2014 <kristian.skordal@wafflemail.net>
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-- (c) Kristian Klomsten Skordal 2014 <kristian.skordal@wafflemail.net>
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-- Report bugs and issues on <https://github.com/skordal/potato/issues>
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-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.pp_csr.all;
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use work.pp_csr.all;
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--! @brief ALU used for calculating new values of control and status registers.
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--! @brief ALU used for calculating new values of control and status registers.
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entity pp_csr_alu is
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entity pp_csr_alu is
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port(
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port(
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x, y : in std_logic_vector(31 downto 0);
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x, y : in std_logic_vector(31 downto 0);
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result : out std_logic_vector(31 downto 0);
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result : out std_logic_vector(31 downto 0);
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immediate : in std_logic_vector(4 downto 0);
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immediate : in std_logic_vector(4 downto 0);
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use_immediate : in std_logic;
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use_immediate : in std_logic;
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write_mode : in csr_write_mode
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write_mode : in csr_write_mode
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);
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);
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end entity pp_csr_alu;
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end entity pp_csr_alu;
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architecture behaviour of pp_csr_alu is
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architecture behaviour of pp_csr_alu is
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signal a, b : std_logic_vector(31 downto 0);
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signal a, b : std_logic_vector(31 downto 0);
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begin
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begin
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a <= x;
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a <= x;
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b <= y when use_immediate = '0' else std_logic_vector(resize(unsigned(immediate), b'length));
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b <= y when use_immediate = '0' else std_logic_vector(resize(unsigned(immediate), b'length));
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calculate: process(a, b, write_mode)
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calculate: process(a, b, write_mode)
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begin
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begin
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case write_mode is
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case write_mode is
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when CSR_WRITE_NONE =>
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when CSR_WRITE_NONE =>
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result <= a;
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result <= a;
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when CSR_WRITE_SET =>
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when CSR_WRITE_SET =>
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result <= a or b;
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result <= a or b;
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when CSR_WRITE_CLEAR =>
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when CSR_WRITE_CLEAR =>
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result <= a and (not b);
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result <= a and (not b);
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when CSR_WRITE_REPLACE =>
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when CSR_WRITE_REPLACE =>
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result <= b;
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result <= b;
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end case;
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end case;
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end process calculate;
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end process calculate;
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end architecture behaviour;
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end architecture behaviour;
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