-- The Potato Processor - A simple processor for FPGAs
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-- The Potato Processor - A simple processor for FPGAs
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-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
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-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
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-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
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-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.pp_csr.all;
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use work.pp_csr.all;
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entity pp_csr_unit is
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entity pp_csr_unit is
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generic(
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generic(
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PROCESSOR_ID : std_logic_vector(31 downto 0)
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PROCESSOR_ID : std_logic_vector(31 downto 0)
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);
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);
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port(
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port(
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clk, timer_clk : in std_logic;
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clk, timer_clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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-- Count retired instruction:
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-- Count retired instruction:
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count_instruction : in std_logic;
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count_instruction : in std_logic;
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-- HTIF interface:
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-- HTIF interface:
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fromhost_data : in std_logic_vector(31 downto 0);
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fromhost_data : in std_logic_vector(31 downto 0);
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fromhost_updated : in std_logic;
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fromhost_updated : in std_logic;
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tohost_data : out std_logic_vector(31 downto 0);
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tohost_data : out std_logic_vector(31 downto 0);
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tohost_updated : out std_logic;
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tohost_updated : out std_logic;
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-- Read port:
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-- Read port:
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read_address : in csr_address;
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read_address : in csr_address;
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read_data_out : out std_logic_vector(31 downto 0);
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read_data_out : out std_logic_vector(31 downto 0);
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read_writeable : out boolean;
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read_writeable : out boolean;
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-- Write port:
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-- Write port:
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write_address : in csr_address;
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write_address : in csr_address;
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write_data_in : in std_logic_vector(31 downto 0);
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write_data_in : in std_logic_vector(31 downto 0);
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write_mode : in csr_write_mode;
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write_mode : in csr_write_mode;
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-- Exception context write port:
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-- Exception context write port:
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exception_context : in csr_exception_context;
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exception_context : in csr_exception_context;
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exception_context_write : in std_logic;
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exception_context_write : in std_logic;
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-- Registers needed for exception handling, always read:
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-- Registers needed for exception handling, always read:
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status_out : out csr_status_register;
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status_out : out csr_status_register;
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evec_out : out std_logic_vector(31 downto 0)
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evec_out : out std_logic_vector(31 downto 0)
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);
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);
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end entity pp_csr_unit;
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end entity pp_csr_unit;
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architecture behaviour of pp_csr_unit is
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architecture behaviour of pp_csr_unit is
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-- Implemented counters:
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-- Implemented counters:
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signal counter_time : std_logic_vector(63 downto 0);
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signal counter_time : std_logic_vector(63 downto 0);
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signal counter_cycle : std_logic_vector(63 downto 0);
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signal counter_cycle : std_logic_vector(63 downto 0);
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signal counter_instret : std_logic_vector(63 downto 0);
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signal counter_instret : std_logic_vector(63 downto 0);
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-- Implemented registers:
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-- Implemented registers:
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signal sup0, sup1 : std_logic_vector(31 downto 0) := (others => '0');
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signal sup0, sup1 : std_logic_vector(31 downto 0) := (others => '0');
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signal epc, evec : std_logic_vector(31 downto 0) := (others => '0');
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signal epc, evec : std_logic_vector(31 downto 0) := (others => '0');
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signal badvaddr : std_logic_vector(31 downto 0) := (others => '0');
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signal badvaddr : std_logic_vector(31 downto 0) := (others => '0');
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signal cause : csr_exception_cause;
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signal cause : csr_exception_cause;
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-- HTIF FROMHOST register:
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-- HTIF FROMHOST register:
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signal fromhost: std_logic_vector(31 downto 0);
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signal fromhost: std_logic_vector(31 downto 0);
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-- Status register:
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-- Status register:
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signal status_register : csr_status_register;
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signal status_register : csr_status_register;
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begin
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begin
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read_writeable <= csr_is_writeable(read_address);
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read_writeable <= csr_is_writeable(read_address);
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--! Updates the FROMHOST register when new data is available.
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--! Updates the FROMHOST register when new data is available.
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htif_fromhost: process(clk)
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htif_fromhost: process(clk)
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if fromhost_updated = '1' then
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if fromhost_updated = '1' then
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fromhost <= fromhost_data;
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fromhost <= fromhost_data;
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end if;
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end if;
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end if;
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end if;
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end process htif_fromhost;
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end process htif_fromhost;
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--! Sends a word to the host over the HTIF interface.
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--! Sends a word to the host over the HTIF interface.
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htif_tohost: process(clk)
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htif_tohost: process(clk)
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if reset = '1' then
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if reset = '1' then
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tohost_data <= (others => '0');
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tohost_data <= (others => '0');
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tohost_updated <= '0';
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tohost_updated <= '0';
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else
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else
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if write_mode /= CSR_WRITE_NONE and write_address = CSR_TOHOST then
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if write_mode /= CSR_WRITE_NONE and write_address = CSR_TOHOST then
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tohost_data <= write_data_in;
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tohost_data <= write_data_in;
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tohost_updated <= '1';
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tohost_updated <= '1';
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else
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else
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tohost_updated <= '0';
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tohost_updated <= '0';
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process htif_tohost;
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end process htif_tohost;
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write: process(clk)
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write: process(clk)
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if reset = '1' then
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if reset = '1' then
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status_register <= CSR_SR_DEFAULT;
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status_register <= CSR_SR_DEFAULT;
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else
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else
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if exception_context_write = '1' then
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if exception_context_write = '1' then
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status_register <= exception_context.status;
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status_register <= exception_context.status;
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cause <= exception_context.cause;
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cause <= exception_context.cause;
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badvaddr <= exception_context.badvaddr;
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badvaddr <= exception_context.badvaddr;
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end if;
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end if;
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if write_mode /= CSR_WRITE_NONE then
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if write_mode /= CSR_WRITE_NONE then
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case write_address is
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case write_address is
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when CSR_STATUS =>
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when CSR_STATUS =>
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if exception_context_write = '0' then
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if exception_context_write = '0' then
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status_register <= to_csr_status_register(write_data_in);
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status_register <= to_csr_status_register(write_data_in);
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end if;
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end if;
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when CSR_EPC =>
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when CSR_EPC =>
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epc <= write_data_in;
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epc <= write_data_in;
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when CSR_EVEC =>
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when CSR_EVEC =>
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evec <= write_data_in;
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evec <= write_data_in;
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when CSR_SUP0 =>
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when CSR_SUP0 =>
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sup0 <= write_data_in;
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sup0 <= write_data_in;
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when CSR_SUP1 =>
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when CSR_SUP1 =>
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sup1 <= write_data_in;
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sup1 <= write_data_in;
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when others =>
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when others =>
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-- Ignore writes to invalid or read-only registers
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-- Ignore writes to invalid or read-only registers
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process write;
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end process write;
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status_out <= exception_context.status when exception_context_write = '1' else status_register;
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read: process(clk)
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read: process(clk)
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if exception_context_write = '1' then
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--if exception_context_write = '1' then
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status_out <= exception_context.status;
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-- status_out <= exception_context.status;
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else
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--else
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status_out <= status_register;
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-- status_out <= status_register;
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end if;
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--end if;
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if write_mode /= CSR_WRITE_NONE and write_address = CSR_EVEC then
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if write_mode /= CSR_WRITE_NONE and write_address = CSR_EVEC then
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evec_out <= write_data_in;
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evec_out <= write_data_in;
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else
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else
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evec_out <= evec;
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evec_out <= evec;
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end if;
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end if;
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if write_mode /= CSR_WRITE_NONE and write_address = read_address then
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if write_mode /= CSR_WRITE_NONE and write_address = read_address then
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read_data_out <= write_data_in;
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read_data_out <= write_data_in;
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else
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else
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case read_address is
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case read_address is
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-- Status and control registers:
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-- Status and control registers:
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when CSR_STATUS => -- Status register
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when CSR_STATUS => -- Status register
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read_data_out <= to_std_logic_vector(status_register);
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read_data_out <= to_std_logic_vector(status_register);
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when CSR_HARTID => -- Processor ID
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when CSR_HARTID => -- Processor ID
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read_data_out <= PROCESSOR_ID;
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read_data_out <= PROCESSOR_ID;
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when CSR_FROMHOST => -- Fromhost data
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when CSR_FROMHOST => -- Fromhost data
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read_data_out <= fromhost;
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read_data_out <= fromhost;
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when CSR_EPC | CSR_EPC_SRET => -- Exception PC value
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when CSR_EPC | CSR_EPC_SRET => -- Exception PC value
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read_data_out <= epc;
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read_data_out <= epc;
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when CSR_EVEC => -- Exception handler address
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when CSR_EVEC => -- Exception handler address
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read_data_out <= evec;
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read_data_out <= evec;
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when CSR_CAUSE => -- Exception cause
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when CSR_CAUSE => -- Exception cause
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read_data_out <= to_std_logic_vector(cause);
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read_data_out <= to_std_logic_vector(cause);
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when CSR_BADVADDR => -- Load/store address responsible for the exception
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when CSR_BADVADDR => -- Load/store address responsible for the exception
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read_data_out <= badvaddr;
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read_data_out <= badvaddr;
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-- Supporting registers:
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-- Supporting registers:
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when CSR_SUP0 =>
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when CSR_SUP0 =>
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read_data_out <= sup0;
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read_data_out <= sup0;
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when CSR_SUP1 =>
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when CSR_SUP1 =>
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read_data_out <= sup1;
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read_data_out <= sup1;
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-- Timers and counters:
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-- Timers and counters:
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when CSR_TIME =>
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when CSR_TIME =>
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read_data_out <= counter_time(31 downto 0);
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read_data_out <= counter_time(31 downto 0);
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when CSR_TIMEH =>
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when CSR_TIMEH =>
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read_data_out <= counter_time(63 downto 32);
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read_data_out <= counter_time(63 downto 32);
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when CSR_CYCLE =>
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when CSR_CYCLE =>
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read_data_out <= counter_cycle(31 downto 0);
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read_data_out <= counter_cycle(31 downto 0);
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when CSR_CYCLEH =>
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when CSR_CYCLEH =>
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read_data_out <= counter_cycle(63 downto 32);
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read_data_out <= counter_cycle(63 downto 32);
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when CSR_INSTRET =>
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when CSR_INSTRET =>
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read_data_out <= counter_instret(31 downto 0);
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read_data_out <= counter_instret(31 downto 0);
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when CSR_INSTRETH =>
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when CSR_INSTRETH =>
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read_data_out <= counter_instret(63 downto 32);
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read_data_out <= counter_instret(63 downto 32);
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-- Return zero from write-only registers and invalid register addresses:
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-- Return zero from write-only registers and invalid register addresses:
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when others =>
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when others =>
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read_data_out <= (others => '0');
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read_data_out <= (others => '0');
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end process read;
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end process read;
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timer_counter: entity work.pp_counter
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timer_counter: entity work.pp_counter
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port map(
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port map(
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clk => timer_clk,
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clk => timer_clk,
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reset => reset,
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reset => reset,
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count => counter_time,
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count => counter_time,
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increment => '1'
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increment => '1'
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);
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);
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cycle_counter: entity work.pp_counter
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cycle_counter: entity work.pp_counter
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port map(
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port map(
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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count => counter_cycle,
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count => counter_cycle,
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increment => '1'
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increment => '1'
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);
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);
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instret_counter: entity work.pp_counter
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instret_counter: entity work.pp_counter
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port map(
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port map(
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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count => counter_instret,
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count => counter_instret,
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increment => count_instruction
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increment => count_instruction
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);
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);
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end architecture behaviour;
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end architecture behaviour;
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