-- The Potato Processor - A simple processor for FPGAs
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-- The Potato Processor - A simple processor for FPGAs
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-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
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-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
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-- Report bugs and issues on <https://github.com/skordal/potato/issues>
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-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.pp_types.all;
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use work.pp_types.all;
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use work.pp_constants.all;
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use work.pp_constants.all;
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use work.pp_csr.all;
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use work.pp_csr.all;
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--! @brief Instruction decode unit.
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--! @brief Instruction decode unit.
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entity pp_decode is
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entity pp_decode is
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generic(
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generic(
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RESET_ADDRESS : std_logic_vector(31 downto 0);
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RESET_ADDRESS : std_logic_vector(31 downto 0);
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PROCESSOR_ID : std_logic_vector(31 downto 0)
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PROCESSOR_ID : std_logic_vector(31 downto 0)
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);
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);
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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flush : in std_logic;
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flush : in std_logic;
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stall : in std_logic;
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stall : in std_logic;
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-- Instruction input:
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-- Instruction input:
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instruction_data : in std_logic_vector(31 downto 0);
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instruction_data : in std_logic_vector(31 downto 0);
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instruction_address : in std_logic_vector(31 downto 0);
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instruction_address : in std_logic_vector(31 downto 0);
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instruction_ready : in std_logic;
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instruction_ready : in std_logic;
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instruction_count : in std_logic;
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instruction_count : in std_logic;
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-- Register addresses:
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-- Register addresses:
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rs1_addr, rs2_addr, rd_addr : out register_address;
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rs1_addr, rs2_addr, rd_addr : out register_address;
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csr_addr : out csr_address;
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csr_addr : out csr_address;
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-- Shamt value for shift operations:
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-- Shamt value for shift operations:
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shamt : out std_logic_vector(4 downto 0);
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shamt : out std_logic_vector(4 downto 0);
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funct3 : out std_logic_vector(2 downto 0);
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funct3 : out std_logic_vector(2 downto 0);
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-- Immediate value for immediate instructions:
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-- Immediate value for immediate instructions:
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immediate : out std_logic_vector(31 downto 0);
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immediate : out std_logic_vector(31 downto 0);
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-- Control signals:
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-- Control signals:
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rd_write : out std_logic;
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rd_write : out std_logic;
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branch : out branch_type;
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branch : out branch_type;
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alu_x_src : out alu_operand_source;
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alu_x_src : out alu_operand_source;
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alu_y_src : out alu_operand_source;
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alu_y_src : out alu_operand_source;
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alu_op : out alu_operation;
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alu_op : out alu_operation;
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mem_op : out memory_operation_type;
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mem_op : out memory_operation_type;
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mem_size : out memory_operation_size;
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mem_size : out memory_operation_size;
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count_instruction : out std_logic;
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count_instruction : out std_logic;
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-- Instruction address:
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-- Instruction address:
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pc : out std_logic_vector(31 downto 0);
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pc : out std_logic_vector(31 downto 0);
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-- CSR control signals:
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-- CSR control signals:
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csr_write : out csr_write_mode;
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csr_write : out csr_write_mode;
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csr_use_imm : out std_logic;
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csr_use_imm : out std_logic;
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-- Exception output signals:
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-- Exception output signals:
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decode_exception : out std_logic;
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decode_exception : out std_logic;
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decode_exception_cause : out csr_exception_cause
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decode_exception_cause : out csr_exception_cause
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);
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);
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end entity pp_decode;
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end entity pp_decode;
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architecture behaviour of pp_decode is
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architecture behaviour of pp_decode is
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signal instruction : std_logic_vector(31 downto 0);
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signal instruction : std_logic_vector(31 downto 0);
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signal immediate_value : std_logic_vector(31 downto 0);
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signal immediate_value : std_logic_vector(31 downto 0);
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begin
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begin
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immediate <= immediate_value;
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immediate <= immediate_value;
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get_instruction: process(clk)
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get_instruction: process(clk)
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if reset = '1' then
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if reset = '1' then
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instruction <= RISCV_NOP;
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instruction <= RISCV_NOP;
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pc <= RESET_ADDRESS;
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pc <= RESET_ADDRESS;
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count_instruction <= '0';
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count_instruction <= '0';
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elsif stall = '1' then
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elsif stall = '1' then
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count_instruction <= '0';
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count_instruction <= '0';
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elsif flush = '1' or instruction_ready = '0' then
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elsif flush = '1' or instruction_ready = '0' then
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instruction <= RISCV_NOP;
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instruction <= RISCV_NOP;
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count_instruction <= '0';
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count_instruction <= '0';
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else
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else
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instruction <= instruction_data;
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instruction <= instruction_data;
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count_instruction <= instruction_count;
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count_instruction <= instruction_count;
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pc <= instruction_address;
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pc <= instruction_address;
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end if;
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end if;
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end if;
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end if;
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end process get_instruction;
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end process get_instruction;
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-- -- Extract register addresses from the instruction word:
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-- -- Extract register addresses from the instruction word:
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rs1_addr <= instruction(19 downto 15);
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rs1_addr <= instruction(19 downto 15);
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rs2_addr <= instruction(24 downto 20);
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rs2_addr <= instruction(24 downto 20);
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rd_addr <= instruction(11 downto 7);
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rd_addr <= instruction(11 downto 7);
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-- Extract the shamt value from the instruction word:
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-- Extract the shamt value from the instruction word:
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shamt <= instruction(24 downto 20);
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shamt <= instruction(24 downto 20);
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-- Extract the value specifying which comparison to do in branch instructions:
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-- Extract the value specifying which comparison to do in branch instructions:
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funct3 <= instruction(14 downto 12);
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funct3 <= instruction(14 downto 12);
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-- Extract the immediate value from the instruction word:
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-- Extract the immediate value from the instruction word:
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immediate_decoder: entity work.pp_imm_decoder
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immediate_decoder: entity work.pp_imm_decoder
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port map(
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port map(
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instruction => instruction(31 downto 2),
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instruction => instruction(31 downto 2),
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immediate => immediate_value
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immediate => immediate_value
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);
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);
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decode_csr_addr: process(immediate_value)
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decode_csr_addr: process(immediate_value)
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begin
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begin
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if immediate_value(11 downto 0) = CSR_EPC_SRET then
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if immediate_value(11 downto 0) = CSR_EPC_SRET then
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csr_addr <= CSR_EPC;
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csr_addr <= CSR_EPC;
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else
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else
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csr_addr <= immediate_value(11 downto 0);
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csr_addr <= immediate_value(11 downto 0);
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end if;
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end if;
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end process decode_csr_addr;
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end process decode_csr_addr;
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control_unit: entity work.pp_control_unit
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control_unit: entity work.pp_control_unit
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port map(
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port map(
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opcode => instruction(6 downto 2),
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opcode => instruction(6 downto 2),
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funct3 => instruction(14 downto 12),
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funct3 => instruction(14 downto 12),
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funct7 => instruction(31 downto 25),
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funct7 => instruction(31 downto 25),
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funct12 => instruction(31 downto 20),
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funct12 => instruction(31 downto 20),
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rd_write => rd_write,
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rd_write => rd_write,
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branch => branch,
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branch => branch,
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alu_x_src => alu_x_src,
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alu_x_src => alu_x_src,
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alu_y_src => alu_y_src,
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alu_y_src => alu_y_src,
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alu_op => alu_op,
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alu_op => alu_op,
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mem_op => mem_op,
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mem_op => mem_op,
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mem_size => mem_size,
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mem_size => mem_size,
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decode_exception => decode_exception,
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decode_exception => decode_exception,
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decode_exception_cause => decode_exception_cause,
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decode_exception_cause => decode_exception_cause,
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csr_write => csr_write,
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csr_write => csr_write,
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csr_imm => csr_use_imm
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csr_imm => csr_use_imm
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);
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);
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end architecture behaviour;
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end architecture behaviour;
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