-- The Potato Processor - A simple processor for FPGAs
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-- The Potato Processor - A simple processor for FPGAs
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-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
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-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
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-- Report bugs and issues on <https://github.com/skordal/potato/issues>
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-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.pp_constants.all;
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use work.pp_constants.all;
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--! @brief Instruction fetch unit.
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--! @brief Instruction fetch unit.
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entity pp_fetch is
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entity pp_fetch is
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generic(
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generic(
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RESET_ADDRESS : std_logic_vector(31 downto 0) := x"00000000"
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RESET_ADDRESS : std_logic_vector(31 downto 0) := x"00000000"
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);
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);
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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-- Instruction memory connections:
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-- Instruction memory connections:
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imem_address : out std_logic_vector(31 downto 0);
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imem_address : out std_logic_vector(31 downto 0);
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imem_data_in : in std_logic_vector(31 downto 0);
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imem_data_in : in std_logic_vector(31 downto 0);
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imem_req : out std_logic;
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imem_req : out std_logic;
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imem_ack : in std_logic;
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imem_ack : in std_logic;
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-- Control inputs:
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-- Control inputs:
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stall : in std_logic;
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stall : in std_logic;
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flush : in std_logic;
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flush : in std_logic;
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branch : in std_logic;
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branch : in std_logic;
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exception : in std_logic;
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exception : in std_logic;
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branch_target : in std_logic_vector(31 downto 0);
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branch_target : in std_logic_vector(31 downto 0);
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evec : in std_logic_vector(31 downto 0);
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evec : in std_logic_vector(31 downto 0);
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-- Outputs to the instruction decode unit:
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-- Outputs to the instruction decode unit:
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instruction_data : out std_logic_vector(31 downto 0);
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instruction_data : out std_logic_vector(31 downto 0);
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instruction_address : out std_logic_vector(31 downto 0);
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instruction_address : out std_logic_vector(31 downto 0);
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instruction_ready : out std_logic
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instruction_ready : out std_logic
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);
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);
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end entity pp_fetch;
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end entity pp_fetch;
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architecture behaviour of pp_fetch is
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architecture behaviour of pp_fetch is
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--signal pc, pc_next : std_logic_vector(31 downto 0);
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--signal pc, pc_next : std_logic_vector(31 downto 0);
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--signal acknowledge, ready : std_logic;
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--signal acknowledge, ready : std_logic;
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signal pc : std_logic_vector(31 downto 0);
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signal pc : std_logic_vector(31 downto 0);
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signal pc_next : std_logic_vector(31 downto 0);
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signal pc_next : std_logic_vector(31 downto 0);
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signal cancel_fetch : std_logic;
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signal cancel_fetch : std_logic;
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begin
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begin
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imem_address <= pc_next;
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imem_address <= pc_next;
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instruction_data <= imem_data_in;
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instruction_data <= imem_data_in;
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instruction_ready <= imem_ack and (not stall) and (not cancel_fetch);
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instruction_ready <= imem_ack and (not stall) and (not cancel_fetch);
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instruction_address <= pc;
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instruction_address <= pc;
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--imem_req <= '1' when cancel_fetch = '0' and
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--imem_req <= '1' when cancel_fetch = '0' and
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imem_req <= '1';
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imem_req <= '1';
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set_pc: process(clk)
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set_pc: process(clk)
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if reset = '1' then
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if reset = '1' then
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pc <= RESET_ADDRESS;
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pc <= RESET_ADDRESS;
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cancel_fetch <= '0';
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cancel_fetch <= '0';
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else
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else
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if (exception = '1' or branch = '1') and imem_ack = '0' then
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if (exception = '1' or branch = '1') and imem_ack = '0' then
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cancel_fetch <= '1';
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cancel_fetch <= '1';
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pc <= pc_next;
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pc <= pc_next;
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elsif cancel_fetch = '1' and imem_ack = '1' then
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elsif cancel_fetch = '1' and imem_ack = '1' then
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--pc <= pc_next;
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--pc <= pc_next;
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cancel_fetch <= '0';
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cancel_fetch <= '0';
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else
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else
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pc <= pc_next;
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pc <= pc_next;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process set_pc;
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end process set_pc;
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calc_next_pc: process(reset, stall, branch, exception, imem_ack, branch_target, evec, pc, cancel_fetch)
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calc_next_pc: process(reset, stall, branch, exception, imem_ack, branch_target, evec, pc, cancel_fetch)
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begin
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begin
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if reset = '1' then
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if reset = '1' then
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pc_next <= RESET_ADDRESS;
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pc_next <= RESET_ADDRESS;
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elsif exception = '1' then
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elsif exception = '1' then
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pc_next <= evec;
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pc_next <= evec;
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elsif branch = '1' then
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elsif branch = '1' then
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pc_next <= branch_target;
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pc_next <= branch_target;
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elsif imem_ack = '1' and stall = '0' and cancel_fetch = '0' then
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elsif imem_ack = '1' and stall = '0' and cancel_fetch = '0' then
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pc_next <= std_logic_vector(unsigned(pc) + 4);
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pc_next <= std_logic_vector(unsigned(pc) + 4);
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else
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else
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pc_next <= pc;
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pc_next <= pc;
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end if;
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end if;
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end process calc_next_pc;
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end process calc_next_pc;
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end architecture behaviour;
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end architecture behaviour;
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