-- The Potato Processor - A simple processor for FPGAs
|
-- The Potato Processor - A simple processor for FPGAs
|
-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
|
-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
|
-- Report bugs and issues on <https://github.com/skordal/potato/issues>
|
-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
|
|
--! @brief A generic FIFO module.
|
--! @brief A generic FIFO module.
|
--! Adopted from the FIFO module in <https://github.com/skordal/smallthings>.
|
--! Adopted from the FIFO module in <https://github.com/skordal/smallthings>.
|
entity pp_fifo is
|
entity pp_fifo is
|
generic(
|
generic(
|
DEPTH : natural := 64;
|
DEPTH : natural := 64;
|
WIDTH : natural := 31
|
WIDTH : natural := 31
|
);
|
);
|
port(
|
port(
|
-- Control lines:
|
-- Control lines:
|
clk : in std_logic;
|
clk : in std_logic;
|
reset : in std_logic;
|
reset : in std_logic;
|
|
|
-- Status lines:
|
-- Status lines:
|
full : out std_logic;
|
full : out std_logic;
|
empty : out std_logic;
|
empty : out std_logic;
|
|
|
-- Data in:
|
-- Data in:
|
data_in : in std_logic_vector(WIDTH - 1 downto 0);
|
data_in : in std_logic_vector(WIDTH - 1 downto 0);
|
data_out : out std_logic_vector(WIDTH - 1 downto 0);
|
data_out : out std_logic_vector(WIDTH - 1 downto 0);
|
push, pop : in std_logic
|
push, pop : in std_logic
|
);
|
);
|
end entity pp_fifo;
|
end entity pp_fifo;
|
|
|
architecture behaviour of pp_fifo is
|
architecture behaviour of pp_fifo is
|
|
|
type memory_array is array(0 to DEPTH - 1) of std_logic_vector(WIDTH - 1 downto 0);
|
type memory_array is array(0 to DEPTH - 1) of std_logic_vector(WIDTH - 1 downto 0);
|
shared variable memory : memory_array := (others => (others => '0'));
|
shared variable memory : memory_array := (others => (others => '0'));
|
|
|
subtype index_type is integer range 0 to DEPTH - 1;
|
subtype index_type is integer range 0 to DEPTH - 1;
|
signal top, bottom : index_type;
|
signal top, bottom : index_type;
|
|
|
type fifo_op is (FIFO_POP, FIFO_PUSH);
|
type fifo_op is (FIFO_POP, FIFO_PUSH);
|
signal prev_op : fifo_op := FIFO_POP;
|
signal prev_op : fifo_op := FIFO_POP;
|
|
|
begin
|
begin
|
|
|
empty <= '1' when top = bottom and prev_op = FIFO_POP else '0';
|
empty <= '1' when top = bottom and prev_op = FIFO_POP else '0';
|
full <= '1' when top = bottom and prev_op = FIFO_PUSH else '0';
|
full <= '1' when top = bottom and prev_op = FIFO_PUSH else '0';
|
|
|
read: process(clk)
|
read: process(clk)
|
begin
|
begin
|
if rising_edge(clk) then
|
if rising_edge(clk) then
|
if reset = '1' then
|
if reset = '1' then
|
bottom <= 0;
|
bottom <= 0;
|
else
|
else
|
if pop = '1' then
|
if pop = '1' then
|
data_out <= memory(bottom);
|
data_out <= memory(bottom);
|
bottom <= (bottom + 1) mod DEPTH;
|
bottom <= (bottom + 1) mod DEPTH;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process read;
|
end process read;
|
|
|
write: process(clk)
|
write: process(clk)
|
begin
|
begin
|
if rising_edge(clk) then
|
if rising_edge(clk) then
|
if reset = '1' then
|
if reset = '1' then
|
top <= 0;
|
top <= 0;
|
else
|
else
|
if push = '1' then
|
if push = '1' then
|
memory(top) := data_in;
|
memory(top) := data_in;
|
top <= (top + 1) mod DEPTH;
|
top <= (top + 1) mod DEPTH;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process write;
|
end process write;
|
|
|
set_prev_op: process(clk)
|
set_prev_op: process(clk)
|
begin
|
begin
|
if rising_edge(clk) then
|
if rising_edge(clk) then
|
if reset = '1' then
|
if reset = '1' then
|
prev_op <= FIFO_POP;
|
prev_op <= FIFO_POP;
|
else
|
else
|
if push = '1' and pop = '1' then
|
if push = '1' and pop = '1' then
|
prev_op <= FIFO_POP;
|
prev_op <= FIFO_POP;
|
elsif push = '1' then
|
elsif push = '1' then
|
prev_op <= FIFO_PUSH;
|
prev_op <= FIFO_PUSH;
|
elsif pop = '1' then
|
elsif pop = '1' then
|
prev_op <= FIFO_POP;
|
prev_op <= FIFO_POP;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process set_prev_op;
|
end process set_prev_op;
|
|
|
end architecture behaviour;
|
end architecture behaviour;
|
|
|
