-- The Potato Processor - A simple processor for FPGAs
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-- The Potato Processor - A simple processor for FPGAs
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-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
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-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
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-- Report bugs and issues on <https://github.com/skordal/potato/issues>
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-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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--! @brief The Potato Processor.
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--! @brief The Potato Processor.
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--! This file provides a Wishbone-compatible interface to the Potato processor.
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--! This file provides a Wishbone-compatible interface to the Potato processor.
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entity pp_potato is
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entity pp_potato is
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generic(
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generic(
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PROCESSOR_ID : std_logic_vector(31 downto 0) := x"00000000"; --! Processor ID.
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PROCESSOR_ID : std_logic_vector(31 downto 0) := x"00000000"; --! Processor ID.
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RESET_ADDRESS : std_logic_vector(31 downto 0) := x"00000000" --! Address of the first instruction to execute.
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RESET_ADDRESS : std_logic_vector(31 downto 0) := x"00000000" --! Address of the first instruction to execute.
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);
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);
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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-- Interrupts:
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-- Interrupts:
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irq : in std_logic_vector(7 downto 0);
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irq : in std_logic_vector(7 downto 0);
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-- Host/Target interface:
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-- Host/Target interface:
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fromhost_data : in std_logic_vector(31 downto 0);
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fromhost_data : in std_logic_vector(31 downto 0);
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fromhost_updated : in std_logic;
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fromhost_updated : in std_logic;
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tohost_data : out std_logic_vector(31 downto 0);
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tohost_data : out std_logic_vector(31 downto 0);
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tohost_updated : out std_logic;
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tohost_updated : out std_logic;
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-- Wishbone interface:
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-- Wishbone interface:
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wb_adr_out : out std_logic_vector(31 downto 0);
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wb_adr_out : out std_logic_vector(31 downto 0);
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wb_sel_out : out std_logic_vector( 3 downto 0);
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wb_sel_out : out std_logic_vector( 3 downto 0);
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wb_cyc_out : out std_logic;
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wb_cyc_out : out std_logic;
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wb_stb_out : out std_logic;
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wb_stb_out : out std_logic;
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wb_we_out : out std_logic;
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wb_we_out : out std_logic;
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wb_dat_out : out std_logic_vector(31 downto 0);
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wb_dat_out : out std_logic_vector(31 downto 0);
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wb_dat_in : in std_logic_vector(31 downto 0);
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wb_dat_in : in std_logic_vector(31 downto 0);
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wb_ack_in : in std_logic
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wb_ack_in : in std_logic
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);
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);
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end entity pp_potato;
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end entity pp_potato;
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architecture behaviour of pp_potato is
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architecture behaviour of pp_potato is
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-- Instruction memory signals:
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-- Instruction memory signals:
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signal imem_address : std_logic_vector(31 downto 0);
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signal imem_address : std_logic_vector(31 downto 0);
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signal imem_data : std_logic_vector(31 downto 0);
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signal imem_data : std_logic_vector(31 downto 0);
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signal imem_req, imem_ack : std_logic;
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signal imem_req, imem_ack : std_logic;
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-- Data memory signals:
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-- Data memory signals:
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signal dmem_address : std_logic_vector(31 downto 0);
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signal dmem_address : std_logic_vector(31 downto 0);
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signal dmem_data_in : std_logic_vector(31 downto 0);
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signal dmem_data_in : std_logic_vector(31 downto 0);
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signal dmem_data_out : std_logic_vector(31 downto 0);
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signal dmem_data_out : std_logic_vector(31 downto 0);
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signal dmem_data_size : std_logic_vector( 1 downto 0);
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signal dmem_data_size : std_logic_vector( 1 downto 0);
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signal dmem_read_req : std_logic;
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signal dmem_read_req : std_logic;
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signal dmem_read_ack : std_logic;
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signal dmem_read_ack : std_logic;
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signal dmem_write_req : std_logic;
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signal dmem_write_req : std_logic;
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signal dmem_write_ack : std_logic;
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signal dmem_write_ack : std_logic;
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begin
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begin
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processor: entity work.pp_core
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processor: entity work.pp_core
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generic map(
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generic map(
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PROCESSOR_ID => PROCESSOR_ID,
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PROCESSOR_ID => PROCESSOR_ID,
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RESET_ADDRESS => RESET_ADDRESS
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RESET_ADDRESS => RESET_ADDRESS
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) port map(
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) port map(
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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timer_clk => clk,
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timer_clk => clk,
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imem_address => imem_address,
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imem_address => imem_address,
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imem_data_in => imem_data,
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imem_data_in => imem_data,
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imem_req => imem_req,
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imem_req => imem_req,
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imem_ack => imem_ack,
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imem_ack => imem_ack,
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dmem_address => dmem_address,
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dmem_address => dmem_address,
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dmem_data_in => dmem_data_in,
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dmem_data_in => dmem_data_in,
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dmem_data_out => dmem_data_out,
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dmem_data_out => dmem_data_out,
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dmem_data_size => dmem_data_size,
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dmem_data_size => dmem_data_size,
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dmem_read_req => dmem_read_req,
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dmem_read_req => dmem_read_req,
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dmem_read_ack => dmem_read_ack,
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dmem_read_ack => dmem_read_ack,
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dmem_write_req => dmem_write_req,
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dmem_write_req => dmem_write_req,
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dmem_write_ack => dmem_write_ack,
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dmem_write_ack => dmem_write_ack,
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fromhost_data => fromhost_data,
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fromhost_data => fromhost_data,
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fromhost_write_en => fromhost_updated,
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fromhost_write_en => fromhost_updated,
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tohost_data => tohost_data,
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tohost_data => tohost_data,
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tohost_write_en => tohost_updated,
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tohost_write_en => tohost_updated,
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irq => irq
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irq => irq
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);
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);
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wb_if: entity work.pp_wb_adapter
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wb_if: entity work.pp_wb_adapter
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port map(
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port map(
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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imem_address => imem_address,
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imem_address => imem_address,
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imem_data_out => imem_data,
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imem_data_out => imem_data,
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imem_read_req => imem_req,
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imem_read_req => imem_req,
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imem_read_ack => imem_ack,
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imem_read_ack => imem_ack,
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dmem_address => dmem_address,
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dmem_address => dmem_address,
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dmem_data_in => dmem_data_out,
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dmem_data_in => dmem_data_out,
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dmem_data_out => dmem_data_in,
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dmem_data_out => dmem_data_in,
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dmem_data_size => dmem_data_size,
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dmem_data_size => dmem_data_size,
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dmem_read_req => dmem_read_req,
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dmem_read_req => dmem_read_req,
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dmem_write_req => dmem_write_req,
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dmem_write_req => dmem_write_req,
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dmem_read_ack => dmem_read_ack,
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dmem_read_ack => dmem_read_ack,
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dmem_write_ack => dmem_write_ack,
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dmem_write_ack => dmem_write_ack,
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wb_adr_out => wb_adr_out,
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wb_adr_out => wb_adr_out,
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wb_sel_out => wb_sel_out,
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wb_sel_out => wb_sel_out,
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wb_cyc_out => wb_cyc_out,
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wb_cyc_out => wb_cyc_out,
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wb_stb_out => wb_stb_out,
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wb_stb_out => wb_stb_out,
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wb_we_out => wb_we_out,
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wb_we_out => wb_we_out,
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wb_dat_out => wb_dat_out,
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wb_dat_out => wb_dat_out,
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wb_dat_in => wb_dat_in,
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wb_dat_in => wb_dat_in,
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wb_ack_in => wb_ack_in
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wb_ack_in => wb_ack_in
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);
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);
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end architecture behaviour;
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end architecture behaviour;
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