-- The Potato Processor - A simple processor for FPGAs
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-- The Potato Processor - A simple processor for FPGAs
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-- (c) Kristian Klomsten Skordal 2014 <kristian.skordal@wafflemail.net>
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-- (c) Kristian Klomsten Skordal 2014 <kristian.skordal@wafflemail.net>
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-- Report bugs and issues on <https://github.com/skordal/potato/issues>
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-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.pp_types.all;
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use work.pp_types.all;
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use work.pp_utilities.all;
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use work.pp_utilities.all;
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--! @brief 32-bit RISC-V register file.
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--! @brief 32-bit RISC-V register file.
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entity pp_register_file is
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entity pp_register_file is
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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-- Read port 1:
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-- Read port 1:
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rs1_addr : in register_address;
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rs1_addr : in register_address;
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rs1_data : out std_logic_vector(31 downto 0);
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rs1_data : out std_logic_vector(31 downto 0);
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-- Read port 2:
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-- Read port 2:
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rs2_addr : in register_address;
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rs2_addr : in register_address;
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rs2_data : out std_logic_vector(31 downto 0);
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rs2_data : out std_logic_vector(31 downto 0);
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-- Write port:
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-- Write port:
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rd_addr : in register_address;
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rd_addr : in register_address;
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rd_data : in std_logic_vector(31 downto 0);
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rd_data : in std_logic_vector(31 downto 0);
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rd_write : in std_logic
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rd_write : in std_logic
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);
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);
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end entity pp_register_file;
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end entity pp_register_file;
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architecture behaviour of pp_register_file is
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architecture behaviour of pp_register_file is
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--! Register array type.
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--! Register array type.
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type regfile_array is array(0 to 31) of std_logic_vector(31 downto 0);
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type regfile_array is array(0 to 31) of std_logic_vector(31 downto 0);
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--! Register array.
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--! Register array.
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--shared variable registers : regfile_array := (others => (others => '0')); -- Shared variable used to simulate write-first RAM
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--shared variable registers : regfile_array := (others => (others => '0')); -- Shared variable used to simulate write-first RAM
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begin
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begin
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regfile: process(clk)
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regfile: process(clk)
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variable registers : regfile_array := (others => (others => '0'));
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variable registers : regfile_array := (others => (others => '0'));
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if rd_write = '1' and rd_addr /= b"00000" then
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if rd_write = '1' and rd_addr /= b"00000" then
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registers(to_integer(unsigned(rd_addr))) := rd_data;
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registers(to_integer(unsigned(rd_addr))) := rd_data;
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end if;
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end if;
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rs1_data <= registers(to_integer(unsigned(rs1_addr)));
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rs1_data <= registers(to_integer(unsigned(rs1_addr)));
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rs2_data <= registers(to_integer(unsigned(rs2_addr)));
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rs2_data <= registers(to_integer(unsigned(rs2_addr)));
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end if;
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end if;
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end process regfile;
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end process regfile;
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end architecture behaviour;
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end architecture behaviour;
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