-- The Potato Processor - A simple processor for FPGAs
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-- The Potato Processor - A simple processor for FPGAs
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-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
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-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
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-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
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-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.pp_types.all;
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use work.pp_types.all;
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use work.pp_utilities.all;
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use work.pp_utilities.all;
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--! @brief Wishbone adapter, for connecting the processor to a Wishbone bus when not using caches.
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--! @brief Wishbone adapter, for connecting the processor to a Wishbone bus when not using caches.
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entity pp_wb_adapter is
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entity pp_wb_adapter is
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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-- Processor data memory signals:
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-- Processor data memory signals:
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signal dmem_address : in std_logic_vector(31 downto 0);
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signal dmem_address : in std_logic_vector(31 downto 0);
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signal dmem_data_in : in std_logic_vector(31 downto 0); -- Data in to the bus
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signal dmem_data_in : in std_logic_vector(31 downto 0); -- Data in to the bus
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signal dmem_data_out : out std_logic_vector(31 downto 0); -- Data out to the bus
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signal dmem_data_out : out std_logic_vector(31 downto 0); -- Data out to the bus
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signal dmem_data_size : in std_logic_vector( 1 downto 0);
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signal dmem_data_size : in std_logic_vector( 1 downto 0);
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signal dmem_read_req : in std_logic;
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signal dmem_read_req : in std_logic;
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signal dmem_read_ack : out std_logic;
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signal dmem_read_ack : out std_logic;
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signal dmem_write_req : in std_logic;
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signal dmem_write_req : in std_logic;
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signal dmem_write_ack : out std_logic;
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signal dmem_write_ack : out std_logic;
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-- Wishbone interface:
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-- Wishbone interface:
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wb_inputs : in wishbone_master_inputs;
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wb_inputs : in wishbone_master_inputs;
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wb_outputs : out wishbone_master_outputs
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wb_outputs : out wishbone_master_outputs
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);
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);
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end entity pp_wb_adapter;
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end entity pp_wb_adapter;
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architecture behaviour of pp_wb_adapter is
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architecture behaviour of pp_wb_adapter is
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type states is (IDLE, READ_WAIT_ACK, WRITE_WAIT_ACK);
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type states is (IDLE, READ_WAIT_ACK, WRITE_WAIT_ACK);
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signal state : states;
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signal state : states;
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signal dmem_r_ack : std_logic;
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signal dmem_r_ack : std_logic;
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function get_data_shift(size : in std_logic_vector(1 downto 0); address : in std_logic_vector)
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function get_data_shift(size : in std_logic_vector(1 downto 0); address : in std_logic_vector)
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return natural is
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return natural is
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begin
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begin
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case size is
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case size is
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when b"01" =>
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when b"01" =>
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case address(1 downto 0) is
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case address(1 downto 0) is
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when b"00" =>
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when b"00" =>
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return 0;
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return 0;
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when b"01" =>
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when b"01" =>
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return 8;
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return 8;
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when b"10" =>
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when b"10" =>
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return 16;
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return 16;
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when b"11" =>
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when b"11" =>
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return 24;
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return 24;
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when others =>
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when others =>
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return 0;
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return 0;
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end case;
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end case;
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when b"10" =>
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when b"10" =>
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if address(1) = '0' then
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if address(1) = '0' then
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return 0;
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return 0;
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else
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else
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return 16;
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return 16;
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end if;
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end if;
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when others =>
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when others =>
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return 0;
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return 0;
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end case;
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end case;
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end function get_data_shift;
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end function get_data_shift;
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begin
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begin
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dmem_write_ack <= '1' when state = WRITE_WAIT_ACK and wb_inputs.ack = '1' else '0';
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dmem_write_ack <= '1' when state = WRITE_WAIT_ACK and wb_inputs.ack = '1' else '0';
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dmem_read_ack <= dmem_r_ack;
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dmem_read_ack <= dmem_r_ack;
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wishbone: process(clk)
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wishbone: process(clk)
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if reset = '1' then
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if reset = '1' then
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state <= IDLE;
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state <= IDLE;
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wb_outputs.cyc <= '0';
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wb_outputs.cyc <= '0';
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wb_outputs.stb <= '0';
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wb_outputs.stb <= '0';
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dmem_r_ack <= '0';
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dmem_r_ack <= '0';
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else
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else
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case state is
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case state is
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when IDLE =>
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when IDLE =>
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dmem_r_ack <= '0';
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dmem_r_ack <= '0';
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-- Prioritize requests from the data memory:
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-- Prioritize requests from the data memory:
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if dmem_write_req = '1' then
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if dmem_write_req = '1' then
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wb_outputs.adr <= dmem_address;
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wb_outputs.adr <= dmem_address;
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wb_outputs.dat <= std_logic_vector(shift_left(unsigned(dmem_data_in),
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wb_outputs.dat <= std_logic_vector(shift_left(unsigned(dmem_data_in),
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get_data_shift(dmem_data_size, dmem_address)));
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get_data_shift(dmem_data_size, dmem_address)));
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wb_outputs.sel <= wb_get_data_sel(dmem_data_size, dmem_address);
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wb_outputs.sel <= wb_get_data_sel(dmem_data_size, dmem_address);
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wb_outputs.cyc <= '1';
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wb_outputs.cyc <= '1';
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wb_outputs.stb <= '1';
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wb_outputs.stb <= '1';
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wb_outputs.we <= '1';
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wb_outputs.we <= '1';
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state <= WRITE_WAIT_ACK;
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state <= WRITE_WAIT_ACK;
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elsif dmem_read_req = '1' then
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elsif dmem_read_req = '1' then
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wb_outputs.adr <= dmem_address;
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wb_outputs.adr <= dmem_address;
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wb_outputs.sel <= wb_get_data_sel(dmem_data_size, dmem_address);
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wb_outputs.sel <= wb_get_data_sel(dmem_data_size, dmem_address);
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wb_outputs.cyc <= '1';
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wb_outputs.cyc <= '1';
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wb_outputs.stb <= '1';
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wb_outputs.stb <= '1';
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wb_outputs.we <= '0';
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wb_outputs.we <= '0';
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state <= READ_WAIT_ACK;
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state <= READ_WAIT_ACK;
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end if;
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end if;
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when READ_WAIT_ACK =>
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when READ_WAIT_ACK =>
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if wb_inputs.ack = '1' then
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if wb_inputs.ack = '1' then
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dmem_data_out <= std_logic_vector(shift_right(unsigned(wb_inputs.dat),
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dmem_data_out <= std_logic_vector(shift_right(unsigned(wb_inputs.dat),
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get_data_shift(dmem_data_size, dmem_address)));
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get_data_shift(dmem_data_size, dmem_address)));
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wb_outputs.cyc <= '0';
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wb_outputs.cyc <= '0';
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wb_outputs.stb <= '0';
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wb_outputs.stb <= '0';
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dmem_r_ack <= '1';
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dmem_r_ack <= '1';
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state <= IDLE;
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state <= IDLE;
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end if;
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end if;
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when WRITE_WAIT_ACK =>
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when WRITE_WAIT_ACK =>
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if wb_inputs.ack = '1' then
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if wb_inputs.ack = '1' then
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wb_outputs.cyc <= '0';
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wb_outputs.cyc <= '0';
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wb_outputs.stb <= '0';
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wb_outputs.stb <= '0';
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wb_outputs.we <= '0';
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wb_outputs.we <= '0';
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state <= IDLE;
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state <= IDLE;
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end if;
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end if;
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end process wishbone;
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end process wishbone;
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end architecture behaviour;
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end architecture behaviour;
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