-- The Potato Processor - A simple processor for FPGAs
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-- The Potato Processor - A simple processor for FPGAs
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-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
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-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
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-- Report bugs and issues on <https://github.com/skordal/potato/issues>
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-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.pp_types.all;
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use work.pp_types.all;
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use work.pp_csr.all;
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use work.pp_csr.all;
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entity pp_writeback is
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entity pp_writeback is
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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-- Count instruction:
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-- Count instruction:
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count_instr_in : in std_logic;
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count_instr_in : in std_logic;
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count_instr_out : out std_logic;
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count_instr_out : out std_logic;
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-- Exception signals:
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-- Exception signals:
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exception_ctx_in : in csr_exception_context;
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exception_ctx_in : in csr_exception_context;
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exception_in : in std_logic;
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exception_in : in std_logic;
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exception_ctx_out : out csr_exception_context;
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exception_ctx_out : out csr_exception_context;
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exception_out : out std_logic;
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exception_out : out std_logic;
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-- CSR signals:
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-- CSR signals:
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csr_write_in : in csr_write_mode;
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csr_write_in : in csr_write_mode;
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csr_write_out : out csr_write_mode;
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csr_write_out : out csr_write_mode;
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csr_data_in : in std_logic_vector(31 downto 0);
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csr_data_in : in std_logic_vector(31 downto 0);
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csr_data_out : out std_logic_vector(31 downto 0);
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csr_data_out : out std_logic_vector(31 downto 0);
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csr_addr_in : in csr_address;
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csr_addr_in : in csr_address;
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csr_addr_out : out csr_address;
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csr_addr_out : out csr_address;
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-- Destination register interface:
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-- Destination register interface:
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rd_addr_in : in register_address;
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rd_addr_in : in register_address;
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rd_addr_out : out register_address;
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rd_addr_out : out register_address;
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rd_write_in : in std_logic;
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rd_write_in : in std_logic;
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rd_write_out : out std_logic;
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rd_write_out : out std_logic;
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rd_data_in : in std_logic_vector(31 downto 0);
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rd_data_in : in std_logic_vector(31 downto 0);
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rd_data_out : out std_logic_vector(31 downto 0)
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rd_data_out : out std_logic_vector(31 downto 0)
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);
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);
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end entity pp_writeback;
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end entity pp_writeback;
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architecture behaviour of pp_writeback is
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architecture behaviour of pp_writeback is
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begin
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begin
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pipeline_register: process(clk)
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pipeline_register: process(clk)
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if reset = '1' then
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if reset = '1' then
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rd_write_out <= '0';
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rd_write_out <= '0';
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exception_out <= '0';
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exception_out <= '0';
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count_instr_out <= '0';
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count_instr_out <= '0';
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else
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else
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count_instr_out <= count_instr_in;
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count_instr_out <= count_instr_in;
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rd_data_out <= rd_data_in;
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rd_data_out <= rd_data_in;
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rd_write_out <= rd_write_in;
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rd_write_out <= rd_write_in;
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rd_addr_out <= rd_addr_in;
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rd_addr_out <= rd_addr_in;
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exception_out <= exception_in;
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exception_out <= exception_in;
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exception_ctx_out <= exception_ctx_in;
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exception_ctx_out <= exception_ctx_in;
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csr_write_out <= csr_write_in;
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csr_write_out <= csr_write_in;
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csr_data_out <= csr_data_in;
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csr_data_out <= csr_data_in;
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csr_addr_out <= csr_addr_in;
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csr_addr_out <= csr_addr_in;
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end if;
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end if;
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end if;
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end if;
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end process pipeline_register;
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end process pipeline_register;
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end architecture behaviour;
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end architecture behaviour;
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