-- The Potato Processor - A simple processor for FPGAs
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-- The Potato Processor - A simple processor for FPGAs
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-- (c) Kristian Klomsten Skordal 2014 <kristian.skordal@wafflemail.net>
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-- (c) Kristian Klomsten Skordal 2014 <kristian.skordal@wafflemail.net>
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-- Report bugs and issues on <https://github.com/skordal/potato/issues>
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-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_textio.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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use std.textio.all;
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use work.pp_constants.all;
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use work.pp_constants.all;
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entity tb_processor is
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entity tb_processor is
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generic(
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generic(
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IMEM_SIZE : natural := 2048; --! Size of the instruction memory in bytes.
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IMEM_SIZE : natural := 2048; --! Size of the instruction memory in bytes.
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DMEM_SIZE : natural := 2048; --! Size of the data memory in bytes.
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DMEM_SIZE : natural := 2048; --! Size of the data memory in bytes.
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IMEM_FILENAME : string := "imem_testfile.hex"; --! File containing the contents of instruction memory.
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IMEM_FILENAME : string := "imem_testfile.hex"; --! File containing the contents of instruction memory.
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DMEM_FILENAME : string := "dmem_testfile.hex" --! File containing the contents of data memory.
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DMEM_FILENAME : string := "dmem_testfile.hex" --! File containing the contents of data memory.
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);
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);
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end entity tb_processor;
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end entity tb_processor;
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architecture testbench of tb_processor is
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architecture testbench of tb_processor is
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-- Processor component prototype:
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-- Processor component prototype:
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component pp_core is
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component pp_core is
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port(
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port(
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-- Common inputs:
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-- Common inputs:
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clk : in std_logic; --! Processor clock
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clk : in std_logic; --! Processor clock
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reset : in std_logic; --! Reset signal
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reset : in std_logic; --! Reset signal
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timer_clk : in std_logic; --! Timer clock input
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timer_clk : in std_logic; --! Timer clock input
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-- Instruction memory interface:
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-- Instruction memory interface:
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imem_address : out std_logic_vector(31 downto 0); --! Address of the next instruction
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imem_address : out std_logic_vector(31 downto 0); --! Address of the next instruction
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imem_data_in : in std_logic_vector(31 downto 0); --! Instruction input
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imem_data_in : in std_logic_vector(31 downto 0); --! Instruction input
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imem_req : out std_logic;
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imem_req : out std_logic;
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imem_ack : in std_logic;
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imem_ack : in std_logic;
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-- Data memory interface:
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-- Data memory interface:
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dmem_address : out std_logic_vector(31 downto 0); --! Data address
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dmem_address : out std_logic_vector(31 downto 0); --! Data address
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dmem_data_in : in std_logic_vector(31 downto 0); --! Input from the data memory
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dmem_data_in : in std_logic_vector(31 downto 0); --! Input from the data memory
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dmem_data_out : out std_logic_vector(31 downto 0); --! Ouptut to the data memory
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dmem_data_out : out std_logic_vector(31 downto 0); --! Ouptut to the data memory
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dmem_data_size : out std_logic_vector( 1 downto 0); --! Size of the data, 1 = 8 bits, 2 = 16 bits, 0 = 32 bits.
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dmem_data_size : out std_logic_vector( 1 downto 0); --! Size of the data, 1 = 8 bits, 2 = 16 bits, 0 = 32 bits.
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dmem_read_req : out std_logic; --! Data memory read request
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dmem_read_req : out std_logic; --! Data memory read request
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dmem_read_ack : in std_logic; --! Data memory read acknowledge
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dmem_read_ack : in std_logic; --! Data memory read acknowledge
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dmem_write_req : out std_logic; --! Data memory write request
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dmem_write_req : out std_logic; --! Data memory write request
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dmem_write_ack : in std_logic; --! Data memory write acknowledge
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dmem_write_ack : in std_logic; --! Data memory write acknowledge
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-- Tohost/fromhost interface:
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-- Tohost/fromhost interface:
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fromhost_data : in std_logic_vector(31 downto 0); --! Data from the host/simulator.
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fromhost_data : in std_logic_vector(31 downto 0); --! Data from the host/simulator.
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fromhost_write_en : in std_logic; --! Write enable signal from the host/simulator.
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fromhost_write_en : in std_logic; --! Write enable signal from the host/simulator.
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tohost_data : out std_logic_vector(31 downto 0); --! Data to the host/simulator.
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tohost_data : out std_logic_vector(31 downto 0); --! Data to the host/simulator.
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tohost_write_en : out std_logic; --! Write enable signal to the host/simulator.
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tohost_write_en : out std_logic; --! Write enable signal to the host/simulator.
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-- External interrupt input:
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-- External interrupt input:
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irq : in std_logic_vector(7 downto 0) --! IRQ input
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irq : in std_logic_vector(7 downto 0) --! IRQ input
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);
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);
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end component pp_core;
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end component pp_core;
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-- Clock signal:
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-- Clock signal:
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signal clk : std_logic := '0';
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signal clk : std_logic := '0';
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constant clk_period : time := 10 ns;
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constant clk_period : time := 10 ns;
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-- Common inputs:
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-- Common inputs:
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signal reset : std_logic := '1';
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signal reset : std_logic := '1';
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-- Instruction memory interface:
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-- Instruction memory interface:
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signal imem_address : std_logic_vector(31 downto 0);
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signal imem_address : std_logic_vector(31 downto 0);
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signal imem_data_in : std_logic_vector(31 downto 0) := (others => '0');
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signal imem_data_in : std_logic_vector(31 downto 0) := (others => '0');
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signal imem_req : std_logic;
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signal imem_req : std_logic;
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signal imem_ack : std_logic := '0';
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signal imem_ack : std_logic := '0';
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-- Data memory interface:
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-- Data memory interface:
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signal dmem_address : std_logic_vector(31 downto 0);
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signal dmem_address : std_logic_vector(31 downto 0);
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signal dmem_data_in : std_logic_vector(31 downto 0) := (others => '0');
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signal dmem_data_in : std_logic_vector(31 downto 0) := (others => '0');
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signal dmem_data_out : std_logic_vector(31 downto 0);
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signal dmem_data_out : std_logic_vector(31 downto 0);
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signal dmem_data_size : std_logic_vector( 1 downto 0);
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signal dmem_data_size : std_logic_vector( 1 downto 0);
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signal dmem_read_req, dmem_write_req : std_logic;
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signal dmem_read_req, dmem_write_req : std_logic;
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signal dmem_read_ack, dmem_write_ack : std_logic := '1';
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signal dmem_read_ack, dmem_write_ack : std_logic := '1';
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-- Tohost/Fromhost:
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-- Tohost/Fromhost:
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signal tohost_data : std_logic_vector(31 downto 0);
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signal tohost_data : std_logic_vector(31 downto 0);
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signal fromhost_data : std_logic_vectoR(31 downto 0) := (others => '0');
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signal fromhost_data : std_logic_vectoR(31 downto 0) := (others => '0');
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signal tohost_write_en : std_logic;
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signal tohost_write_en : std_logic;
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signal fromhost_write_en : std_logic := '0';
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signal fromhost_write_en : std_logic := '0';
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-- External interrupt input:
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-- External interrupt input:
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signal irq : std_logic_vector(7 downto 0) := (others => '0');
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signal irq : std_logic_vector(7 downto 0) := (others => '0');
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-- Simulation initialized:
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-- Simulation initialized:
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signal imem_initialized, dmem_initialized, initialized : boolean := false;
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signal imem_initialized, dmem_initialized, initialized : boolean := false;
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-- Memory array type:
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-- Memory array type:
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type memory_array is array(natural range <>) of std_logic_vector(7 downto 0);
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type memory_array is array(natural range <>) of std_logic_vector(7 downto 0);
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constant IMEM_BASE : natural := 0;
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constant IMEM_BASE : natural := 0;
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constant IMEM_END : natural := IMEM_SIZE - 1;
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constant IMEM_END : natural := IMEM_SIZE - 1;
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constant DMEM_BASE : natural := IMEM_SIZE;
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constant DMEM_BASE : natural := IMEM_SIZE;
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constant DMEM_END : natural := IMEM_SIZE + DMEM_SIZE - 1;
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constant DMEM_END : natural := IMEM_SIZE + DMEM_SIZE - 1;
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-- Memories:
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-- Memories:
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signal imem_memory : memory_array(IMEM_BASE to IMEM_END);
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signal imem_memory : memory_array(IMEM_BASE to IMEM_END);
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signal dmem_memory : memory_array(DMEM_BASE to DMEM_END);
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signal dmem_memory : memory_array(DMEM_BASE to DMEM_END);
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signal simulation_finished : boolean := false;
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signal simulation_finished : boolean := false;
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begin
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begin
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uut: pp_core
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uut: pp_core
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port map(
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port map(
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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timer_clk => clk,
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timer_clk => clk,
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imem_address => imem_address,
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imem_address => imem_address,
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imem_data_in => imem_data_in,
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imem_data_in => imem_data_in,
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imem_req => imem_req,
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imem_req => imem_req,
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imem_ack => imem_ack,
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imem_ack => imem_ack,
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dmem_address => dmem_address,
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dmem_address => dmem_address,
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dmem_data_in => dmem_data_in,
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dmem_data_in => dmem_data_in,
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dmem_data_out => dmem_data_out,
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dmem_data_out => dmem_data_out,
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dmem_data_size => dmem_data_size,
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dmem_data_size => dmem_data_size,
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dmem_read_req => dmem_read_req,
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dmem_read_req => dmem_read_req,
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dmem_read_ack => dmem_read_ack,
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dmem_read_ack => dmem_read_ack,
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dmem_write_req => dmem_write_req,
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dmem_write_req => dmem_write_req,
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dmem_write_ack => dmem_write_ack,
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dmem_write_ack => dmem_write_ack,
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tohost_data => tohost_data,
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tohost_data => tohost_data,
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tohost_write_en => tohost_write_en,
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tohost_write_en => tohost_write_en,
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fromhost_data => fromhost_data,
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fromhost_data => fromhost_data,
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fromhost_write_en => fromhost_write_en,
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fromhost_write_en => fromhost_write_en,
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irq => irq
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irq => irq
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);
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);
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clock: process
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clock: process
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begin
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begin
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clk <= '0';
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clk <= '0';
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wait for clk_period / 2;
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wait for clk_period / 2;
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clk <= '1';
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clk <= '1';
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wait for clk_period / 2;
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wait for clk_period / 2;
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if simulation_finished then
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if simulation_finished then
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wait;
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wait;
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end if;
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end if;
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end process clock;
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end process clock;
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--! Initializes the instruction memory from file.
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--! Initializes the instruction memory from file.
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imem_init: process
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imem_init: process
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file imem_file : text open READ_MODE is IMEM_FILENAME;
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file imem_file : text open READ_MODE is IMEM_FILENAME;
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variable input_line : line;
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variable input_line : line;
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variable input_index : natural;
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variable input_index : natural;
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variable input_value : std_logic_vector(31 downto 0);
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variable input_value : std_logic_vector(31 downto 0);
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begin
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begin
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for i in IMEM_BASE / 4 to IMEM_END / 4 loop
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for i in IMEM_BASE / 4 to IMEM_END / 4 loop
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if not endfile(imem_file) then
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if not endfile(imem_file) then
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readline(imem_file, input_line);
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readline(imem_file, input_line);
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hread(input_line, input_value);
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hread(input_line, input_value);
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imem_memory(i * 4 + 0) <= input_value( 7 downto 0);
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imem_memory(i * 4 + 0) <= input_value( 7 downto 0);
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imem_memory(i * 4 + 1) <= input_value(15 downto 8);
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imem_memory(i * 4 + 1) <= input_value(15 downto 8);
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imem_memory(i * 4 + 2) <= input_value(23 downto 16);
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imem_memory(i * 4 + 2) <= input_value(23 downto 16);
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imem_memory(i * 4 + 3) <= input_value(31 downto 24);
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imem_memory(i * 4 + 3) <= input_value(31 downto 24);
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else
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else
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imem_memory(i * 4 + 0) <= RISCV_NOP( 7 downto 0);
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imem_memory(i * 4 + 0) <= RISCV_NOP( 7 downto 0);
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imem_memory(i * 4 + 1) <= RISCV_NOP(15 downto 8);
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imem_memory(i * 4 + 1) <= RISCV_NOP(15 downto 8);
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imem_memory(i * 4 + 2) <= RISCV_NOP(23 downto 16);
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imem_memory(i * 4 + 2) <= RISCV_NOP(23 downto 16);
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imem_memory(i * 4 + 3) <= RISCV_NOP(31 downto 24);
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imem_memory(i * 4 + 3) <= RISCV_NOP(31 downto 24);
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end if;
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end if;
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end loop;
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end loop;
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imem_initialized <= true;
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imem_initialized <= true;
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wait;
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wait;
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end process imem_init;
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end process imem_init;
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--! Initializes and handles writes to the data memory.
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--! Initializes and handles writes to the data memory.
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dmem_init_and_write: process(clk)
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dmem_init_and_write: process(clk)
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file dmem_file : text open READ_MODE is DMEM_FILENAME;
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file dmem_file : text open READ_MODE is DMEM_FILENAME;
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variable input_line : line;
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variable input_line : line;
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variable input_index : natural;
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variable input_index : natural;
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variable input_value : std_logic_vector(31 downto 0);
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variable input_value : std_logic_vector(31 downto 0);
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begin
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begin
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if not dmem_initialized then
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if not dmem_initialized then
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for i in DMEM_BASE / 4 to DMEM_END / 4 loop
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for i in DMEM_BASE / 4 to DMEM_END / 4 loop
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if not endfile(dmem_file) then
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if not endfile(dmem_file) then
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readline(dmem_file, input_line);
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readline(dmem_file, input_line);
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hread(input_line, input_value);
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hread(input_line, input_value);
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-- Read from a big-endian file:
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-- Read from a big-endian file:
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dmem_memory(i * 4 + 3) <= input_value( 7 downto 0);
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dmem_memory(i * 4 + 3) <= input_value( 7 downto 0);
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dmem_memory(i * 4 + 2) <= input_value(15 downto 8);
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dmem_memory(i * 4 + 2) <= input_value(15 downto 8);
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dmem_memory(i * 4 + 1) <= input_value(23 downto 16);
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dmem_memory(i * 4 + 1) <= input_value(23 downto 16);
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dmem_memory(i * 4 + 0) <= input_value(31 downto 24);
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dmem_memory(i * 4 + 0) <= input_value(31 downto 24);
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else
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else
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dmem_memory(i * 4 + 0) <= (others => '0');
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dmem_memory(i * 4 + 0) <= (others => '0');
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dmem_memory(i * 4 + 1) <= (others => '0');
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dmem_memory(i * 4 + 1) <= (others => '0');
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dmem_memory(i * 4 + 2) <= (others => '0');
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dmem_memory(i * 4 + 2) <= (others => '0');
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dmem_memory(i * 4 + 3) <= (others => '0');
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dmem_memory(i * 4 + 3) <= (others => '0');
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end if;
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end if;
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end loop;
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end loop;
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dmem_initialized <= true;
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dmem_initialized <= true;
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end if;
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end if;
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if rising_edge(clk) then
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if rising_edge(clk) then
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if dmem_write_ack = '1' then
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if dmem_write_ack = '1' then
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dmem_write_ack <= '0';
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dmem_write_ack <= '0';
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elsif dmem_write_req = '1' then
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elsif dmem_write_req = '1' then
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case dmem_data_size is
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case dmem_data_size is
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when b"00" => -- 32 bits
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when b"00" => -- 32 bits
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dmem_memory(to_integer(unsigned(dmem_address)) + 0) <= dmem_data_out(7 downto 0);
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dmem_memory(to_integer(unsigned(dmem_address)) + 0) <= dmem_data_out(7 downto 0);
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dmem_memory(to_integer(unsigned(dmem_address)) + 1) <= dmem_data_out(15 downto 8);
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dmem_memory(to_integer(unsigned(dmem_address)) + 1) <= dmem_data_out(15 downto 8);
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dmem_memory(to_integer(unsigned(dmem_address)) + 2) <= dmem_data_out(23 downto 16);
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dmem_memory(to_integer(unsigned(dmem_address)) + 2) <= dmem_data_out(23 downto 16);
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dmem_memory(to_integer(unsigned(dmem_address)) + 3) <= dmem_data_out(31 downto 24);
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dmem_memory(to_integer(unsigned(dmem_address)) + 3) <= dmem_data_out(31 downto 24);
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when b"01" => -- 8 bits
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when b"01" => -- 8 bits
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dmem_memory(to_integer(unsigned(dmem_address))) <= dmem_data_out(7 downto 0);
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dmem_memory(to_integer(unsigned(dmem_address))) <= dmem_data_out(7 downto 0);
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when b"10" => -- 16 bits
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when b"10" => -- 16 bits
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dmem_memory(to_integer(unsigned(dmem_address)) + 0) <= dmem_data_out( 7 downto 0);
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dmem_memory(to_integer(unsigned(dmem_address)) + 0) <= dmem_data_out( 7 downto 0);
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dmem_memory(to_integer(unsigned(dmem_address)) + 1) <= dmem_data_out(15 downto 8);
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dmem_memory(to_integer(unsigned(dmem_address)) + 1) <= dmem_data_out(15 downto 8);
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when others => -- Reserved for possible future 64 bit support
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when others => -- Reserved for possible future 64 bit support
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end case;
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end case;
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dmem_write_ack <= '1';
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dmem_write_ack <= '1';
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end if;
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end if;
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end if;
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end if;
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end process dmem_init_and_write;
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end process dmem_init_and_write;
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initialized <= imem_initialized and dmem_initialized;
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initialized <= imem_initialized and dmem_initialized;
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--! Instruction memory read process.
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--! Instruction memory read process.
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imem_read: process(clk)
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imem_read: process(clk)
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if reset = '1' then
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if reset = '1' then
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imem_ack <= '0';
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imem_ack <= '0';
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else
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else
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if to_integer(unsigned(imem_address)) > IMEM_END then
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if to_integer(unsigned(imem_address)) > IMEM_END then
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imem_data_in <= (others => 'X');
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imem_data_in <= (others => 'X');
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else
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else
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imem_data_in <= imem_memory(to_integer(unsigned(imem_address)) + 3)
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imem_data_in <= imem_memory(to_integer(unsigned(imem_address)) + 3)
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& imem_memory(to_integer(unsigned(imem_address)) + 2)
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& imem_memory(to_integer(unsigned(imem_address)) + 2)
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& imem_memory(to_integer(unsigned(imem_address)) + 1)
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& imem_memory(to_integer(unsigned(imem_address)) + 1)
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& imem_memory(to_integer(unsigned(imem_address)) + 0);
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& imem_memory(to_integer(unsigned(imem_address)) + 0);
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end if;
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end if;
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|
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imem_ack <= '1';
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imem_ack <= '1';
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end if;
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end if;
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end if;
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end if;
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end process imem_read;
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end process imem_read;
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|
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--! Data memory read process.
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--! Data memory read process.
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dmem_read: process(clk)
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dmem_read: process(clk)
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if dmem_read_ack = '1' then
|
if dmem_read_ack = '1' then
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dmem_read_ack <= '0';
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dmem_read_ack <= '0';
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elsif dmem_read_req = '1' then
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elsif dmem_read_req = '1' then
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case dmem_data_size is
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case dmem_data_size is
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when b"00" => -- 32 bits
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when b"00" => -- 32 bits
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dmem_data_in <= dmem_memory(to_integer(unsigned(dmem_address) + 3))
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dmem_data_in <= dmem_memory(to_integer(unsigned(dmem_address) + 3))
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& dmem_memory(to_integer(unsigned(dmem_address) + 2))
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& dmem_memory(to_integer(unsigned(dmem_address) + 2))
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& dmem_memory(to_integer(unsigned(dmem_address) + 1))
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& dmem_memory(to_integer(unsigned(dmem_address) + 1))
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& dmem_memory(to_integer(unsigned(dmem_address) + 0));
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& dmem_memory(to_integer(unsigned(dmem_address) + 0));
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when b"10" => -- 16 bits
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when b"10" => -- 16 bits
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dmem_data_in(15 downto 8) <= dmem_memory(to_integer(unsigned(dmem_address)) + 1);
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dmem_data_in(15 downto 8) <= dmem_memory(to_integer(unsigned(dmem_address)) + 1);
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dmem_data_in( 7 downto 0) <= dmem_memory(to_integer(unsigned(dmem_address)) + 0);
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dmem_data_in( 7 downto 0) <= dmem_memory(to_integer(unsigned(dmem_address)) + 0);
|
when b"01" => -- 8 bits
|
when b"01" => -- 8 bits
|
dmem_data_in(7 downto 0) <= dmem_memory(to_integer(unsigned(dmem_address)));
|
dmem_data_in(7 downto 0) <= dmem_memory(to_integer(unsigned(dmem_address)));
|
when others => -- Reserved for possible future 64 bit support
|
when others => -- Reserved for possible future 64 bit support
|
end case;
|
end case;
|
dmem_read_ack <= '1';
|
dmem_read_ack <= '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process dmem_read;
|
end process dmem_read;
|
|
|
stimulus: process
|
stimulus: process
|
begin
|
begin
|
wait until initialized = true;
|
wait until initialized = true;
|
report "Testbench initialized, starting behavioural simulation..." severity NOTE;
|
report "Testbench initialized, starting behavioural simulation..." severity NOTE;
|
wait for clk_period * 2;
|
wait for clk_period * 2;
|
|
|
-- Release the processor from reset:
|
-- Release the processor from reset:
|
reset <= '0';
|
reset <= '0';
|
wait for clk_period;
|
wait for clk_period;
|
|
|
wait until tohost_write_en = '1';
|
wait until tohost_write_en = '1';
|
wait for clk_period; -- Let the signal "settle", because of clock edges
|
wait for clk_period; -- Let the signal "settle", because of clock edges
|
if tohost_data = x"00000001" then
|
if tohost_data = x"00000001" then
|
report "Success!" severity NOTE;
|
report "Success!" severity NOTE;
|
else
|
else
|
report "Failure in test " & integer'image(to_integer(shift_right(unsigned(tohost_data), 1))) & "!" severity NOTE;
|
report "Failure in test " & integer'image(to_integer(shift_right(unsigned(tohost_data), 1))) & "!" severity NOTE;
|
end if;
|
end if;
|
|
|
simulation_finished <= true;
|
simulation_finished <= true;
|
wait;
|
wait;
|
end process stimulus;
|
end process stimulus;
|
|
|
end architecture testbench;
|
end architecture testbench;
|
|
|
