-- The Potato Processor - A simple processor for FPGAs
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-- The Potato Processor - A simple processor for FPGAs
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-- (c) Kristian Klomsten Skordal 2014 <kristian.skordal@wafflemail.net>
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-- (c) Kristian Klomsten Skordal 2014 <kristian.skordal@wafflemail.net>
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-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
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-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_textio.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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use std.textio.all;
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use work.pp_constants.all;
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use work.pp_constants.all;
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use work.pp_utilities.all;
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use work.pp_utilities.all;
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--! @brief Testbench providing a full SoC architecture connected with a Wishbone bus.
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--! @brief Testbench providing a full SoC architecture connected with a Wishbone bus.
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entity tb_soc is
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entity tb_soc is
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generic(
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generic(
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IMEM_SIZE : natural := 2048; --! Size of the instruction memory in bytes.
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IMEM_SIZE : natural := 4096; --! Size of the instruction memory in bytes.
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DMEM_SIZE : natural := 2048; --! Size of the data memory in bytes.
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DMEM_SIZE : natural := 4096; --! Size of the data memory in bytes.
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RESET_ADDRESS : std_logic_vector := x"00000200"; --! Processor reset address
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IMEM_START_ADDR : std_logic_vector := x"00000100"; --! Instruction memory start address
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IMEM_FILENAME : string := "imem_testfile.hex"; --! File containing the contents of instruction memory.
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IMEM_FILENAME : string := "imem_testfile.hex"; --! File containing the contents of instruction memory.
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DMEM_FILENAME : string := "dmem_testfile.hex" --! File containing the contents of data memory.
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DMEM_FILENAME : string := "dmem_testfile.hex" --! File containing the contents of data memory.
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);
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);
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end entity tb_soc;
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end entity tb_soc;
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architecture testbench of tb_soc is
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architecture testbench of tb_soc is
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-- Clock signals:
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-- Clock signals:
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signal clk : std_logic;
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signal clk : std_logic;
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constant clk_period : time := 10 ns;
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constant clk_period : time := 10 ns;
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signal timer_clk : std_logic;
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constant timer_clk_period : time := 100 ns;
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-- Reset:
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-- Reset:
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signal reset : std_logic := '1';
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signal reset : std_logic := '1';
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-- Interrupts:
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-- Interrupts:
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signal irq : std_logic_vector(7 downto 0) := (others => '0');
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signal irq : std_logic_vector(7 downto 0) := (others => '0');
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-- HTIF:
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-- HTIF:
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signal fromhost_data, tohost_data : std_logic_vector(31 downto 0);
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signal fromhost_data, tohost_data : std_logic_vector(31 downto 0);
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signal fromhost_updated : std_logic := '0';
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signal fromhost_updated : std_logic := '0';
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signal tohost_updated : std_logic;
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signal tohost_updated : std_logic;
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-- Instruction memory signals:
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-- Instruction memory signals:
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signal imem_adr_in : std_logic_vector(log2(IMEM_SIZE) - 1 downto 0);
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signal imem_adr_in : std_logic_vector(log2(IMEM_SIZE) - 1 downto 0);
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signal imem_dat_in : std_logic_vector(31 downto 0);
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signal imem_dat_in : std_logic_vector(31 downto 0);
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signal imem_dat_out : std_logic_vector(31 downto 0);
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signal imem_dat_out : std_logic_vector(31 downto 0);
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signal imem_cyc_in : std_logic;
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signal imem_cyc_in : std_logic;
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signal imem_stb_in : std_logic;
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signal imem_stb_in : std_logic;
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signal imem_sel_in : std_logic_vector(3 downto 0);
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signal imem_sel_in : std_logic_vector(3 downto 0);
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signal imem_we_in : std_logic;
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signal imem_we_in : std_logic;
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signal imem_ack_out : std_logic;
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signal imem_ack_out : std_logic;
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-- Data memory signals:
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-- Data memory signals:
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signal dmem_adr_in : std_logic_vector(log2(DMEM_SIZE) - 1 downto 0);
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signal dmem_adr_in : std_logic_vector(log2(DMEM_SIZE) - 1 downto 0);
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signal dmem_dat_in : std_logic_vector(31 downto 0);
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signal dmem_dat_in : std_logic_vector(31 downto 0);
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signal dmem_dat_out : std_logic_vector(31 downto 0);
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signal dmem_dat_out : std_logic_vector(31 downto 0);
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signal dmem_cyc_in : std_logic;
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signal dmem_cyc_in : std_logic;
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signal dmem_stb_in : std_logic;
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signal dmem_stb_in : std_logic;
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signal dmem_sel_in : std_logic_vector(3 downto 0);
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signal dmem_sel_in : std_logic_vector(3 downto 0);
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signal dmem_we_in : std_logic;
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signal dmem_we_in : std_logic;
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signal dmem_ack_out : std_logic;
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signal dmem_ack_out : std_logic;
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-- Processor signals:
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-- Processor signals:
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signal p_adr_out : std_logic_vector(31 downto 0);
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signal p_adr_out : std_logic_vector(31 downto 0);
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signal p_dat_out : std_logic_vector(31 downto 0);
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signal p_dat_out : std_logic_vector(31 downto 0);
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signal p_dat_in : std_logic_vector(31 downto 0);
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signal p_dat_in : std_logic_vector(31 downto 0);
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signal p_cyc_out : std_logic;
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signal p_cyc_out : std_logic;
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signal p_stb_out : std_logic;
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signal p_stb_out : std_logic;
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signal p_sel_out : std_logic_vector(3 downto 0);
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signal p_sel_out : std_logic_vector(3 downto 0);
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signal p_we_out : std_logic;
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signal p_we_out : std_logic;
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signal p_ack_in : std_logic;
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signal p_ack_in : std_logic;
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-- Arbitrated wishbone signals:
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-- Arbitrated wishbone signals:
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signal wb_adr : std_logic_vector(31 downto 0);
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signal wb_adr : std_logic_vector(31 downto 0);
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signal wb_dat : std_logic_vector(31 downto 0);
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signal wb_dat : std_logic_vector(31 downto 0);
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signal wb_sel : std_logic_vector( 3 downto 0);
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signal wb_sel : std_logic_vector( 3 downto 0);
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signal wb_cyc : std_logic;
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signal wb_cyc : std_logic;
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signal wb_stb : std_logic;
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signal wb_stb : std_logic;
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signal wb_we : std_logic;
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signal wb_we : std_logic;
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-- Initialization "module" signals:
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-- Initialization "module" signals:
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signal init_adr_out : std_logic_vector(31 downto 0) := (others => '0');
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signal init_adr_out : std_logic_vector(31 downto 0) := (others => '0');
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signal init_dat_out : std_logic_vector(31 downto 0) := (others => '0');
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signal init_dat_out : std_logic_vector(31 downto 0) := (others => '0');
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signal init_cyc_out : std_logic := '0';
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signal init_cyc_out : std_logic := '0';
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signal init_stb_out : std_logic := '0';
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signal init_stb_out : std_logic := '0';
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signal init_we_out : std_logic := '1';
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signal init_we_out : std_logic := '1';
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-- Processor reset signals:
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-- Processor reset signals:
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signal processor_reset : std_logic := '1';
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signal processor_reset : std_logic := '1';
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-- Simulation control:
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-- Simulation control:
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signal initialized : boolean := false;
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signal initialized : boolean := false;
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signal simulation_finished : boolean := false;
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signal simulation_finished : boolean := false;
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begin
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begin
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processor: entity work.pp_potato
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processor: entity work.pp_potato
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port map(
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generic map(
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RESET_ADDRESS => RESET_ADDRESS
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) port map(
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clk => clk,
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clk => clk,
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reset => processor_reset,
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reset => processor_reset,
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timer_clk => timer_clk,
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irq => irq,
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irq => irq,
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fromhost_data => fromhost_data,
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fromhost_data => fromhost_data,
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fromhost_updated => fromhost_updated,
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fromhost_updated => fromhost_updated,
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tohost_data => tohost_data,
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tohost_data => tohost_data,
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tohost_updated => tohost_updated,
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tohost_updated => tohost_updated,
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wb_adr_out => p_adr_out,
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wb_adr_out => p_adr_out,
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wb_sel_out => p_sel_out,
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wb_sel_out => p_sel_out,
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wb_cyc_out => p_cyc_out,
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wb_cyc_out => p_cyc_out,
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wb_stb_out => p_stb_out,
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wb_stb_out => p_stb_out,
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wb_we_out => p_we_out,
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wb_we_out => p_we_out,
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wb_dat_out => p_dat_out,
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wb_dat_out => p_dat_out,
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wb_dat_in => p_dat_in,
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wb_dat_in => p_dat_in,
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wb_ack_in => p_ack_in
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wb_ack_in => p_ack_in
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);
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);
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imem: entity work.pp_soc_memory
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imem: entity work.pp_soc_memory
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generic map(
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generic map(
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MEMORY_SIZE => IMEM_SIZE
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MEMORY_SIZE => IMEM_SIZE
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) port map(
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) port map(
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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wb_adr_in => imem_adr_in,
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wb_adr_in => imem_adr_in,
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wb_dat_in => imem_dat_in,
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wb_dat_in => imem_dat_in,
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wb_dat_out => imem_dat_out,
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wb_dat_out => imem_dat_out,
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wb_cyc_in => imem_cyc_in,
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wb_cyc_in => imem_cyc_in,
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wb_stb_in => imem_stb_in,
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wb_stb_in => imem_stb_in,
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wb_sel_in => imem_sel_in,
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wb_sel_in => imem_sel_in,
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wb_we_in => imem_we_in,
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wb_we_in => imem_we_in,
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wb_ack_out => imem_ack_out
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wb_ack_out => imem_ack_out
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);
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);
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dmem: entity work.pp_soc_memory
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dmem: entity work.pp_soc_memory
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generic map(
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generic map(
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MEMORY_SIZE => DMEM_SIZE
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MEMORY_SIZE => DMEM_SIZE
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) port map(
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) port map(
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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wb_adr_in => dmem_adr_in,
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wb_adr_in => dmem_adr_in,
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wb_dat_in => dmem_dat_in,
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wb_dat_in => dmem_dat_in,
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wb_dat_out => dmem_dat_out,
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wb_dat_out => dmem_dat_out,
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wb_cyc_in => dmem_cyc_in,
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wb_cyc_in => dmem_cyc_in,
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wb_stb_in => dmem_stb_in,
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wb_stb_in => dmem_stb_in,
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wb_sel_in => dmem_sel_in,
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wb_sel_in => dmem_sel_in,
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wb_we_in => dmem_we_in,
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wb_we_in => dmem_we_in,
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wb_ack_out => dmem_ack_out
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wb_ack_out => dmem_ack_out
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);
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);
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imem_adr_in <= wb_adr(imem_adr_in'range);
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imem_adr_in <= wb_adr(imem_adr_in'range);
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imem_dat_in <= wb_dat;
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imem_dat_in <= wb_dat;
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imem_we_in <= wb_we;
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imem_we_in <= wb_we;
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imem_sel_in <= wb_sel;
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imem_sel_in <= wb_sel;
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dmem_adr_in <= wb_adr(dmem_adr_in'range);
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dmem_adr_in <= wb_adr(dmem_adr_in'range);
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dmem_dat_in <= wb_dat;
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dmem_dat_in <= wb_dat;
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dmem_we_in <= wb_we;
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dmem_we_in <= wb_we;
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dmem_sel_in <= wb_sel;
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dmem_sel_in <= wb_sel;
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address_decoder: process(wb_adr, imem_dat_out, imem_ack_out, dmem_dat_out, dmem_ack_out,
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address_decoder: process(wb_adr, imem_dat_out, imem_ack_out, dmem_dat_out, dmem_ack_out,
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wb_cyc, wb_stb)
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wb_cyc, wb_stb)
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begin
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begin
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if to_integer(unsigned(wb_adr)) < IMEM_SIZE then
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if to_integer(unsigned(wb_adr)) < IMEM_SIZE then
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p_dat_in <= imem_dat_out;
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p_dat_in <= imem_dat_out;
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p_ack_in <= imem_ack_out;
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p_ack_in <= imem_ack_out;
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imem_cyc_in <= wb_cyc;
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imem_cyc_in <= wb_cyc;
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imem_stb_in <= wb_stb;
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imem_stb_in <= wb_stb;
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dmem_cyc_in <= '0';
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dmem_cyc_in <= '0';
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dmem_stb_in <= '0';
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dmem_stb_in <= '0';
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else
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else
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p_dat_in <= dmem_dat_out;
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p_dat_in <= dmem_dat_out;
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p_ack_in <= dmem_ack_out;
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p_ack_in <= dmem_ack_out;
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dmem_cyc_in <= wb_cyc;
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dmem_cyc_in <= wb_cyc;
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dmem_stb_in <= wb_stb;
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dmem_stb_in <= wb_stb;
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imem_cyc_in <= '0';
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imem_cyc_in <= '0';
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imem_stb_in <= '0';
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imem_stb_in <= '0';
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end if;
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end if;
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end process address_decoder;
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end process address_decoder;
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arbiter: process(initialized, init_adr_out, init_dat_out, init_cyc_out, init_stb_out, init_we_out,
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arbiter: process(initialized, init_adr_out, init_dat_out, init_cyc_out, init_stb_out, init_we_out,
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p_adr_out, p_dat_out, p_cyc_out, p_stb_out, p_we_out, p_sel_out)
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p_adr_out, p_dat_out, p_cyc_out, p_stb_out, p_we_out, p_sel_out)
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begin
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begin
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if not initialized then
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if not initialized then
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wb_adr <= init_adr_out;
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wb_adr <= init_adr_out;
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wb_dat <= init_dat_out;
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wb_dat <= init_dat_out;
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wb_cyc <= init_cyc_out;
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wb_cyc <= init_cyc_out;
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wb_stb <= init_stb_out;
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wb_stb <= init_stb_out;
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wb_we <= init_we_out;
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wb_we <= init_we_out;
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wb_sel <= x"f";
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wb_sel <= x"f";
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else
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else
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wb_adr <= p_adr_out;
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wb_adr <= p_adr_out;
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wb_dat <= p_dat_out;
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wb_dat <= p_dat_out;
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wb_cyc <= p_cyc_out;
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wb_cyc <= p_cyc_out;
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wb_stb <= p_stb_out;
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wb_stb <= p_stb_out;
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wb_we <= p_we_out;
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wb_we <= p_we_out;
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wb_sel <= p_sel_out;
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wb_sel <= p_sel_out;
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end if;
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end if;
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end process arbiter;
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end process arbiter;
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initializer: process
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initializer: process
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file imem_file : text open READ_MODE is IMEM_FILENAME;
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file imem_file : text open READ_MODE is IMEM_FILENAME;
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file dmem_file : text open READ_MODE is DMEM_FILENAME;
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file dmem_file : text open READ_MODE is DMEM_FILENAME;
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variable input_line : line;
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variable input_line : line;
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variable input_index : natural;
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variable input_index : natural;
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variable input_value : std_logic_vector(31 downto 0);
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variable input_value : std_logic_vector(31 downto 0);
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variable temp : std_logic_vector(31 downto 0);
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variable temp : std_logic_vector(31 downto 0);
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|
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constant DMEM_START : natural := IMEM_SIZE;
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constant DMEM_START_ADDR : natural := IMEM_SIZE;
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begin
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begin
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if not initialized then
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if not initialized then
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-- Read the instruction memory file:
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-- Read the instruction memory file:
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for i in 0 to IMEM_SIZE loop
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for i in 0 to (IMEM_SIZE / 4) - 1 loop
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exit when endfile(imem_file);
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exit when endfile(imem_file);
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readline(imem_file, input_line);
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readline(imem_file, input_line);
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hread(input_line, input_value);
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hread(input_line, input_value);
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|
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init_adr_out <= std_logic_vector(to_unsigned(i * 4, init_adr_out'length));
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init_adr_out <= std_logic_vector(to_unsigned(to_integer(unsigned(IMEM_START_ADDR)) + (i * 4),
|
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init_adr_out'length));
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init_dat_out <= input_value;
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init_dat_out <= input_value;
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init_cyc_out <= '1';
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init_cyc_out <= '1';
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init_stb_out <= '1';
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init_stb_out <= '1';
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wait until imem_ack_out = '1';
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wait until imem_ack_out = '1';
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wait for clk_period;
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wait for clk_period;
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init_stb_out <= '0';
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init_stb_out <= '0';
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wait until imem_ack_out = '0';
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wait until imem_ack_out = '0';
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wait for clk_period;
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wait for clk_period;
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end loop;
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end loop;
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init_cyc_out <= '0';
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init_cyc_out <= '0';
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init_stb_out <= '0';
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init_stb_out <= '0';
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wait for clk_period;
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wait for clk_period;
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-- Read the data memory file:
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-- Read the data memory file:
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for i in 0 to DMEM_SIZE loop
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for i in 0 to (DMEM_SIZE / 4) - 1 loop
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exit when endfile(dmem_file);
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exit when endfile(dmem_file);
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readline(dmem_file, input_line);
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readline(dmem_file, input_line);
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hread(input_line, input_value);
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hread(input_line, input_value);
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|
|
|
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-- Swap endianness, TODO: prevent this, fix scripts/extract_hex.sh
|
-- Swap endianness, TODO: prevent this, fix scripts/extract_hex.sh
|
temp(7 downto 0) := input_value(31 downto 24);
|
temp(7 downto 0) := input_value(31 downto 24);
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temp(15 downto 8) := input_value(23 downto 16);
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temp(15 downto 8) := input_value(23 downto 16);
|
temp(23 downto 16) := input_value(15 downto 8);
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temp(23 downto 16) := input_value(15 downto 8);
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temp(31 downto 24) := input_value(7 downto 0);
|
temp(31 downto 24) := input_value(7 downto 0);
|
|
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input_value := temp;
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input_value := temp;
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|
|
init_adr_out <= std_logic_vector(to_unsigned(DMEM_START + (i * 4), init_adr_out'length));
|
init_adr_out <= std_logic_vector(to_unsigned(DMEM_START_ADDR + (i * 4), init_adr_out'length));
|
init_dat_out <= input_value;
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init_dat_out <= input_value;
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init_cyc_out <= '1';
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init_cyc_out <= '1';
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init_stb_out <= '1';
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init_stb_out <= '1';
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wait until dmem_ack_out = '1';
|
wait until dmem_ack_out = '1';
|
wait for clk_period;
|
wait for clk_period;
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init_stb_out <= '0';
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init_stb_out <= '0';
|
wait until dmem_ack_out = '0';
|
wait until dmem_ack_out = '0';
|
wait for clk_period;
|
wait for clk_period;
|
end loop;
|
end loop;
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|
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init_cyc_out <= '0';
|
init_cyc_out <= '0';
|
init_stb_out <= '0';
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init_stb_out <= '0';
|
wait for clk_period;
|
wait for clk_period;
|
|
|
initialized <= true;
|
initialized <= true;
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wait;
|
wait;
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end if;
|
end if;
|
end process initializer;
|
end process initializer;
|
|
|
clock: process
|
clock: process
|
begin
|
begin
|
clk <= '1';
|
clk <= '1';
|
wait for clk_period / 2;
|
wait for clk_period / 2;
|
clk <= '0';
|
clk <= '0';
|
wait for clk_period / 2;
|
wait for clk_period / 2;
|
|
|
if simulation_finished then
|
if simulation_finished then
|
wait;
|
wait;
|
end if;
|
end if;
|
end process clock;
|
end process clock;
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|
|
|
timer_clock: process
|
|
begin
|
|
timer_clk <= '1';
|
|
wait for timer_clk_period / 2;
|
|
timer_clk <= '0';
|
|
wait for timer_clk_period / 2;
|
|
|
|
if simulation_finished then
|
|
wait;
|
|
end if;
|
|
end process timer_clock;
|
|
|
stimulus: process
|
stimulus: process
|
begin
|
begin
|
wait for clk_period * 2;
|
wait for clk_period * 2;
|
reset <= '0';
|
reset <= '0';
|
|
|
wait until initialized;
|
wait until initialized;
|
processor_reset <= '0';
|
processor_reset <= '0';
|
|
|
wait until tohost_updated = '1';
|
wait until tohost_updated = '1';
|
wait for clk_period; -- Let the signal "settle", because of stupid clock edges
|
wait for clk_period; -- Let the signal "settle", because of stupid clock edges
|
if tohost_data = x"00000001" then
|
if tohost_data = x"00000001" then
|
report "Success!" severity NOTE;
|
report "Success!" severity NOTE;
|
else
|
else
|
report "Failure in test " & integer'image(to_integer(shift_right(unsigned(tohost_data), 1))) & "!" severity NOTE;
|
report "Failure in test " & integer'image(to_integer(shift_right(unsigned(tohost_data), 1))) & "!" severity NOTE;
|
end if;
|
end if;
|
|
|
simulation_finished <= true;
|
simulation_finished <= true;
|
wait;
|
wait;
|
end process stimulus;
|
end process stimulus;
|
|
|
end architecture testbench;
|
end architecture testbench;
|
|
|
