-- The Potato Processor - A simple processor for FPGAs
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-- The Potato Processor - A simple processor for FPGAs
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-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
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-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
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-- Report bugs and issues on <https://github.com/skordal/potato/issues>
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-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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entity tb_soc_memory is
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entity tb_soc_memory is
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end entity tb_soc_memory;
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end entity tb_soc_memory;
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architecture testbench of tb_soc_memory is
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architecture testbench of tb_soc_memory is
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-- Clock signal:
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-- Clock signal:
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signal clk : std_logic;
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signal clk : std_logic;
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constant clk_period : time := 10 ns;
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constant clk_period : time := 10 ns;
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-- Reset signal:
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-- Reset signal:
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signal reset : std_logic := '1';
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signal reset : std_logic := '1';
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-- Wishbone signals:
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-- Wishbone signals:
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signal wb_adr_in : std_logic_vector(31 downto 0);
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signal wb_adr_in : std_logic_vector(31 downto 0);
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signal wb_dat_in : std_logic_vector(31 downto 0);
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signal wb_dat_in : std_logic_vector(31 downto 0);
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signal wb_dat_out : std_logic_vector(31 downto 0);
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signal wb_dat_out : std_logic_vector(31 downto 0);
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signal wb_cyc_in : std_logic := '0';
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signal wb_cyc_in : std_logic := '0';
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signal wb_stb_in : std_logic := '0';
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signal wb_stb_in : std_logic := '0';
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signal wb_sel_in : std_logic_vector(3 downto 0) := (others => '1');
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signal wb_sel_in : std_logic_vector(3 downto 0) := (others => '1');
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signal wb_we_in : std_logic := '0';
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signal wb_we_in : std_logic := '0';
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signal wb_ack_out : std_logic;
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signal wb_ack_out : std_logic;
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begin
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begin
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uut: entity work.pp_soc_memory
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uut: entity work.pp_soc_memory
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port map(
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port map(
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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wb_adr_in => wb_adr_in,
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wb_adr_in => wb_adr_in,
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wb_dat_in => wb_dat_in,
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wb_dat_in => wb_dat_in,
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wb_dat_out => wb_dat_out,
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wb_dat_out => wb_dat_out,
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wb_cyc_in => wb_cyc_in,
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wb_cyc_in => wb_cyc_in,
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wb_stb_in => wb_stb_in,
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wb_stb_in => wb_stb_in,
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wb_sel_in => wb_sel_in,
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wb_sel_in => wb_sel_in,
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wb_we_in => wb_we_in,
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wb_we_in => wb_we_in,
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wb_ack_out => wb_ack_out
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wb_ack_out => wb_ack_out
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);
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);
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clock: process
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clock: process
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begin
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begin
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clk <= '1';
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clk <= '1';
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wait for clk_period / 2;
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wait for clk_period / 2;
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clk <= '0';
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clk <= '0';
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wait for clk_period / 2;
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wait for clk_period / 2;
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end process clock;
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end process clock;
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stimulus: process
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stimulus: process
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begin
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begin
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wait for clk_period;
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wait for clk_period;
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reset <= '0';
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reset <= '0';
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-- Write 32 bit of data to address 0:
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-- Write 32 bit of data to address 0:
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wb_adr_in <= x"00000000";
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wb_adr_in <= x"00000000";
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wb_dat_in <= x"deadbeef";
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wb_dat_in <= x"deadbeef";
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wb_cyc_in <= '1';
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wb_cyc_in <= '1';
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wb_stb_in <= '1';
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wb_stb_in <= '1';
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wb_we_in <= '1';
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wb_we_in <= '1';
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wait for clk_period;
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wait for clk_period;
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wb_stb_in <= '0';
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wb_stb_in <= '0';
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wb_cyc_in <= '0';
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wb_cyc_in <= '0';
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wait for clk_period;
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wait for clk_period;
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-- Write a block write of two 32-bit words at address 0 and 1:
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-- Write a block write of two 32-bit words at address 0 and 1:
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wb_adr_in <= x"00000000";
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wb_adr_in <= x"00000000";
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wb_dat_in <= x"feedbeef";
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wb_dat_in <= x"feedbeef";
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wb_cyc_in <= '1';
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wb_cyc_in <= '1';
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wb_stb_in <= '1';
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wb_stb_in <= '1';
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wait for clk_period;
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wait for clk_period;
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wb_stb_in <= '0';
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wb_stb_in <= '0';
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wb_adr_in <= x"00000004";
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wb_adr_in <= x"00000004";
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wb_dat_in <= x"f00dd00d";
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wb_dat_in <= x"f00dd00d";
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wait for clk_period;
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wait for clk_period;
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wb_stb_in <= '1';
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wb_stb_in <= '1';
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wait for clk_period;
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wait for clk_period;
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wb_stb_in <= '0';
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wb_stb_in <= '0';
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wb_cyc_in <= '0';
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wb_cyc_in <= '0';
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-- Read address 4:
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-- Read address 4:
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wait for clk_period;
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wait for clk_period;
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wb_we_in <= '0';
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wb_we_in <= '0';
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wb_adr_in <= x"00000000";
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wb_adr_in <= x"00000000";
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wb_cyc_in <= '1';
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wb_cyc_in <= '1';
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wb_stb_in <= '1';
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wb_stb_in <= '1';
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wait for clk_period;
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wait for clk_period;
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-- TODO: Make this testbench automatic.
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-- TODO: Make this testbench automatic.
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wait;
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wait;
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end process stimulus;
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end process stimulus;
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end architecture testbench;
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end architecture testbench;
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