library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use work.StimLog.all;
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use work.StimLog.all;
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entity TestBench55 is
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entity TestBench55 is
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end TestBench55;
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end TestBench55;
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architecture behaviour of TestBench55 is
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architecture behaviour of TestBench55 is
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signal Clk : std_logic := '0';
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signal Clk : std_logic := '0';
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signal Reset_n : std_logic := '0';
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signal Reset_n : std_logic := '0';
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signal T0CKI : std_logic := '0';
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signal T0CKI : std_logic := '0';
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signal Port_A : std_logic_vector(7 downto 0);
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signal Port_A : std_logic_vector(7 downto 0);
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signal Port_B : std_logic_vector(7 downto 0);
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signal Port_B : std_logic_vector(7 downto 0);
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signal Port_C : std_logic_vector(7 downto 0);
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signal Port_C : std_logic_vector(7 downto 0);
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begin
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begin
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p1 : entity work.P16C55 port map (Clk, Reset_n, T0CKI, Port_A, Port_B, Port_C);
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p1 : entity work.P16C55 port map (Clk, Reset_n, T0CKI, Port_A, Port_B, Port_C);
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as : AsyncStim generic map(FileName => "../../../rtl/vhdl/PPX16.vhd", InterCharDelay => 300 us, Baud => 48000, Bits => 8)
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as : AsyncStim generic map(FileName => "../../../rtl/vhdl/PPX16.vhd", InterCharDelay => 300 us, Baud => 48000, Bits => 8)
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port map(Port_A(1));
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port map(Port_A(1));
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al : AsyncLog generic map(FileName => "RX_Log.txt", Baud => 48000, Bits => 8)
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al : AsyncLog generic map(FileName => "RX_Log.txt", Baud => 48000, Bits => 8)
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port map(Port_A(0));
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port map(Port_A(0));
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Clk <= not Clk after 50 ns;
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Clk <= not Clk after 50 ns;
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Reset_n <= '1' after 200 ns;
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Reset_n <= '1' after 200 ns;
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end;
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end;
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