--
|
--
|
-- PIC16xx compatible microcontroller core
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-- PIC16xx compatible microcontroller core
|
--
|
--
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-- Version : 0222
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-- Version : 0222
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--
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--
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-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
|
-- Redistribution and use in source and synthezised forms, with or without
|
-- Redistribution and use in source and synthezised forms, with or without
|
-- modification, are permitted provided that the following conditions are met:
|
-- modification, are permitted provided that the following conditions are met:
|
--
|
--
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-- Redistributions of source code must retain the above copyright notice,
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-- Redistributions of source code must retain the above copyright notice,
|
-- this list of conditions and the following disclaimer.
|
-- this list of conditions and the following disclaimer.
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--
|
--
|
-- Redistributions in synthesized form must reproduce the above copyright
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-- Redistributions in synthesized form must reproduce the above copyright
|
-- notice, this list of conditions and the following disclaimer in the
|
-- notice, this list of conditions and the following disclaimer in the
|
-- documentation and/or other materials provided with the distribution.
|
-- documentation and/or other materials provided with the distribution.
|
--
|
--
|
-- Neither the name of the author nor the names of other contributors may
|
-- Neither the name of the author nor the names of other contributors may
|
-- be used to endorse or promote products derived from this software without
|
-- be used to endorse or promote products derived from this software without
|
-- specific prior written permission.
|
-- specific prior written permission.
|
--
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
-- POSSIBILITY OF SUCH DAMAGE.
|
-- POSSIBILITY OF SUCH DAMAGE.
|
--
|
--
|
-- Please report bugs to the author, but before you do so, please
|
-- Please report bugs to the author, but before you do so, please
|
-- make sure that this is not a derivative work and that
|
-- make sure that this is not a derivative work and that
|
-- you have the latest version of this file.
|
-- you have the latest version of this file.
|
--
|
--
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-- The latest version of this file can be found at:
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-- The latest version of this file can be found at:
|
-- http://www.opencores.org/cvsweb.shtml/t51/
|
-- http://www.opencores.org/cvsweb.shtml/t51/
|
--
|
--
|
-- Limitations :
|
-- Limitations :
|
--
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--
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-- File history :
|
-- File history :
|
--
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--
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|
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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|
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entity PPX_ALU is
|
entity PPX_ALU is
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generic(
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generic(
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InstructionLength : integer;
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InstructionLength : integer;
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TriState : boolean := false
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TriState : boolean := false
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);
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);
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port (
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port (
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Clk : in std_logic;
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Clk : in std_logic;
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ROM_Data : in std_logic_vector(InstructionLength - 1 downto 0);
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ROM_Data : in std_logic_vector(InstructionLength - 1 downto 0);
|
A : in std_logic_vector(7 downto 0);
|
A : in std_logic_vector(7 downto 0);
|
B : in std_logic_vector(7 downto 0);
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B : in std_logic_vector(7 downto 0);
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Q : out std_logic_vector(7 downto 0);
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Q : out std_logic_vector(7 downto 0);
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Skip : in std_logic;
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Skip : in std_logic;
|
Carry : in std_logic;
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Carry : in std_logic;
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Z_Skip : out std_logic;
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Z_Skip : out std_logic;
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STATUS_d : out std_logic_vector(2 downto 0);
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STATUS_d : out std_logic_vector(2 downto 0);
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STATUS_Wr : out std_logic_vector(2 downto 0)
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STATUS_Wr : out std_logic_vector(2 downto 0)
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);
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);
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end PPX_ALU;
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end PPX_ALU;
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|
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architecture rtl of PPX_ALU is
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architecture rtl of PPX_ALU is
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|
|
procedure AddSub(A : std_logic_vector(3 downto 0);
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procedure AddSub(A : std_logic_vector(3 downto 0);
|
B : std_logic_vector(3 downto 0);
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B : std_logic_vector(3 downto 0);
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Sub : std_logic;
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Sub : std_logic;
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Carry_In : std_logic;
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Carry_In : std_logic;
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signal Res : out std_logic_vector(3 downto 0);
|
signal Res : out std_logic_vector(3 downto 0);
|
signal Carry : out std_logic) is
|
signal Carry : out std_logic) is
|
variable B_i : unsigned(4 downto 0);
|
variable B_i : unsigned(4 downto 0);
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variable Full_Carry : unsigned(4 downto 0);
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variable Full_Carry : unsigned(4 downto 0);
|
variable Res_i : unsigned(4 downto 0);
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variable Res_i : unsigned(4 downto 0);
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begin
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begin
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if Sub = '1' then
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if Sub = '1' then
|
B_i := "0" & not unsigned(B);
|
B_i := "0" & not unsigned(B);
|
else
|
else
|
B_i := "0" & unsigned(B);
|
B_i := "0" & unsigned(B);
|
end if;
|
end if;
|
if (Sub = '1' and Carry_In = '1') or (Sub = '0' and Carry_In = '1') then
|
if (Sub = '1' and Carry_In = '1') or (Sub = '0' and Carry_In = '1') then
|
Full_Carry := "00001";
|
Full_Carry := "00001";
|
else
|
else
|
Full_Carry := "00000";
|
Full_Carry := "00000";
|
end if;
|
end if;
|
Res_i := unsigned("0" & A) + B_i + Full_Carry;
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Res_i := unsigned("0" & A) + B_i + Full_Carry;
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Carry <= Res_i(4);
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Carry <= Res_i(4);
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Res <= std_logic_vector(Res_i(3 downto 0));
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Res <= std_logic_vector(Res_i(3 downto 0));
|
end;
|
end;
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|
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signal Do_IDTEST : std_logic;
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signal Do_IDTEST : std_logic;
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signal Do_ADD : std_logic;
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signal Do_ADD : std_logic;
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signal Do_SUB : std_logic;
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signal Do_SUB : std_logic;
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signal Do_DEC : std_logic;
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signal Do_DEC : std_logic;
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signal Do_INC : std_logic;
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signal Do_INC : std_logic;
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signal Do_AND : std_logic;
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signal Do_AND : std_logic;
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signal Do_OR : std_logic;
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signal Do_OR : std_logic;
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signal Do_XOR : std_logic;
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signal Do_XOR : std_logic;
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signal Do_COM : std_logic;
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signal Do_COM : std_logic;
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signal Do_RRF : std_logic;
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signal Do_RRF : std_logic;
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signal Do_RLF : std_logic;
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signal Do_RLF : std_logic;
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signal Do_SWAP : std_logic;
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signal Do_SWAP : std_logic;
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signal Do_BITCLR : std_logic;
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signal Do_BITCLR : std_logic;
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signal Do_BITSET : std_logic;
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signal Do_BITSET : std_logic;
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signal Do_BITTESTCLR : std_logic;
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signal Do_BITTESTCLR : std_logic;
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signal Do_BITTESTSET : std_logic;
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signal Do_BITTESTSET : std_logic;
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signal Do_CLR : std_logic;
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signal Do_CLR : std_logic;
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|
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signal Inst_Top : std_logic_vector(11 downto 0);
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signal Inst_Top : std_logic_vector(11 downto 0);
|
|
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signal Bit_Pattern : std_logic_vector(7 downto 0);
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signal Bit_Pattern : std_logic_vector(7 downto 0);
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signal Bit_Test : std_logic_vector(7 downto 0);
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signal Bit_Test : std_logic_vector(7 downto 0);
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|
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signal Q_ID : std_logic_vector(7 downto 0);
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signal Q_ID : std_logic_vector(7 downto 0);
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signal Q_L : std_logic_vector(7 downto 0);
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signal Q_L : std_logic_vector(7 downto 0);
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signal Q_C : std_logic_vector(7 downto 0);
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signal Q_C : std_logic_vector(7 downto 0);
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signal Q_RR : std_logic_vector(7 downto 0);
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signal Q_RR : std_logic_vector(7 downto 0);
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signal Q_RL : std_logic_vector(7 downto 0);
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signal Q_RL : std_logic_vector(7 downto 0);
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signal Q_S : std_logic_vector(7 downto 0);
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signal Q_S : std_logic_vector(7 downto 0);
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signal Q_BC : std_logic_vector(7 downto 0);
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signal Q_BC : std_logic_vector(7 downto 0);
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signal Q_BS : std_logic_vector(7 downto 0);
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signal Q_BS : std_logic_vector(7 downto 0);
|
|
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signal DC_i : std_logic;
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signal DC_i : std_logic;
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signal AddSubRes : std_logic_vector(8 downto 0);
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signal AddSubRes : std_logic_vector(8 downto 0);
|
|
|
signal Q_i : std_logic_vector(7 downto 0);
|
signal Q_i : std_logic_vector(7 downto 0);
|
|
|
begin
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begin
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|
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Q <= Q_i;
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Q <= Q_i;
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|
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Inst_Top <= ROM_Data(InstructionLength - 1 downto InstructionLength - 12);
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Inst_Top <= ROM_Data(InstructionLength - 1 downto InstructionLength - 12);
|
|
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gNoTri : if not TriState generate
|
gNoTri : if not TriState generate
|
Q_i <= Q_ID when Do_INC = '1' or Do_DEC = '1' else
|
Q_i <= Q_ID when Do_INC = '1' or Do_DEC = '1' else
|
AddSubRes(7 downto 0) when Do_ADD = '1' OR Do_SUB = '1' else
|
AddSubRes(7 downto 0) when Do_ADD = '1' OR Do_SUB = '1' else
|
Q_L when Do_AND = '1' or Do_OR = '1' or Do_XOR = '1' else
|
Q_L when Do_AND = '1' or Do_OR = '1' or Do_XOR = '1' else
|
Q_C when Do_COM = '1' else
|
Q_C when Do_COM = '1' else
|
Q_RR when Do_RRF = '1' else
|
Q_RR when Do_RRF = '1' else
|
Q_RL when Do_RLF = '1' else
|
Q_RL when Do_RLF = '1' else
|
Q_S when Do_SWAP = '1' else
|
Q_S when Do_SWAP = '1' else
|
Q_BC when Do_BITCLR = '1' else
|
Q_BC when Do_BITCLR = '1' else
|
Q_BS when Do_BITSET = '1' else
|
Q_BS when Do_BITSET = '1' else
|
"00000000";
|
"00000000";
|
end generate;
|
end generate;
|
|
|
gTri : if TriState generate
|
gTri : if TriState generate
|
Q_i <= Q_ID when Do_INC = '1' or Do_DEC = '1' else "ZZZZZZZZ";
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Q_i <= Q_ID when Do_INC = '1' or Do_DEC = '1' else "ZZZZZZZZ";
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Q_i <= AddSubRes(7 downto 0) when Do_ADD = '1' OR Do_SUB = '1' else "ZZZZZZZZ";
|
Q_i <= AddSubRes(7 downto 0) when Do_ADD = '1' OR Do_SUB = '1' else "ZZZZZZZZ";
|
Q_i <= Q_L when Do_AND = '1' or Do_OR = '1' or Do_XOR = '1' else "ZZZZZZZZ";
|
Q_i <= Q_L when Do_AND = '1' or Do_OR = '1' or Do_XOR = '1' else "ZZZZZZZZ";
|
Q_i <= Q_C when Do_COM = '1' else "ZZZZZZZZ";
|
Q_i <= Q_C when Do_COM = '1' else "ZZZZZZZZ";
|
Q_i <= Q_RR when Do_RRF = '1' else "ZZZZZZZZ";
|
Q_i <= Q_RR when Do_RRF = '1' else "ZZZZZZZZ";
|
Q_i <= Q_RL when Do_RLF = '1' else "ZZZZZZZZ";
|
Q_i <= Q_RL when Do_RLF = '1' else "ZZZZZZZZ";
|
Q_i <= Q_S when Do_SWAP = '1' else "ZZZZZZZZ";
|
Q_i <= Q_S when Do_SWAP = '1' else "ZZZZZZZZ";
|
Q_i <= Q_BC when Do_BITCLR = '1' else "ZZZZZZZZ";
|
Q_i <= Q_BC when Do_BITCLR = '1' else "ZZZZZZZZ";
|
Q_i <= Q_BS when Do_BITSET = '1' else "ZZZZZZZZ";
|
Q_i <= Q_BS when Do_BITSET = '1' else "ZZZZZZZZ";
|
Q_i <= "00000000" when Do_CLR = '1' else "ZZZZZZZZ";
|
Q_i <= "00000000" when Do_CLR = '1' else "ZZZZZZZZ";
|
end generate;
|
end generate;
|
|
|
process (Clk)
|
process (Clk)
|
begin
|
begin
|
if Clk'event and Clk = '1' then
|
if Clk'event and Clk = '1' then
|
Do_ADD <= '0';
|
Do_ADD <= '0';
|
Do_SUB <= '0';
|
Do_SUB <= '0';
|
Do_AND <= '0';
|
Do_AND <= '0';
|
Do_OR <= '0';
|
Do_OR <= '0';
|
Do_XOR <= '0';
|
Do_XOR <= '0';
|
Do_IDTEST <= '0';
|
Do_IDTEST <= '0';
|
Do_INC <= '0';
|
Do_INC <= '0';
|
Do_DEC <= '0';
|
Do_DEC <= '0';
|
Do_COM <= '0';
|
Do_COM <= '0';
|
Do_RRF <= '0';
|
Do_RRF <= '0';
|
Do_RLF <= '0';
|
Do_RLF <= '0';
|
Do_SWAP <= '0';
|
Do_SWAP <= '0';
|
Do_BITCLR <= '0';
|
Do_BITCLR <= '0';
|
Do_BITSET <= '0';
|
Do_BITSET <= '0';
|
Do_BITTESTCLR <= '0';
|
Do_BITTESTCLR <= '0';
|
Do_BITTESTSET <= '0';
|
Do_BITTESTSET <= '0';
|
Do_CLR <= '0';
|
Do_CLR <= '0';
|
if Skip = '0' then
|
if Skip = '0' then
|
if InstructionLength = 12 then
|
if InstructionLength = 12 then
|
if Inst_Top(11 downto 6) = "000111" then
|
if Inst_Top(11 downto 6) = "000111" then
|
-- ADDWF
|
-- ADDWF
|
Do_ADD <= '1';
|
Do_ADD <= '1';
|
end if;
|
end if;
|
if Inst_Top(11 downto 6) = "000010" then
|
if Inst_Top(11 downto 6) = "000010" then
|
-- SUBWF
|
-- SUBWF
|
Do_SUB <= '1';
|
Do_SUB <= '1';
|
end if;
|
end if;
|
if Inst_Top(11 downto 6) = "000101" or Inst_Top(11 downto 8) = "1110" then
|
if Inst_Top(11 downto 6) = "000101" or Inst_Top(11 downto 8) = "1110" then
|
-- ANDWF, ANDLW
|
-- ANDWF, ANDLW
|
Do_AND <= '1';
|
Do_AND <= '1';
|
end if;
|
end if;
|
if Inst_Top(11 downto 6) = "000100" or Inst_Top(11 downto 8) = "1101" then
|
if Inst_Top(11 downto 6) = "000100" or Inst_Top(11 downto 8) = "1101" then
|
-- IORWF, IORLW
|
-- IORWF, IORLW
|
Do_OR <= '1';
|
Do_OR <= '1';
|
end if;
|
end if;
|
if Inst_Top(11 downto 6) = "000110" or Inst_Top(11 downto 8) = "1111" then
|
if Inst_Top(11 downto 6) = "000110" or Inst_Top(11 downto 8) = "1111" then
|
-- XORWF, XORLW
|
-- XORWF, XORLW
|
Do_XOR <= '1';
|
Do_XOR <= '1';
|
end if;
|
end if;
|
else
|
else
|
if Inst_Top(11 downto 6) = "000111" or Inst_Top(11 downto 7) = "11111" then
|
if Inst_Top(11 downto 6) = "000111" or Inst_Top(11 downto 7) = "11111" then
|
-- ADDWF, ADDLW
|
-- ADDWF, ADDLW
|
Do_ADD <= '1';
|
Do_ADD <= '1';
|
end if;
|
end if;
|
if Inst_Top(11 downto 6) = "000010" or Inst_Top(11 downto 7) = "11110" then
|
if Inst_Top(11 downto 6) = "000010" or Inst_Top(11 downto 7) = "11110" then
|
-- SUBWF, SUBLW
|
-- SUBWF, SUBLW
|
Do_SUB <= '1';
|
Do_SUB <= '1';
|
end if;
|
end if;
|
if Inst_Top(11 downto 6) = "000101" or Inst_Top(11 downto 6) = "111001" then
|
if Inst_Top(11 downto 6) = "000101" or Inst_Top(11 downto 6) = "111001" then
|
-- ANDWF, ANDLW
|
-- ANDWF, ANDLW
|
Do_AND <= '1';
|
Do_AND <= '1';
|
end if;
|
end if;
|
if Inst_Top(11 downto 6) = "000100" or Inst_Top(11 downto 6) = "111000" then
|
if Inst_Top(11 downto 6) = "000100" or Inst_Top(11 downto 6) = "111000" then
|
-- IORWF, IORLW
|
-- IORWF, IORLW
|
Do_OR <= '1';
|
Do_OR <= '1';
|
end if;
|
end if;
|
if Inst_Top(11 downto 6) = "000110" or Inst_Top(11 downto 6) = "111010" then
|
if Inst_Top(11 downto 6) = "000110" or Inst_Top(11 downto 6) = "111010" then
|
-- XORWF, XORLW
|
-- XORWF, XORLW
|
Do_XOR <= '1';
|
Do_XOR <= '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
if Inst_Top(11 downto 9) = "001" and Inst_Top(7 downto 6) = "11" then
|
if Inst_Top(11 downto 9) = "001" and Inst_Top(7 downto 6) = "11" then
|
-- INC/DEC w conditional skip
|
-- INC/DEC w conditional skip
|
Do_IDTEST <= '1';
|
Do_IDTEST <= '1';
|
end if;
|
end if;
|
if Inst_Top(11 downto 6) = "001010" or Inst_Top(11 downto 6) = "001111" then
|
if Inst_Top(11 downto 6) = "001010" or Inst_Top(11 downto 6) = "001111" then
|
-- INCF, INCFSZ
|
-- INCF, INCFSZ
|
Do_INC <= '1';
|
Do_INC <= '1';
|
end if;
|
end if;
|
if Inst_Top(11 downto 6) = "000011" or Inst_Top(11 downto 6) = "001011" then
|
if Inst_Top(11 downto 6) = "000011" or Inst_Top(11 downto 6) = "001011" then
|
-- DECF, DECFSZ,
|
-- DECF, DECFSZ,
|
Do_DEC <= '1';
|
Do_DEC <= '1';
|
end if;
|
end if;
|
if Inst_Top(11 downto 6) = "001001" then
|
if Inst_Top(11 downto 6) = "001001" then
|
-- COMF
|
-- COMF
|
Do_COM <= '1';
|
Do_COM <= '1';
|
end if;
|
end if;
|
if Inst_Top(11 downto 6) = "001100" then
|
if Inst_Top(11 downto 6) = "001100" then
|
-- RRF
|
-- RRF
|
Do_RRF <= '1';
|
Do_RRF <= '1';
|
end if;
|
end if;
|
if Inst_Top(11 downto 6) = "001101" then
|
if Inst_Top(11 downto 6) = "001101" then
|
-- RLF
|
-- RLF
|
Do_RLF <= '1';
|
Do_RLF <= '1';
|
end if;
|
end if;
|
if Inst_Top(11 downto 6) = "001110" then
|
if Inst_Top(11 downto 6) = "001110" then
|
-- SWAPF
|
-- SWAPF
|
Do_SWAP <= '1';
|
Do_SWAP <= '1';
|
end if;
|
end if;
|
if Inst_Top(11 downto 8) = "0100" then
|
if Inst_Top(11 downto 8) = "0100" then
|
-- BCF
|
-- BCF
|
Do_BITCLR <= '1';
|
Do_BITCLR <= '1';
|
end if;
|
end if;
|
if Inst_Top(11 downto 8) = "0101" then
|
if Inst_Top(11 downto 8) = "0101" then
|
-- BSF
|
-- BSF
|
Do_BITSET <= '1';
|
Do_BITSET <= '1';
|
end if;
|
end if;
|
if Inst_Top(11 downto 8) = "0110" then
|
if Inst_Top(11 downto 8) = "0110" then
|
-- BTFSC
|
-- BTFSC
|
Do_BITTESTCLR <= '1';
|
Do_BITTESTCLR <= '1';
|
end if;
|
end if;
|
if Inst_Top(11 downto 8) = "0111" then
|
if Inst_Top(11 downto 8) = "0111" then
|
-- BTFSS
|
-- BTFSS
|
Do_BITTESTSET <= '1';
|
Do_BITTESTSET <= '1';
|
end if;
|
end if;
|
if Inst_Top(11 downto 6) = "000001" then
|
if Inst_Top(11 downto 6) = "000001" then
|
-- CLRF, CLRW
|
-- CLRF, CLRW
|
Do_CLR <= '1';
|
Do_CLR <= '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
case Inst_Top(7 downto 5) is
|
case Inst_Top(7 downto 5) is
|
when "000" =>
|
when "000" =>
|
Bit_Pattern <= "00000001";
|
Bit_Pattern <= "00000001";
|
when "001" =>
|
when "001" =>
|
Bit_Pattern <= "00000010";
|
Bit_Pattern <= "00000010";
|
when "010" =>
|
when "010" =>
|
Bit_Pattern <= "00000100";
|
Bit_Pattern <= "00000100";
|
when "011" =>
|
when "011" =>
|
Bit_Pattern <= "00001000";
|
Bit_Pattern <= "00001000";
|
when "100" =>
|
when "100" =>
|
Bit_Pattern <= "00010000";
|
Bit_Pattern <= "00010000";
|
when "101" =>
|
when "101" =>
|
Bit_Pattern <= "00100000";
|
Bit_Pattern <= "00100000";
|
when "110" =>
|
when "110" =>
|
Bit_Pattern <= "01000000";
|
Bit_Pattern <= "01000000";
|
when others =>
|
when others =>
|
Bit_Pattern <= "10000000";
|
Bit_Pattern <= "10000000";
|
end case;
|
end case;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
Q_ID <= std_logic_vector(unsigned(A) + 1) when Do_INC = '1' else
|
Q_ID <= std_logic_vector(unsigned(A) + 1) when Do_INC = '1' else
|
std_logic_vector(unsigned(A) - 1);
|
std_logic_vector(unsigned(A) - 1);
|
|
|
AddSub(A(3 downto 0), B(3 downto 0), Do_SUB, Do_SUB, AddSubRes(3 downto 0), DC_i);
|
AddSub(A(3 downto 0), B(3 downto 0), Do_SUB, Do_SUB, AddSubRes(3 downto 0), DC_i);
|
AddSub(A(7 downto 4), B(7 downto 4), Do_SUB, DC_i, AddSubRes(7 downto 4), AddSubRes(8));
|
AddSub(A(7 downto 4), B(7 downto 4), Do_SUB, DC_i, AddSubRes(7 downto 4), AddSubRes(8));
|
|
|
Q_L <= (A and B) when Do_AND = '1' else
|
Q_L <= (A and B) when Do_AND = '1' else
|
(A or B) when Do_OR = '1' else
|
(A or B) when Do_OR = '1' else
|
(A xor B);
|
(A xor B);
|
Q_C <= (not A);
|
Q_C <= (not A);
|
|
|
Q_RR <= Carry & A(7 downto 1);
|
Q_RR <= Carry & A(7 downto 1);
|
Q_RL <= A(6 downto 0) & Carry;
|
Q_RL <= A(6 downto 0) & Carry;
|
|
|
Q_S <= A(3 downto 0) & A(7 downto 4);
|
Q_S <= A(3 downto 0) & A(7 downto 4);
|
|
|
Q_BC <= ((not Bit_Pattern) and A);
|
Q_BC <= ((not Bit_Pattern) and A);
|
Q_BS <= (Bit_Pattern or A);
|
Q_BS <= (Bit_Pattern or A);
|
|
|
Bit_Test <= Bit_Pattern and A;
|
Bit_Test <= Bit_Pattern and A;
|
|
|
Z_Skip <= '1' when (Do_IDTEST = '1' and Q_ID = "00000000") or
|
Z_Skip <= '1' when (Do_IDTEST = '1' and Q_ID = "00000000") or
|
(Bit_Test /= "00000000" and Do_BITTESTSET = '1') or
|
(Bit_Test /= "00000000" and Do_BITTESTSET = '1') or
|
(Bit_Test = "00000000" and Do_BITTESTCLR = '1') else '0';
|
(Bit_Test = "00000000" and Do_BITTESTCLR = '1') else '0';
|
|
|
STATUS_d(2) <= '1' when Q_i(7 downto 0) = "00000000" else '0';
|
STATUS_d(2) <= '1' when Q_i(7 downto 0) = "00000000" else '0';
|
STATUS_d(1) <= DC_i;
|
STATUS_d(1) <= DC_i;
|
STATUS_d(0) <= A(0) when Do_RRF = '1' else
|
STATUS_d(0) <= A(0) when Do_RRF = '1' else
|
A(7) when Do_RLF = '1' else
|
A(7) when Do_RLF = '1' else
|
AddSubRes(8);
|
AddSubRes(8);
|
|
|
-- Z
|
-- Z
|
STATUS_Wr(2) <= '1' when Do_SUB = '1' or Do_ADD = '1' or
|
STATUS_Wr(2) <= '1' when Do_SUB = '1' or Do_ADD = '1' or
|
((Do_DEC = '1' or Do_INC = '1') and Do_IDTEST = '0') or
|
((Do_DEC = '1' or Do_INC = '1') and Do_IDTEST = '0') or
|
Do_AND = '1' or Do_OR = '1' or Do_XOR = '1' or
|
Do_AND = '1' or Do_OR = '1' or Do_XOR = '1' or
|
Do_CLR = '1' or Do_COM = '1' else '0';
|
Do_CLR = '1' or Do_COM = '1' else '0';
|
-- DC
|
-- DC
|
STATUS_Wr(1) <= '1' when Do_SUB = '1' or Do_ADD = '1' else '0';
|
STATUS_Wr(1) <= '1' when Do_SUB = '1' or Do_ADD = '1' else '0';
|
-- C
|
-- C
|
STATUS_Wr(0) <= '1' when Do_SUB = '1' or Do_ADD = '1' or Do_RRF = '1' or Do_RLF = '1' else '0';
|
STATUS_Wr(0) <= '1' when Do_SUB = '1' or Do_ADD = '1' or Do_RRF = '1' or Do_RLF = '1' else '0';
|
|
|
end;
|
end;
|
|
|
