OpenCores
URL https://opencores.org/ocsvn/present/present/trunk

Subversion Repositories present

[/] [present/] [trunk/] [DecodeTesting/] [rtl/] [vhdl/] [Reg.vhd] - Diff between revs 3 and 4

Only display areas with differences | Details | Blame | View Log

Rev 3 Rev 4
 
-----------------------------------------------------------------------
 
----                                                               ----
 
---- Present - a lightweight block cipher project                  ----
 
----                                                               ----
 
---- This file is part of the Present - a lightweight block        ----
 
---- cipher project                                                ----
 
---- http://www.http://opencores.org/project,present               ----
 
----                                                               ----
 
---- Description:                                                  ----
 
----     Register - nothing special.                                ----
 
---- To Do:                                                        ----
 
----                                                               ----
 
---- Author(s):                                                    ----
 
---- - Krzysztof Gajewski, gajos@opencores.org                     ----
 
----                       k.gajewski@gmail.com                    ----
 
----                                                               ----
 
-----------------------------------------------------------------------
 
----                                                               ----
 
---- Copyright (C) 2013 Authors and OPENCORES.ORG                  ----
 
----                                                               ----
 
---- This source file may be used and distributed without          ----
 
---- restriction provided that this copyright statement is not     ----
 
---- removed from the file and that any derivative work contains   ----
 
---- the original copyright notice and the associated disclaimer.  ----
 
----                                                               ----
 
---- This source file is free software; you can redistribute it    ----
 
---- and-or modify it under the terms of the GNU Lesser General    ----
 
---- Public License as published by the Free Software Foundation;  ----
 
---- either version 2.1 of the License, or (at your option) any    ----
 
---- later version.                                                ----
 
----                                                               ----
 
---- This source is distributed in the hope that it will be        ----
 
---- useful, but WITHOUT ANY WARRANTY; without even the implied    ----
 
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR       ----
 
---- PURPOSE. See the GNU Lesser General Public License for more   ----
 
---- details.                                                      ----
 
----                                                               ----
 
---- You should have received a copy of the GNU Lesser General     ----
 
---- Public License along with this source; if not, download it    ----
 
---- from http://www.opencores.org/lgpl.shtml                      ----
 
----                                                               ----
 
-----------------------------------------------------------------------
 
library IEEE;
 
use IEEE.STD_LOGIC_1164.ALL;
 
 
 
-- Uncomment the following library declaration if using
 
-- arithmetic functions with Signed or Unsigned values
 
--use IEEE.NUMERIC_STD.ALL;
 
 
 
-- Uncomment the following library declaration if instantiating
 
-- any Xilinx primitives in this code.
 
--library UNISIM;
 
--use UNISIM.VComponents.all;
 
 
 
entity Reg is
 
        generic(width : integer := 64);
 
        port(
 
                input  : in  STD_LOGIC_VECTOR(width - 1 downto 0);
 
                output : out STD_LOGIC_VECTOR(width - 1 downto 0);
 
                enable : in  STD_LOGIC;
 
                clk    : in  STD_LOGIC;
 
                reset  : in  STD_LOGIC
 
        );
 
end Reg;
 
 
 
architecture Behavioral of Reg is
 
 
 
signal reg : STD_LOGIC_VECTOR(width - 1 downto 0);
 
 
 
begin
 
        clock : process(clk, reset)
 
                begin
 
                        if (reset = '1') then
 
                                reg <= (others => '0');
 
                        elsif (clk = '1' and clk'Event) then
 
                                if (enable = '1') then
 
                                        reg <= input;
 
                                end if;
 
                        end if;
 
                end process clock;
 
        output <= reg;
 
end Behavioral;
 
 
 
 
 No newline at end of file
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.