-- $Id: input.vhdl,v 1.1.1.1 2005-11-15 01:51:28 arif_endro Exp $
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-- $Id: input.vhdl,v 1.1.1.1 2005-11-15 01:51:28 arif_endro Exp $
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Title : Input Data
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-- Title : Input Data
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-- Project :
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-- Project :
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : input.vhdl
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-- File : input.vhdl
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-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
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-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
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-- Created : 2005/11/01
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-- Created : 2005/11/01
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-- Last update :
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-- Last update :
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-- Simulators :
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-- Simulators :
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-- Synthesizers:
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-- Synthesizers:
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-- Target :
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-- Target :
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Description : わかりません
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-- Description : わかりません
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Copyright (C) 2005 Arif E. Nugroho
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-- Copyright (C) 2005 Arif E. Nugroho
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-- This VHDL design file is an open design; you can redistribute it and/or
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-- This VHDL design file is an open design; you can redistribute it and/or
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-- modify it and/or implement it after contacting the author
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-- modify it and/or implement it after contacting the author
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
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-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
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-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
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-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
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-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
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-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
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-- ASSOCIATED DISCLAIMER.
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-- ASSOCIATED DISCLAIMER.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
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-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
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-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use std.textio.all;
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use std.textio.all;
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entity input is
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entity input is
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port (
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port (
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clock : out bit;
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clock : out bit;
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start : out bit;
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start : out bit;
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rxin : out bit_vector (07 downto 00)
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rxin : out bit_vector (07 downto 00)
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);
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);
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end input;
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end input;
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architecture test_bench of input is
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architecture test_bench of input is
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type char_to_stdlogic_t is array (character) of std_logic;
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type char_to_stdlogic_t is array (character) of std_logic;
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constant to_std_logic : char_to_stdlogic_t := (
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constant to_std_logic : char_to_stdlogic_t := (
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'U' => 'U',
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'U' => 'U',
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'X' => 'X',
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'X' => 'X',
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'0' => '0',
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'0' => '0',
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'1' => '1',
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'1' => '1',
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'Z' => 'Z',
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'Z' => 'Z',
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'W' => 'L',
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'W' => 'L',
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'H' => 'H',
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'H' => 'H',
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'-' => '-',
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'-' => '-',
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others => 'X'
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others => 'X'
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);
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);
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file start_ptr : text open read_mode is "../data/start.txt";
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file start_ptr : text open read_mode is "../data/start.txt";
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file rxin_ptr : text open read_mode is "../data/rxin100DB.txt";
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file rxin_ptr : text open read_mode is "../data/rxin100DB.txt";
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begin
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begin
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process
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process
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variable start_ln : line;
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variable start_ln : line;
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variable rxin_ln : line;
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variable rxin_ln : line;
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variable delay : time := 1 ns;
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variable delay : time := 1 ns;
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variable start_str : string (01 to 01) := " ";
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variable start_str : string (01 to 01) := " ";
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variable rxin_str : string (01 to 08) := " ";
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variable rxin_str : string (01 to 08) := " ";
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variable rxin_len : integer;
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variable rxin_len : integer;
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variable start_var : std_logic;
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variable start_var : std_logic;
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variable rxin_var : std_logic_vector (07 downto 00);
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variable rxin_var : std_logic_vector (07 downto 00);
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begin
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begin
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while not (endfile(start_ptr) and endfile(rxin_ptr)) loop
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while not (endfile(start_ptr) and endfile(rxin_ptr)) loop
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readline(start_ptr, start_ln);
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readline(start_ptr, start_ln);
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if (not(endfile(rxin_ptr))) then
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if (not(endfile(rxin_ptr))) then
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readline(rxin_ptr, rxin_ln);
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readline(rxin_ptr, rxin_ln);
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else
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else
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write(rxin_ln, string'("00000000"));
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write(rxin_ln, string'("00000000"));
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end if;
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end if;
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if (start_ln /= NULL) and (start_ln'length > 0) and (rxin_ln /= NULL) and (rxin_ln'length > 0) then
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if (start_ln /= NULL) and (start_ln'length > 0) and (rxin_ln /= NULL) and (rxin_ln'length > 0) then
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read(start_ln, start_str);
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read(start_ln, start_str);
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read(rxin_ln, rxin_str);
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read(rxin_ln, rxin_str);
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rxin_len := rxin_str'length - 1;
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rxin_len := rxin_str'length - 1;
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start_var := to_std_logic (start_str(01));
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start_var := to_std_logic (start_str(01));
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for b in rxin_str'range loop
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for b in rxin_str'range loop
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rxin_var(rxin_len) := to_std_logic (rxin_str(b));
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rxin_var(rxin_len) := to_std_logic (rxin_str(b));
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rxin_len := rxin_len - 1;
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rxin_len := rxin_len - 1;
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end loop;
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end loop;
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start <= to_bit (start_var);
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start <= to_bit (start_var);
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rxin <= to_bitvector (rxin_var);
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rxin <= to_bitvector (rxin_var);
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clock <= '1';
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clock <= '1';
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wait for delay;
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wait for delay;
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clock <= '0';
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clock <= '0';
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wait for delay;
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wait for delay;
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end if;
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end if;
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end loop;
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end loop;
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wait;
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wait;
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end process;
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end process;
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end test_bench;
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end test_bench;
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