-- $Id: modelsim_bench.vhdl,v 1.1.1.1 2005-11-15 01:51:28 arif_endro Exp $
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-- $Id: modelsim_bench.vhdl,v 1.1.1.1 2005-11-15 01:51:28 arif_endro Exp $
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Title : Test bench top modules.
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-- Title : Test bench top modules.
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-- Project :
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-- Project :
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : modelsim_bench.vhdl
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-- File : modelsim_bench.vhdl
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-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
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-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
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-- Created : 2005/11/01
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-- Created : 2005/11/01
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-- Last update :
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-- Last update :
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-- Simulators :
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-- Simulators :
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-- Synthesizers:
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-- Synthesizers:
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-- Target :
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-- Target :
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Description : Top modules for test bench.
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-- Description : Top modules for test bench.
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Copyright (C) 2005 Arif E. Nugroho
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-- Copyright (C) 2005 Arif E. Nugroho
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-- This VHDL design file is an open design; you can redistribute it and/or
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-- This VHDL design file is an open design; you can redistribute it and/or
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-- modify it and/or implement it after contacting the author
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-- modify it and/or implement it after contacting the author
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
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-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
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-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
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-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
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-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
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-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
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-- ASSOCIATED DISCLAIMER.
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-- ASSOCIATED DISCLAIMER.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
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-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
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-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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entity modelsim_bench is
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entity modelsim_bench is
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port (
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port (
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y0d : out bit;
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y0d : out bit;
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y1d : out bit;
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y1d : out bit;
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y2d : out bit;
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y2d : out bit;
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y3d : out bit
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y3d : out bit
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);
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);
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end modelsim_bench;
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end modelsim_bench;
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architecture structural of modelsim_bench is
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architecture structural of modelsim_bench is
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component product_code
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component product_code
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port (
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port (
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clock : in bit;
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clock : in bit;
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start : in bit;
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start : in bit;
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rxin : in bit_vector (07 downto 00);
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rxin : in bit_vector (07 downto 00);
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y0d : out bit;
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y0d : out bit;
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y1d : out bit;
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y1d : out bit;
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y2d : out bit;
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y2d : out bit;
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y3d : out bit
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y3d : out bit
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);
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);
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end component;
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end component;
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component input
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component input
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port (
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port (
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clock : out bit;
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clock : out bit;
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start : out bit;
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start : out bit;
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rxin : out bit_vector (07 downto 00)
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rxin : out bit_vector (07 downto 00)
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);
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);
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end component;
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end component;
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component output
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component output
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port (
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port (
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start : in bit;
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start : in bit;
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y0 : in bit;
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y0 : in bit;
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y1 : in bit;
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y1 : in bit;
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y2 : in bit;
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y2 : in bit;
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y3 : in bit
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y3 : in bit
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);
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);
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end component;
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end component;
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signal clock : bit;
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signal clock : bit;
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signal start : bit;
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signal start : bit;
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signal y0 : bit;
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signal y0 : bit;
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signal y1 : bit;
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signal y1 : bit;
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signal y2 : bit;
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signal y2 : bit;
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signal y3 : bit;
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signal y3 : bit;
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signal rxin : bit_vector (07 downto 00);
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signal rxin : bit_vector (07 downto 00);
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begin
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begin
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y0d <= y0;
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y0d <= y0;
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y1d <= y1;
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y1d <= y1;
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y2d <= y2;
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y2d <= y2;
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y3d <= y3;
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y3d <= y3;
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my_product_code : product_code
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my_product_code : product_code
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port map (
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port map (
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clock => clock,
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clock => clock,
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start => start,
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start => start,
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rxin => rxin,
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rxin => rxin,
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y0d => y0,
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y0d => y0,
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y1d => y1,
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y1d => y1,
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y2d => y2,
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y2d => y2,
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y3d => y3
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y3d => y3
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);
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);
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my_input : input
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my_input : input
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port map (
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port map (
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clock => clock,
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clock => clock,
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start => start,
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start => start,
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rxin => rxin
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rxin => rxin
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);
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);
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my_output : output
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my_output : output
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port map (
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port map (
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start => start,
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start => start,
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y0 => y0,
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y0 => y0,
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y1 => y1,
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y1 => y1,
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y2 => y2,
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y2 => y2,
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y3 => y3
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y3 => y3
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);
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);
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end structural;
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end structural;
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