-- $Id: comparator_7bit.vhdl,v 1.1.1.1 2005-11-15 01:52:30 arif_endro Exp $
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-- $Id: comparator_7bit.vhdl,v 1.1.1.1 2005-11-15 01:52:30 arif_endro Exp $
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Title : 7 bit comparator
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-- Title : 7 bit comparator
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-- Project :
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-- Project :
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : comparator_7bit.vhdl
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-- File : comparator_7bit.vhdl
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-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
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-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
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-- Created : 2005/11/01
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-- Created : 2005/11/01
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-- Last update :
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-- Last update :
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-- Simulators :
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-- Simulators :
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-- Synthesizers:
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-- Synthesizers:
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-- Target :
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-- Target :
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Description : Compare two input ( 7 bit signal )
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-- Description : Compare two input ( 7 bit signal )
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Copyright (C) 2005 Arif E. Nugroho
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-- Copyright (C) 2005 Arif E. Nugroho
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-- This VHDL design file is an open design; you can redistribute it and/or
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-- This VHDL design file is an open design; you can redistribute it and/or
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-- modify it and/or implement it after contacting the author
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-- modify it and/or implement it after contacting the author
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
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-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
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-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
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-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
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-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
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-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
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-- ASSOCIATED DISCLAIMER.
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-- ASSOCIATED DISCLAIMER.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
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-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
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-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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entity comparator_7bit is
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entity comparator_7bit is
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port (
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port (
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a_7bit_i : in bit_vector (06 downto 00);
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a_7bit_i : in bit_vector (06 downto 00);
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b_7bit_i : in bit_vector (06 downto 00);
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b_7bit_i : in bit_vector (06 downto 00);
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a_eq_b : out bit;
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a_eq_b : out bit;
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a_gt_b : out bit;
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a_gt_b : out bit;
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a_lt_b : out bit
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a_lt_b : out bit
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);
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);
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end comparator_7bit;
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end comparator_7bit;
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architecture structural of comparator_7bit is
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architecture structural of comparator_7bit is
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component bit_comparator
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component bit_comparator
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port (
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port (
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a_i : in bit;
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a_i : in bit;
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b_i : in bit;
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b_i : in bit;
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eq_i : in bit;
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eq_i : in bit;
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gt_i : in bit;
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gt_i : in bit;
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lt_i : in bit;
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lt_i : in bit;
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eq_o : out bit;
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eq_o : out bit;
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gt_o : out bit;
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gt_o : out bit;
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lt_o : out bit
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lt_o : out bit
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);
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);
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end component;
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end component;
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signal eq_i_0 : bit;
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signal eq_i_0 : bit;
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signal gt_i_0 : bit;
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signal gt_i_0 : bit;
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signal lt_i_0 : bit;
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signal lt_i_0 : bit;
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signal eq_o_0 : bit;
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signal eq_o_0 : bit;
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signal gt_o_0 : bit;
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signal gt_o_0 : bit;
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signal lt_o_0 : bit;
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signal lt_o_0 : bit;
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signal eq_o_1 : bit;
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signal eq_o_1 : bit;
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signal gt_o_1 : bit;
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signal gt_o_1 : bit;
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signal lt_o_1 : bit;
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signal lt_o_1 : bit;
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signal eq_o_2 : bit;
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signal eq_o_2 : bit;
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signal gt_o_2 : bit;
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signal gt_o_2 : bit;
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signal lt_o_2 : bit;
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signal lt_o_2 : bit;
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signal eq_o_3 : bit;
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signal eq_o_3 : bit;
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signal gt_o_3 : bit;
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signal gt_o_3 : bit;
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signal lt_o_3 : bit;
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signal lt_o_3 : bit;
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signal eq_o_4 : bit;
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signal eq_o_4 : bit;
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signal gt_o_4 : bit;
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signal gt_o_4 : bit;
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signal lt_o_4 : bit;
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signal lt_o_4 : bit;
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signal eq_o_5 : bit;
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signal eq_o_5 : bit;
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signal gt_o_5 : bit;
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signal gt_o_5 : bit;
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signal lt_o_5 : bit;
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signal lt_o_5 : bit;
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signal eq_o_6 : bit;
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signal eq_o_6 : bit;
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signal gt_o_6 : bit;
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signal gt_o_6 : bit;
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signal lt_o_6 : bit;
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signal lt_o_6 : bit;
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begin
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begin
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eq_i_0 <= '1'; -- 20051015 Fixed
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eq_i_0 <= '1'; -- 20051015 Fixed
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gt_i_0 <= '0';
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gt_i_0 <= '0';
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lt_i_0 <= '0';
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lt_i_0 <= '0';
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a_eq_b <= eq_o_6;
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a_eq_b <= eq_o_6;
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a_gt_b <= gt_o_6;
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a_gt_b <= gt_o_6;
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a_lt_b <= lt_o_6;
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a_lt_b <= lt_o_6;
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cmp6 : bit_comparator
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cmp6 : bit_comparator
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port map (
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port map (
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a_i => a_7bit_i (06),
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a_i => a_7bit_i (06),
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b_i => b_7bit_i (06),
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b_i => b_7bit_i (06),
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eq_i => eq_o_5,
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eq_i => eq_o_5,
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gt_i => gt_o_5,
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gt_i => gt_o_5,
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lt_i => lt_o_5,
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lt_i => lt_o_5,
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eq_o => eq_o_6,
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eq_o => eq_o_6,
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gt_o => gt_o_6,
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gt_o => gt_o_6,
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lt_o => lt_o_6
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lt_o => lt_o_6
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);
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);
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cmp5 : bit_comparator
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cmp5 : bit_comparator
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port map (
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port map (
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a_i => a_7bit_i (05),
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a_i => a_7bit_i (05),
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b_i => b_7bit_i (05),
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b_i => b_7bit_i (05),
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eq_i => eq_o_4,
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eq_i => eq_o_4,
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gt_i => gt_o_4,
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gt_i => gt_o_4,
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lt_i => lt_o_4,
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lt_i => lt_o_4,
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eq_o => eq_o_5,
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eq_o => eq_o_5,
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gt_o => gt_o_5,
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gt_o => gt_o_5,
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lt_o => lt_o_5
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lt_o => lt_o_5
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);
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);
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cmp4 : bit_comparator
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cmp4 : bit_comparator
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port map (
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port map (
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a_i => a_7bit_i (04),
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a_i => a_7bit_i (04),
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b_i => b_7bit_i (04),
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b_i => b_7bit_i (04),
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eq_i => eq_o_3,
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eq_i => eq_o_3,
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gt_i => gt_o_3,
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gt_i => gt_o_3,
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lt_i => lt_o_3,
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lt_i => lt_o_3,
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eq_o => eq_o_4,
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eq_o => eq_o_4,
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gt_o => gt_o_4,
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gt_o => gt_o_4,
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lt_o => lt_o_4
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lt_o => lt_o_4
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);
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);
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cmp3 : bit_comparator
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cmp3 : bit_comparator
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port map (
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port map (
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a_i => a_7bit_i (03),
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a_i => a_7bit_i (03),
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b_i => b_7bit_i (03),
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b_i => b_7bit_i (03),
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eq_i => eq_o_2,
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eq_i => eq_o_2,
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gt_i => gt_o_2,
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gt_i => gt_o_2,
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lt_i => lt_o_2,
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lt_i => lt_o_2,
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eq_o => eq_o_3,
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eq_o => eq_o_3,
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gt_o => gt_o_3,
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gt_o => gt_o_3,
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lt_o => lt_o_3
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lt_o => lt_o_3
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);
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);
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cmp2 : bit_comparator
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cmp2 : bit_comparator
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port map (
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port map (
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a_i => a_7bit_i (02),
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a_i => a_7bit_i (02),
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b_i => b_7bit_i (02),
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b_i => b_7bit_i (02),
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eq_i => eq_o_1,
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eq_i => eq_o_1,
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gt_i => gt_o_1,
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gt_i => gt_o_1,
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lt_i => lt_o_1,
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lt_i => lt_o_1,
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eq_o => eq_o_2,
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eq_o => eq_o_2,
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gt_o => gt_o_2,
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gt_o => gt_o_2,
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lt_o => lt_o_2
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lt_o => lt_o_2
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);
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);
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cmp1 : bit_comparator
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cmp1 : bit_comparator
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port map (
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port map (
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a_i => a_7bit_i (01),
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a_i => a_7bit_i (01),
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b_i => b_7bit_i (01),
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b_i => b_7bit_i (01),
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eq_i => eq_o_0,
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eq_i => eq_o_0,
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gt_i => gt_o_0,
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gt_i => gt_o_0,
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lt_i => lt_o_0,
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lt_i => lt_o_0,
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eq_o => eq_o_1,
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eq_o => eq_o_1,
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gt_o => gt_o_1,
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gt_o => gt_o_1,
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lt_o => lt_o_1
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lt_o => lt_o_1
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);
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);
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cmp0 : bit_comparator
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cmp0 : bit_comparator
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port map (
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port map (
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a_i => a_7bit_i (00),
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a_i => a_7bit_i (00),
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b_i => b_7bit_i (00),
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b_i => b_7bit_i (00),
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eq_i => eq_i_0,
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eq_i => eq_i_0,
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gt_i => gt_i_0,
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gt_i => gt_i_0,
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lt_i => lt_i_0,
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lt_i => lt_i_0,
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eq_o => eq_o_0,
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eq_o => eq_o_0,
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gt_o => gt_o_0,
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gt_o => gt_o_0,
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lt_o => lt_o_0
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lt_o => lt_o_0
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);
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);
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end structural;
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end structural;
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