-- $Id: product_code.vhdl,v 1.1.1.1 2005-11-15 01:52:31 arif_endro Exp $
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-- $Id: product_code.vhdl,v 1.1.1.1 2005-11-15 01:52:31 arif_endro Exp $
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Title : Product Code Iterative Decoder
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-- Title : Product Code Iterative Decoder
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-- Project :
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-- Project :
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : product_code.vhdl
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-- File : product_code.vhdl
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-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
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-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
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-- Created : 2005/11/01
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-- Created : 2005/11/01
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-- Last update :
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-- Last update :
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-- Simulators :
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-- Simulators :
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-- Synthesizers:
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-- Synthesizers:
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-- Target :
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-- Target :
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Description : Connector of all component in Product Code Iterative Decoder.
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-- Description : Connector of all component in Product Code Iterative Decoder.
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Copyright (C) 2005 Arif E. Nugroho
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-- Copyright (C) 2005 Arif E. Nugroho
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-- This VHDL design file is an open design; you can redistribute it and/or
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-- This VHDL design file is an open design; you can redistribute it and/or
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-- modify it and/or implement it after contacting the author
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-- modify it and/or implement it after contacting the author
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
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-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
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-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
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-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
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-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
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-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
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-- ASSOCIATED DISCLAIMER.
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-- ASSOCIATED DISCLAIMER.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
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-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
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-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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|
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entity product_code is
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entity product_code is
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port (
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port (
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clock : in bit;
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clock : in bit;
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start : in bit;
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start : in bit;
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rxin : in bit_vector (07 downto 00);
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rxin : in bit_vector (07 downto 00);
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y0d : out bit;
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y0d : out bit;
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y1d : out bit;
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y1d : out bit;
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y2d : out bit;
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y2d : out bit;
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y3d : out bit
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y3d : out bit
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);
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);
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end product_code;
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end product_code;
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architecture structural of product_code is
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architecture structural of product_code is
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|
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component ser2par8bit
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component ser2par8bit
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port (
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port (
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clock : in bit;
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clock : in bit;
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clear : in bit;
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clear : in bit;
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start : in bit;
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start : in bit;
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rxin : in bit_vector (07 downto 00);
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rxin : in bit_vector (07 downto 00);
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y0 : out bit_vector (07 downto 00);
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y0 : out bit_vector (07 downto 00);
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y1 : out bit_vector (07 downto 00);
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y1 : out bit_vector (07 downto 00);
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y2 : out bit_vector (07 downto 00);
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y2 : out bit_vector (07 downto 00);
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y3 : out bit_vector (07 downto 00);
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y3 : out bit_vector (07 downto 00);
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r0 : out bit_vector (07 downto 00);
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r0 : out bit_vector (07 downto 00);
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r1 : out bit_vector (07 downto 00);
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r1 : out bit_vector (07 downto 00);
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c0 : out bit_vector (07 downto 00);
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c0 : out bit_vector (07 downto 00);
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c1 : out bit_vector (07 downto 00)
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c1 : out bit_vector (07 downto 00)
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);
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);
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end component;
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end component;
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component ext_val
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component ext_val
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port (
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port (
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ext_a_i : in bit_vector (07 downto 00);
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ext_a_i : in bit_vector (07 downto 00);
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ext_b_i : in bit_vector (07 downto 00);
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ext_b_i : in bit_vector (07 downto 00);
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ext_r_o : out bit_vector (07 downto 00)
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ext_r_o : out bit_vector (07 downto 00)
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);
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);
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end component;
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end component;
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component adder_08bit
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component adder_08bit
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port (
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port (
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addend_08bit : in bit_vector (07 downto 00);
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addend_08bit : in bit_vector (07 downto 00);
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augend_08bit : in bit_vector (07 downto 00);
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augend_08bit : in bit_vector (07 downto 00);
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adder08_output : out bit_vector (08 downto 00)
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adder08_output : out bit_vector (08 downto 00)
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);
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);
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end component;
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end component;
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signal y0e : bit_vector (07 downto 00);
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signal y0e : bit_vector (07 downto 00);
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signal y1e : bit_vector (07 downto 00);
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signal y1e : bit_vector (07 downto 00);
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signal y2e : bit_vector (07 downto 00);
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signal y2e : bit_vector (07 downto 00);
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signal y3e : bit_vector (07 downto 00);
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signal y3e : bit_vector (07 downto 00);
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|
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signal y0 : bit_vector (07 downto 00);
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signal y0 : bit_vector (07 downto 00);
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signal y1 : bit_vector (07 downto 00);
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signal y1 : bit_vector (07 downto 00);
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signal y2 : bit_vector (07 downto 00);
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signal y2 : bit_vector (07 downto 00);
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signal y3 : bit_vector (07 downto 00);
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signal y3 : bit_vector (07 downto 00);
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signal r0 : bit_vector (07 downto 00);
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signal r0 : bit_vector (07 downto 00);
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signal r1 : bit_vector (07 downto 00);
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signal r1 : bit_vector (07 downto 00);
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signal c0 : bit_vector (07 downto 00);
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signal c0 : bit_vector (07 downto 00);
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signal c1 : bit_vector (07 downto 00);
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signal c1 : bit_vector (07 downto 00);
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signal ext_b_c_0_b : bit_vector (08 downto 00);
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signal ext_b_c_0_b : bit_vector (08 downto 00);
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signal ext_b_c_1_b : bit_vector (08 downto 00);
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signal ext_b_c_1_b : bit_vector (08 downto 00);
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signal ext_b_c_2_b : bit_vector (08 downto 00);
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signal ext_b_c_2_b : bit_vector (08 downto 00);
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signal ext_b_c_3_b : bit_vector (08 downto 00);
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signal ext_b_c_3_b : bit_vector (08 downto 00);
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signal augend_sum_c_0 : bit_vector (07 downto 00);
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signal augend_sum_c_0 : bit_vector (07 downto 00);
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signal augend_sum_c_1 : bit_vector (07 downto 00);
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signal augend_sum_c_1 : bit_vector (07 downto 00);
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signal augend_sum_c_2 : bit_vector (07 downto 00);
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signal augend_sum_c_2 : bit_vector (07 downto 00);
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signal augend_sum_c_3 : bit_vector (07 downto 00);
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signal augend_sum_c_3 : bit_vector (07 downto 00);
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signal ext_r_r_0 : bit_vector (07 downto 00);
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signal ext_r_r_0 : bit_vector (07 downto 00);
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signal ext_r_r_1 : bit_vector (07 downto 00);
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signal ext_r_r_1 : bit_vector (07 downto 00);
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signal ext_r_r_2 : bit_vector (07 downto 00);
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signal ext_r_r_2 : bit_vector (07 downto 00);
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signal ext_r_r_3 : bit_vector (07 downto 00);
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signal ext_r_r_3 : bit_vector (07 downto 00);
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signal ext_b_r_0_b : bit_vector (08 downto 00);
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signal ext_b_r_0_b : bit_vector (08 downto 00);
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signal ext_b_r_1_b : bit_vector (08 downto 00);
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signal ext_b_r_1_b : bit_vector (08 downto 00);
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signal ext_b_r_2_b : bit_vector (08 downto 00);
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signal ext_b_r_2_b : bit_vector (08 downto 00);
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signal ext_b_r_3_b : bit_vector (08 downto 00);
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signal ext_b_r_3_b : bit_vector (08 downto 00);
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signal ext_b_r_0 : bit_vector (07 downto 00);
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signal ext_b_r_0 : bit_vector (07 downto 00);
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signal ext_b_r_1 : bit_vector (07 downto 00);
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signal ext_b_r_1 : bit_vector (07 downto 00);
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signal ext_b_r_2 : bit_vector (07 downto 00);
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signal ext_b_r_2 : bit_vector (07 downto 00);
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signal ext_b_r_3 : bit_vector (07 downto 00);
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signal ext_b_r_3 : bit_vector (07 downto 00);
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signal ext_r_c_0 : bit_vector (07 downto 00);
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signal ext_r_c_0 : bit_vector (07 downto 00);
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signal ext_r_c_1 : bit_vector (07 downto 00);
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signal ext_r_c_1 : bit_vector (07 downto 00);
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signal ext_r_c_2 : bit_vector (07 downto 00);
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signal ext_r_c_2 : bit_vector (07 downto 00);
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signal ext_r_c_3 : bit_vector (07 downto 00);
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signal ext_r_c_3 : bit_vector (07 downto 00);
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signal ext_b_c_0 : bit_vector (07 downto 00);
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signal ext_b_c_0 : bit_vector (07 downto 00);
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signal ext_b_c_1 : bit_vector (07 downto 00);
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signal ext_b_c_1 : bit_vector (07 downto 00);
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signal ext_b_c_2 : bit_vector (07 downto 00);
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signal ext_b_c_2 : bit_vector (07 downto 00);
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signal ext_b_c_3 : bit_vector (07 downto 00);
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signal ext_b_c_3 : bit_vector (07 downto 00);
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signal y0p_b : bit_vector (08 downto 00);
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signal y0p_b : bit_vector (08 downto 00);
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signal y1p_b : bit_vector (08 downto 00);
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signal y1p_b : bit_vector (08 downto 00);
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signal y2p_b : bit_vector (08 downto 00);
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signal y2p_b : bit_vector (08 downto 00);
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signal y3p_b : bit_vector (08 downto 00);
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signal y3p_b : bit_vector (08 downto 00);
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signal y0p : bit;
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signal y0p : bit;
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signal y1p : bit;
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signal y1p : bit;
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signal y2p : bit;
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signal y2p : bit;
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signal y3p : bit;
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signal y3p : bit;
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constant gnd : bit := '0';
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constant gnd : bit := '0';
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begin
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begin
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ext_b_c_0 (07 downto 00) <= ext_b_c_0_b (07 downto 00);
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ext_b_c_0 (07 downto 00) <= ext_b_c_0_b (07 downto 00);
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ext_b_c_1 (07 downto 00) <= ext_b_c_1_b (07 downto 00);
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ext_b_c_1 (07 downto 00) <= ext_b_c_1_b (07 downto 00);
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ext_b_c_2 (07 downto 00) <= ext_b_c_2_b (07 downto 00);
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ext_b_c_2 (07 downto 00) <= ext_b_c_2_b (07 downto 00);
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ext_b_c_3 (07 downto 00) <= ext_b_c_3_b (07 downto 00);
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ext_b_c_3 (07 downto 00) <= ext_b_c_3_b (07 downto 00);
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|
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ext_b_r_0 (07 downto 00) <= ext_b_r_0_b (07 downto 00);
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ext_b_r_0 (07 downto 00) <= ext_b_r_0_b (07 downto 00);
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ext_b_r_1 (07 downto 00) <= ext_b_r_1_b (07 downto 00);
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ext_b_r_1 (07 downto 00) <= ext_b_r_1_b (07 downto 00);
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ext_b_r_2 (07 downto 00) <= ext_b_r_2_b (07 downto 00);
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ext_b_r_2 (07 downto 00) <= ext_b_r_2_b (07 downto 00);
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ext_b_r_3 (07 downto 00) <= ext_b_r_3_b (07 downto 00);
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ext_b_r_3 (07 downto 00) <= ext_b_r_3_b (07 downto 00);
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|
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first : ser2par8bit
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first : ser2par8bit
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port map (
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port map (
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clock => clock,
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clock => clock,
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clear => gnd,
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clear => gnd,
|
start => start,
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start => start,
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rxin => rxin,
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rxin => rxin,
|
y0 => y0,
|
y0 => y0,
|
y1 => y1,
|
y1 => y1,
|
y2 => y2,
|
y2 => y2,
|
y3 => y3,
|
y3 => y3,
|
r0 => r0,
|
r0 => r0,
|
r1 => r1,
|
r1 => r1,
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c0 => c0,
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c0 => c0,
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c1 => c1
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c1 => c1
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);
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);
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|
|
sum_r_0 : adder_08bit
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sum_r_0 : adder_08bit
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port map (
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port map (
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addend_08bit => y0,
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addend_08bit => y0,
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augend_08bit => y0e,
|
augend_08bit => y0e,
|
adder08_output => ext_b_r_1_b
|
adder08_output => ext_b_r_1_b
|
);
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);
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|
|
sum_r_1 : adder_08bit
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sum_r_1 : adder_08bit
|
port map (
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port map (
|
addend_08bit => y1,
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addend_08bit => y1,
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augend_08bit => y1e,
|
augend_08bit => y1e,
|
adder08_output => ext_b_r_0_b
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adder08_output => ext_b_r_0_b
|
);
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);
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|
|
sum_r_2 : adder_08bit
|
sum_r_2 : adder_08bit
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port map (
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port map (
|
addend_08bit => y2,
|
addend_08bit => y2,
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augend_08bit => y2e,
|
augend_08bit => y2e,
|
adder08_output => ext_b_r_3_b
|
adder08_output => ext_b_r_3_b
|
);
|
);
|
|
|
sum_r_3 : adder_08bit
|
sum_r_3 : adder_08bit
|
port map (
|
port map (
|
addend_08bit => y3,
|
addend_08bit => y3,
|
augend_08bit => y3e,
|
augend_08bit => y3e,
|
adder08_output => ext_b_r_2_b
|
adder08_output => ext_b_r_2_b
|
);
|
);
|
|
|
sum_c_0 : adder_08bit
|
sum_c_0 : adder_08bit
|
port map (
|
port map (
|
addend_08bit => y0,
|
addend_08bit => y0,
|
augend_08bit => augend_sum_c_0,
|
augend_08bit => augend_sum_c_0,
|
adder08_output => ext_b_c_2_b
|
adder08_output => ext_b_c_2_b
|
);
|
);
|
|
|
sum_c_1 : adder_08bit
|
sum_c_1 : adder_08bit
|
port map (
|
port map (
|
addend_08bit => y1,
|
addend_08bit => y1,
|
augend_08bit => augend_sum_c_1,
|
augend_08bit => augend_sum_c_1,
|
adder08_output => ext_b_c_3_b
|
adder08_output => ext_b_c_3_b
|
);
|
);
|
|
|
sum_c_2 : adder_08bit
|
sum_c_2 : adder_08bit
|
port map (
|
port map (
|
addend_08bit => y2,
|
addend_08bit => y2,
|
augend_08bit => augend_sum_c_2,
|
augend_08bit => augend_sum_c_2,
|
adder08_output => ext_b_c_0_b
|
adder08_output => ext_b_c_0_b
|
);
|
);
|
|
|
sum_c_3 : adder_08bit
|
sum_c_3 : adder_08bit
|
port map (
|
port map (
|
addend_08bit => y3,
|
addend_08bit => y3,
|
augend_08bit => augend_sum_c_3,
|
augend_08bit => augend_sum_c_3,
|
adder08_output => ext_b_c_1_b
|
adder08_output => ext_b_c_1_b
|
);
|
);
|
|
|
sum_p_0 : adder_08bit
|
sum_p_0 : adder_08bit
|
port map (
|
port map (
|
addend_08bit => ext_b_r_1,
|
addend_08bit => ext_b_r_1,
|
augend_08bit => ext_r_r_0,
|
augend_08bit => ext_r_r_0,
|
adder08_output => y0p_b
|
adder08_output => y0p_b
|
);
|
);
|
|
|
sum_p_1 : adder_08bit
|
sum_p_1 : adder_08bit
|
port map (
|
port map (
|
addend_08bit => ext_b_r_0,
|
addend_08bit => ext_b_r_0,
|
augend_08bit => ext_r_r_1,
|
augend_08bit => ext_r_r_1,
|
adder08_output => y1p_b
|
adder08_output => y1p_b
|
);
|
);
|
|
|
sum_p_2 : adder_08bit
|
sum_p_2 : adder_08bit
|
port map (
|
port map (
|
addend_08bit => ext_b_r_3,
|
addend_08bit => ext_b_r_3,
|
augend_08bit => ext_r_r_2,
|
augend_08bit => ext_r_r_2,
|
adder08_output => y2p_b
|
adder08_output => y2p_b
|
);
|
);
|
|
|
sum_p_3 : adder_08bit
|
sum_p_3 : adder_08bit
|
port map (
|
port map (
|
addend_08bit => ext_b_r_2,
|
addend_08bit => ext_b_r_2,
|
augend_08bit => ext_r_r_3,
|
augend_08bit => ext_r_r_3,
|
adder08_output => y3p_b
|
adder08_output => y3p_b
|
);
|
);
|
|
|
row0 : ext_val
|
row0 : ext_val
|
port map (
|
port map (
|
ext_a_i => r0,
|
ext_a_i => r0,
|
ext_b_i => ext_b_r_0,
|
ext_b_i => ext_b_r_0,
|
ext_r_o => ext_r_r_0
|
ext_r_o => ext_r_r_0
|
);
|
);
|
|
|
row1 : ext_val
|
row1 : ext_val
|
port map (
|
port map (
|
ext_a_i => r0,
|
ext_a_i => r0,
|
ext_b_i => ext_b_r_1,
|
ext_b_i => ext_b_r_1,
|
ext_r_o => ext_r_r_1
|
ext_r_o => ext_r_r_1
|
);
|
);
|
|
|
row2 : ext_val
|
row2 : ext_val
|
port map (
|
port map (
|
ext_a_i => r1,
|
ext_a_i => r1,
|
ext_b_i => ext_b_r_2,
|
ext_b_i => ext_b_r_2,
|
ext_r_o => ext_r_r_2
|
ext_r_o => ext_r_r_2
|
);
|
);
|
|
|
row3 : ext_val
|
row3 : ext_val
|
port map (
|
port map (
|
ext_a_i => r1,
|
ext_a_i => r1,
|
ext_b_i => ext_b_r_3,
|
ext_b_i => ext_b_r_3,
|
ext_r_o => ext_r_r_3
|
ext_r_o => ext_r_r_3
|
);
|
);
|
|
|
col0 : ext_val
|
col0 : ext_val
|
port map (
|
port map (
|
ext_a_i => c0,
|
ext_a_i => c0,
|
ext_b_i => ext_b_c_0,
|
ext_b_i => ext_b_c_0,
|
ext_r_o => ext_r_c_0
|
ext_r_o => ext_r_c_0
|
);
|
);
|
|
|
col1 : ext_val
|
col1 : ext_val
|
port map (
|
port map (
|
ext_a_i => c1,
|
ext_a_i => c1,
|
ext_b_i => ext_b_c_1,
|
ext_b_i => ext_b_c_1,
|
ext_r_o => ext_r_c_1
|
ext_r_o => ext_r_c_1
|
);
|
);
|
|
|
col2 : ext_val
|
col2 : ext_val
|
port map (
|
port map (
|
ext_a_i => c0,
|
ext_a_i => c0,
|
ext_b_i => ext_b_c_2,
|
ext_b_i => ext_b_c_2,
|
ext_r_o => ext_r_c_2
|
ext_r_o => ext_r_c_2
|
);
|
);
|
|
|
col3 : ext_val
|
col3 : ext_val
|
port map (
|
port map (
|
ext_a_i => c1,
|
ext_a_i => c1,
|
ext_b_i => ext_b_c_3,
|
ext_b_i => ext_b_c_3,
|
ext_r_o => ext_r_c_3
|
ext_r_o => ext_r_c_3
|
);
|
);
|
|
|
process (start)
|
process (start)
|
begin
|
begin
|
if (start = '1' and start'event) then
|
if (start = '1' and start'event) then
|
|
|
y0p <= y0p_b (07);
|
y0p <= y0p_b (07);
|
y1p <= y1p_b (07);
|
y1p <= y1p_b (07);
|
y2p <= y2p_b (07);
|
y2p <= y2p_b (07);
|
y3p <= y3p_b (07);
|
y3p <= y3p_b (07);
|
|
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
process (start)
|
process (start)
|
begin
|
begin
|
if (start = '0' and start'event) then
|
if (start = '0' and start'event) then
|
|
|
y0d <= y0p;
|
y0d <= y0p;
|
y1d <= y1p;
|
y1d <= y1p;
|
y2d <= y2p;
|
y2d <= y2p;
|
y3d <= y3p;
|
y3d <= y3p;
|
|
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
process (clock, start)
|
process (clock, start)
|
begin
|
begin
|
|
|
if (clock = '0' and clock'event) then
|
if (clock = '0' and clock'event) then
|
|
|
if (start = '1') then
|
if (start = '1') then
|
y0e <= ( others => '0' );
|
y0e <= ( others => '0' );
|
y1e <= ( others => '0' );
|
y1e <= ( others => '0' );
|
y2e <= ( others => '0' );
|
y2e <= ( others => '0' );
|
y3e <= ( others => '0' );
|
y3e <= ( others => '0' );
|
|
|
augend_sum_c_0 <= ( others => '0' );
|
augend_sum_c_0 <= ( others => '0' );
|
augend_sum_c_1 <= ( others => '0' );
|
augend_sum_c_1 <= ( others => '0' );
|
augend_sum_c_2 <= ( others => '0' );
|
augend_sum_c_2 <= ( others => '0' );
|
augend_sum_c_3 <= ( others => '0' );
|
augend_sum_c_3 <= ( others => '0' );
|
else
|
else
|
y0e <= ext_r_c_0;
|
y0e <= ext_r_c_0;
|
y1e <= ext_r_c_1;
|
y1e <= ext_r_c_1;
|
y2e <= ext_r_c_2;
|
y2e <= ext_r_c_2;
|
y3e <= ext_r_c_3;
|
y3e <= ext_r_c_3;
|
|
|
augend_sum_c_0 <= ext_r_r_0;
|
augend_sum_c_0 <= ext_r_r_0;
|
augend_sum_c_1 <= ext_r_r_1;
|
augend_sum_c_1 <= ext_r_r_1;
|
augend_sum_c_2 <= ext_r_r_2;
|
augend_sum_c_2 <= ext_r_r_2;
|
augend_sum_c_3 <= ext_r_r_3;
|
augend_sum_c_3 <= ext_r_r_3;
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
end structural;
|
end structural;
|
|
|