-- $Id: ser2par8bit.vhdl,v 1.1.1.1 2005-11-15 01:52:31 arif_endro Exp $
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-- $Id: ser2par8bit.vhdl,v 1.1.1.1 2005-11-15 01:52:31 arif_endro Exp $
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Title : Serial to paralel 8bit
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-- Title : Serial to paralel 8bit
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-- Project :
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-- Project :
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : ser2par8bit.vhdl
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-- File : ser2par8bit.vhdl
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-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
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-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
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-- Created : 2005/11/01
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-- Created : 2005/11/01
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-- Last update :
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-- Last update :
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-- Simulators :
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-- Simulators :
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-- Synthesizers:
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-- Synthesizers:
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-- Target :
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-- Target :
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Description : Conversion from serial input to paralel output
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-- Description : Conversion from serial input to paralel output
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Copyright (C) 2005 Arif E. Nugroho
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-- Copyright (C) 2005 Arif E. Nugroho
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-- This VHDL design file is an open design; you can redistribute it and/or
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-- This VHDL design file is an open design; you can redistribute it and/or
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-- modify it and/or implement it after contacting the author
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-- modify it and/or implement it after contacting the author
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
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-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
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-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
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-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
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-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
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-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
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-- ASSOCIATED DISCLAIMER.
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-- ASSOCIATED DISCLAIMER.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
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-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
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-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.ALL;
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use IEEE.std_logic_1164.ALL;
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entity ser2par8bit is
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entity ser2par8bit is
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port (
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port (
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clock : in bit;
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clock : in bit;
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clear : in bit;
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clear : in bit;
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start : in bit;
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start : in bit;
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rxin : in bit_vector (07 downto 00);
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rxin : in bit_vector (07 downto 00);
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y0 : out bit_vector (07 downto 00);
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y0 : out bit_vector (07 downto 00);
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y1 : out bit_vector (07 downto 00);
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y1 : out bit_vector (07 downto 00);
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y2 : out bit_vector (07 downto 00);
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y2 : out bit_vector (07 downto 00);
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y3 : out bit_vector (07 downto 00);
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y3 : out bit_vector (07 downto 00);
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r0 : out bit_vector (07 downto 00);
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r0 : out bit_vector (07 downto 00);
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r1 : out bit_vector (07 downto 00);
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r1 : out bit_vector (07 downto 00);
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c0 : out bit_vector (07 downto 00);
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c0 : out bit_vector (07 downto 00);
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c1 : out bit_vector (07 downto 00)
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c1 : out bit_vector (07 downto 00)
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);
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);
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end ser2par8bit;
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end ser2par8bit;
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architecture data_flow of ser2par8bit is
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architecture data_flow of ser2par8bit is
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subtype type_word is bit_vector (07 downto 00);
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subtype type_word is bit_vector (07 downto 00);
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type type_fifo is array (09 downto 00) of type_word;
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type type_fifo is array (09 downto 00) of type_word;
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signal fifo8bx7 : type_fifo;
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signal fifo8bx7 : type_fifo;
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begin
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begin
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process (clock, clear)
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process (clock, clear)
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begin
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begin
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if (clear = '1') then
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if (clear = '1') then
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fifo8bx7 (00) <= (others => '0');
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fifo8bx7 (00) <= (others => '0');
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fifo8bx7 (01) <= (others => '0');
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fifo8bx7 (01) <= (others => '0');
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fifo8bx7 (02) <= (others => '0');
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fifo8bx7 (02) <= (others => '0');
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fifo8bx7 (03) <= (others => '0');
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fifo8bx7 (03) <= (others => '0');
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fifo8bx7 (04) <= (others => '0');
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fifo8bx7 (04) <= (others => '0');
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fifo8bx7 (05) <= (others => '0');
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fifo8bx7 (05) <= (others => '0');
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fifo8bx7 (06) <= (others => '0');
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fifo8bx7 (06) <= (others => '0');
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fifo8bx7 (07) <= (others => '0');
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fifo8bx7 (07) <= (others => '0');
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fifo8bx7 (08) <= (others => '0');
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fifo8bx7 (08) <= (others => '0');
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fifo8bx7 (09) <= (others => '0');
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fifo8bx7 (09) <= (others => '0');
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elsif ((clock = '0') and clock'event) then
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elsif ((clock = '0') and clock'event) then
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fifo8bx7 (00) <= rxin (07 downto 00);
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fifo8bx7 (00) <= rxin (07 downto 00);
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fifo8bx7 (09 downto 01) <= fifo8bx7 (08 downto 00);
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fifo8bx7 (09 downto 01) <= fifo8bx7 (08 downto 00);
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end if;
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end if;
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end process;
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end process;
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process (start)
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process (start)
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begin
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begin
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if (start = '0' and start'event) then
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if (start = '0' and start'event) then
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y0 <= fifo8bx7 (08);
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y0 <= fifo8bx7 (08);
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y1 <= fifo8bx7 (07);
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y1 <= fifo8bx7 (07);
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y2 <= fifo8bx7 (06);
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y2 <= fifo8bx7 (06);
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y3 <= fifo8bx7 (05);
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y3 <= fifo8bx7 (05);
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r0 <= fifo8bx7 (04);
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r0 <= fifo8bx7 (04);
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r1 <= fifo8bx7 (03);
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r1 <= fifo8bx7 (03);
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c0 <= fifo8bx7 (02);
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c0 <= fifo8bx7 (02);
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c1 <= fifo8bx7 (01);
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c1 <= fifo8bx7 (01);
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end if;
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end if;
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end process;
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end process;
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end data_flow;
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end data_flow;
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