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[/] [product_code_iterative_decoder/] [trunk/] [source/] [adder_08bit.vhdl] - Diff between revs 14 and 18

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-- $Id: adder_08bit.vhdl,v 1.1.1.1 2005-11-15 01:52:30 arif_endro Exp $
-- ------------------------------------------------------------------------
-------------------------------------------------------------------------------
 
-- Title       : 8 bit adder
 
-- Project     : 
 
-------------------------------------------------------------------------------
 
-- File        : adder_08bit.vhdl
 
-- Author      : "Arif E. Nugroho" <arif_endro@yahoo.com>
 
-- Created     : 2005/11/01
 
-- Last update : 
 
-- Simulators  :
 
-- Synthesizers: 
 
-- Target      : 
 
-------------------------------------------------------------------------------
 
-- Description : 8 bit signed adder
 
-------------------------------------------------------------------------------
 
-- Copyright (C) 2005 Arif Endro Nugroho
-- Copyright (C) 2005 Arif Endro Nugroho
-------------------------------------------------------------------------------
-- All rights reserved.
-- 
-- 
--      THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
-- Redistribution and use in source and binary forms, with or without
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
-- modification, are permitted provided that the following conditions
-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
-- are met:
-- ASSOCIATED DISCLAIMER.
 
-- 
-- 
-------------------------------------------------------------------------------
-- 1. Redistributions of source code must retain the above copyright
 
--    notice, this list of conditions and the following disclaimer.
 
-- 2. Redistributions in binary form must reproduce the above copyright
 
--    notice, this list of conditions and the following disclaimer in the
 
--    documentation and/or other materials provided with the distribution.
-- 
-- 
--      THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 
-- POSSIBILITY OF SUCH DAMAGE.
-- 
-- 
-------------------------------------------------------------------------------
-- End Of License.
 
-- ------------------------------------------------------------------------
 
 
library IEEE;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_1164.all;
 
 
entity adder_08bit is
entity adder_08bit is
   port (
   port (
      addend_08bit  : in  bit_vector (07 downto 0);
      addend_08bit  : in  bit_vector (07 downto 0);
      augend_08bit  : in  bit_vector (07 downto 0);
      augend_08bit  : in  bit_vector (07 downto 0);
      adder08_output: out bit_vector (08 downto 0)
      adder08_output: out bit_vector (08 downto 0)
      );
      );
end adder_08bit;
end adder_08bit;
 
 
architecture structural of adder_08bit is
architecture structural of adder_08bit is
 
 
   component fulladder
   component fulladder
      port (
      port (
      addend        : in   bit;
      addend        : in   bit;
      augend        : in   bit;
      augend        : in   bit;
      carry_in      : in   bit;
      carry_in      : in   bit;
      sum           : out  bit;
      sum           : out  bit;
      carry         : out  bit
      carry         : out  bit
      );
      );
   end component;
   end component;
 
 
signal c00 : bit;
signal c00 : bit;
signal c01 : bit;
signal c01 : bit;
signal c02 : bit;
signal c02 : bit;
signal c03 : bit;
signal c03 : bit;
signal c04 : bit;
signal c04 : bit;
signal c05 : bit;
signal c05 : bit;
signal c06 : bit;
signal c06 : bit;
signal c07 : bit;
signal c07 : bit;
signal c08 : bit;
signal c08 : bit;
signal over08 : bit;
signal over08 : bit;
signal adder08_output_int : bit_vector (08 downto 0);
signal adder08_output_int : bit_vector (08 downto 0);
 
 
begin
begin
 
 
c00                     <= '0';
c00                     <= '0';
over08                  <= (addend_08bit (07) xor augend_08bit (07));
over08                  <= (addend_08bit (07) xor augend_08bit (07));
adder08_output_int (08) <= ((adder08_output_int (07) and over08) or
adder08_output_int (08) <= ((adder08_output_int (07) and over08) or
                           (c08 and (not (over08))));
                           (c08 and (not (over08))));
adder08_output          <= adder08_output_int;
adder08_output          <= adder08_output_int;
 
 
fa07 : fulladder
fa07 : fulladder
   port map (
   port map (
      addend     => addend_08bit(07),
      addend     => addend_08bit(07),
      augend     => augend_08bit(07),
      augend     => augend_08bit(07),
      carry_in   => c07,
      carry_in   => c07,
      sum        => adder08_output_int(07),
      sum        => adder08_output_int(07),
      carry      => c08
      carry      => c08
      );
      );
 
 
fa06 : fulladder
fa06 : fulladder
   port map (
   port map (
      addend     => addend_08bit(06),
      addend     => addend_08bit(06),
      augend     => augend_08bit(06),
      augend     => augend_08bit(06),
      carry_in   => c06,
      carry_in   => c06,
      sum        => adder08_output_int(06),
      sum        => adder08_output_int(06),
      carry      => c07
      carry      => c07
      );
      );
 
 
fa05 : fulladder
fa05 : fulladder
   port map (
   port map (
      addend     => addend_08bit(05),
      addend     => addend_08bit(05),
      augend     => augend_08bit(05),
      augend     => augend_08bit(05),
      carry_in   => c05,
      carry_in   => c05,
      sum        => adder08_output_int(05),
      sum        => adder08_output_int(05),
      carry      => c06
      carry      => c06
      );
      );
 
 
fa04 : fulladder
fa04 : fulladder
   port map (
   port map (
      addend     => addend_08bit(04),
      addend     => addend_08bit(04),
      augend     => augend_08bit(04),
      augend     => augend_08bit(04),
      carry_in   => c04,
      carry_in   => c04,
      sum        => adder08_output_int(04),
      sum        => adder08_output_int(04),
      carry      => c05
      carry      => c05
      );
      );
 
 
fa03 : fulladder
fa03 : fulladder
   port map (
   port map (
      addend     => addend_08bit(03),
      addend     => addend_08bit(03),
      augend     => augend_08bit(03),
      augend     => augend_08bit(03),
      carry_in   => c03,
      carry_in   => c03,
      sum        => adder08_output_int(03),
      sum        => adder08_output_int(03),
      carry      => c04
      carry      => c04
      );
      );
 
 
fa02 : fulladder
fa02 : fulladder
   port map (
   port map (
      addend     => addend_08bit(02),
      addend     => addend_08bit(02),
      augend     => augend_08bit(02),
      augend     => augend_08bit(02),
      carry_in   => c02,
      carry_in   => c02,
      sum        => adder08_output_int(02),
      sum        => adder08_output_int(02),
      carry      => c03
      carry      => c03
      );
      );
 
 
fa01 : fulladder
fa01 : fulladder
   port map (
   port map (
      addend     => addend_08bit(01),
      addend     => addend_08bit(01),
      augend     => augend_08bit(01),
      augend     => augend_08bit(01),
      carry_in   => c01,
      carry_in   => c01,
      sum        => adder08_output_int(01),
      sum        => adder08_output_int(01),
      carry      => c02
      carry      => c02
      );
      );
 
 
fa00 : fulladder
fa00 : fulladder
   port map (
   port map (
      addend     => addend_08bit(00),
      addend     => addend_08bit(00),
      augend     => augend_08bit(00),
      augend     => augend_08bit(00),
      carry_in   => c00,
      carry_in   => c00,
      sum        => adder08_output_int(00),
      sum        => adder08_output_int(00),
      carry      => c01
      carry      => c01
      );
      );
 
 
end structural;
end structural;
 
 

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