-- $Id: adder_08bit.vhdl,v 1.1.1.1 2005-11-15 01:52:30 arif_endro Exp $
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-- ------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Title : 8 bit adder
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-- Project :
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-------------------------------------------------------------------------------
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-- File : adder_08bit.vhdl
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-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
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-- Created : 2005/11/01
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-- Last update :
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-- Simulators :
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-- Synthesizers:
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-- Target :
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-------------------------------------------------------------------------------
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-- Description : 8 bit signed adder
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-------------------------------------------------------------------------------
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-- Copyright (C) 2005 Arif Endro Nugroho
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-- Copyright (C) 2005 Arif Endro Nugroho
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-------------------------------------------------------------------------------
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-- All rights reserved.
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--
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--
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-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
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-- Redistribution and use in source and binary forms, with or without
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-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
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-- modification, are permitted provided that the following conditions
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-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
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-- are met:
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-- ASSOCIATED DISCLAIMER.
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--
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--
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-------------------------------------------------------------------------------
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-- 1. Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- 2. Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
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-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
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-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-------------------------------------------------------------------------------
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-- End Of License.
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-- ------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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entity adder_08bit is
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entity adder_08bit is
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port (
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port (
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addend_08bit : in bit_vector (07 downto 0);
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addend_08bit : in bit_vector (07 downto 0);
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augend_08bit : in bit_vector (07 downto 0);
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augend_08bit : in bit_vector (07 downto 0);
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adder08_output: out bit_vector (08 downto 0)
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adder08_output: out bit_vector (08 downto 0)
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);
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);
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end adder_08bit;
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end adder_08bit;
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architecture structural of adder_08bit is
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architecture structural of adder_08bit is
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component fulladder
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component fulladder
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port (
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port (
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addend : in bit;
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addend : in bit;
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augend : in bit;
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augend : in bit;
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carry_in : in bit;
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carry_in : in bit;
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sum : out bit;
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sum : out bit;
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carry : out bit
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carry : out bit
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);
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);
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end component;
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end component;
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signal c00 : bit;
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signal c00 : bit;
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signal c01 : bit;
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signal c01 : bit;
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signal c02 : bit;
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signal c02 : bit;
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signal c03 : bit;
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signal c03 : bit;
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signal c04 : bit;
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signal c04 : bit;
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signal c05 : bit;
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signal c05 : bit;
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signal c06 : bit;
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signal c06 : bit;
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signal c07 : bit;
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signal c07 : bit;
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signal c08 : bit;
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signal c08 : bit;
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signal over08 : bit;
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signal over08 : bit;
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signal adder08_output_int : bit_vector (08 downto 0);
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signal adder08_output_int : bit_vector (08 downto 0);
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begin
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begin
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c00 <= '0';
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c00 <= '0';
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over08 <= (addend_08bit (07) xor augend_08bit (07));
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over08 <= (addend_08bit (07) xor augend_08bit (07));
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adder08_output_int (08) <= ((adder08_output_int (07) and over08) or
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adder08_output_int (08) <= ((adder08_output_int (07) and over08) or
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(c08 and (not (over08))));
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(c08 and (not (over08))));
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adder08_output <= adder08_output_int;
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adder08_output <= adder08_output_int;
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fa07 : fulladder
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fa07 : fulladder
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port map (
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port map (
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addend => addend_08bit(07),
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addend => addend_08bit(07),
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augend => augend_08bit(07),
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augend => augend_08bit(07),
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carry_in => c07,
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carry_in => c07,
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sum => adder08_output_int(07),
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sum => adder08_output_int(07),
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carry => c08
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carry => c08
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);
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);
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fa06 : fulladder
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fa06 : fulladder
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port map (
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port map (
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addend => addend_08bit(06),
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addend => addend_08bit(06),
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augend => augend_08bit(06),
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augend => augend_08bit(06),
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carry_in => c06,
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carry_in => c06,
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sum => adder08_output_int(06),
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sum => adder08_output_int(06),
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carry => c07
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carry => c07
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);
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);
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fa05 : fulladder
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fa05 : fulladder
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port map (
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port map (
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addend => addend_08bit(05),
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addend => addend_08bit(05),
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augend => augend_08bit(05),
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augend => augend_08bit(05),
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carry_in => c05,
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carry_in => c05,
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sum => adder08_output_int(05),
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sum => adder08_output_int(05),
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carry => c06
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carry => c06
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);
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);
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fa04 : fulladder
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fa04 : fulladder
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port map (
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port map (
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addend => addend_08bit(04),
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addend => addend_08bit(04),
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augend => augend_08bit(04),
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augend => augend_08bit(04),
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carry_in => c04,
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carry_in => c04,
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sum => adder08_output_int(04),
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sum => adder08_output_int(04),
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carry => c05
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carry => c05
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);
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);
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fa03 : fulladder
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fa03 : fulladder
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port map (
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port map (
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addend => addend_08bit(03),
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addend => addend_08bit(03),
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augend => augend_08bit(03),
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augend => augend_08bit(03),
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carry_in => c03,
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carry_in => c03,
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sum => adder08_output_int(03),
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sum => adder08_output_int(03),
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carry => c04
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carry => c04
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);
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);
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fa02 : fulladder
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fa02 : fulladder
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port map (
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port map (
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addend => addend_08bit(02),
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addend => addend_08bit(02),
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augend => augend_08bit(02),
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augend => augend_08bit(02),
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carry_in => c02,
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carry_in => c02,
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sum => adder08_output_int(02),
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sum => adder08_output_int(02),
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carry => c03
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carry => c03
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);
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);
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fa01 : fulladder
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fa01 : fulladder
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port map (
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port map (
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addend => addend_08bit(01),
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addend => addend_08bit(01),
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augend => augend_08bit(01),
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augend => augend_08bit(01),
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carry_in => c01,
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carry_in => c01,
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sum => adder08_output_int(01),
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sum => adder08_output_int(01),
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carry => c02
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carry => c02
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);
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);
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fa00 : fulladder
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fa00 : fulladder
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port map (
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port map (
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addend => addend_08bit(00),
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addend => addend_08bit(00),
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augend => augend_08bit(00),
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augend => augend_08bit(00),
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carry_in => c00,
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carry_in => c00,
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sum => adder08_output_int(00),
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sum => adder08_output_int(00),
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carry => c01
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carry => c01
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);
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);
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end structural;
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end structural;
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