-- $Id: xilinx.vhdl,v 1.1 2006-01-16 03:40:22 arif_endro Exp $
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-- ------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Title :
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-- Project :
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-------------------------------------------------------------------------------
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-- File :
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-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
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-- Created : 2005/12/18
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-- Last update :
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-- Simulators :
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-- Synthesizers: ISE Xilinx 6.3i
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-- Target :
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-------------------------------------------------------------------------------
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-- Description :
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-------------------------------------------------------------------------------
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-- Copyright (C) 2005 Arif Endro Nugroho
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-- Copyright (C) 2005 Arif Endro Nugroho
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-------------------------------------------------------------------------------
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-- All rights reserved.
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--
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--
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-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
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-- Redistribution and use in source and binary forms, with or without
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-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
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-- modification, are permitted provided that the following conditions
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-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
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-- are met:
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-- ASSOCIATED DISCLAIMER.
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--
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--
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-------------------------------------------------------------------------------
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-- 1. Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- 2. Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
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-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
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-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-------------------------------------------------------------------------------
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-- End Of License.
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-- ------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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entity xilinx is
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entity xilinx is
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port (
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port (
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clock : in bit;
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clock : in bit;
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clear : in bit;
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clear : in bit;
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start : out bit;
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start : out bit;
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rom_pos : out integer;
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rom_pos : out integer;
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y0d : out bit;
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y0d : out bit;
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y1d : out bit;
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y1d : out bit;
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y2d : out bit;
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y2d : out bit;
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y3d : out bit;
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y3d : out bit;
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senddata : out bit_vector (3 downto 0);
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senddata : out bit_vector (3 downto 0);
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match : out bit_vector (3 downto 0);
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match : out bit_vector (3 downto 0);
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bit_error : out integer
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bit_error : out integer
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);
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);
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end xilinx;
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end xilinx;
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architecture structural of xilinx is
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architecture structural of xilinx is
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component product_code
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component product_code
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port (
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port (
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clock : in bit;
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clock : in bit;
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start : in bit;
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start : in bit;
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rxin : in bit_vector (07 downto 00);
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rxin : in bit_vector (07 downto 00);
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y0d : out bit;
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y0d : out bit;
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y1d : out bit;
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y1d : out bit;
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y2d : out bit;
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y2d : out bit;
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y3d : out bit
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y3d : out bit
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);
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);
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end component;
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end component;
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component input
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component input
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port (
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port (
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clock : in bit;
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clock : in bit;
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clear : in bit;
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clear : in bit;
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start : out bit;
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start : out bit;
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rom_pos : out integer;
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rom_pos : out integer;
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rxin : out bit_vector (07 downto 00)
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rxin : out bit_vector (07 downto 00)
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);
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);
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end component;
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end component;
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component reference
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component reference
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port (
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port (
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clear : in bit;
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clear : in bit;
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start : in bit;
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start : in bit;
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y0 : in bit;
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y0 : in bit;
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y1 : in bit;
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y1 : in bit;
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y2 : in bit;
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y2 : in bit;
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y3 : in bit;
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y3 : in bit;
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senddata : out bit_vector (3 downto 0);
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senddata : out bit_vector (3 downto 0);
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match : out bit_vector (3 downto 0)
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match : out bit_vector (3 downto 0)
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);
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);
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end component;
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end component;
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component analyze
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component analyze
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port (
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port (
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clear : in bit;
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clear : in bit;
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start : in bit;
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start : in bit;
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match : in bit_vector (3 downto 0);
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match : in bit_vector (3 downto 0);
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col_0 : out integer;
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col_0 : out integer;
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col_1 : out integer;
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col_1 : out integer;
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col_2 : out integer;
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col_2 : out integer;
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col_3 : out integer;
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col_3 : out integer;
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result : out integer
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result : out integer
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);
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);
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end component;
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end component;
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signal str : bit;
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signal str : bit;
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signal y0 : bit;
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signal y0 : bit;
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signal y1 : bit;
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signal y1 : bit;
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signal y2 : bit;
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signal y2 : bit;
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signal y3 : bit;
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signal y3 : bit;
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signal rxin : bit_vector (07 downto 00);
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signal rxin : bit_vector (07 downto 00);
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signal mtch : bit_vector (03 downto 00);
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signal mtch : bit_vector (03 downto 00);
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signal col_0 : integer;
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signal col_0 : integer;
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signal col_1 : integer;
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signal col_1 : integer;
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signal col_2 : integer;
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signal col_2 : integer;
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signal col_3 : integer;
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signal col_3 : integer;
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begin
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begin
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start <= str;
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start <= str;
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match <= mtch;
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match <= mtch;
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y0d <= y0;
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y0d <= y0;
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y1d <= y1;
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y1d <= y1;
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y2d <= y2;
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y2d <= y2;
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y3d <= y3;
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y3d <= y3;
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my_product_code : product_code
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my_product_code : product_code
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port map (
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port map (
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clock => clock,
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clock => clock,
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start => str,
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start => str,
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rxin => rxin,
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rxin => rxin,
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y0d => y0,
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y0d => y0,
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y1d => y1,
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y1d => y1,
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y2d => y2,
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y2d => y2,
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y3d => y3
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y3d => y3
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);
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);
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my_input : input
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my_input : input
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port map (
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port map (
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clock => clock,
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clock => clock,
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clear => clear,
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clear => clear,
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start => str,
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start => str,
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rom_pos => rom_pos,
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rom_pos => rom_pos,
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rxin => rxin
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rxin => rxin
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);
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);
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my_senddata: reference
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my_senddata: reference
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port map (
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port map (
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clear => clear,
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clear => clear,
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start => str,
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start => str,
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y0 => y0,
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y0 => y0,
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y1 => y1,
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y1 => y1,
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y2 => y2,
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y2 => y2,
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y3 => y3,
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y3 => y3,
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senddata=> senddata,
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senddata=> senddata,
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match => mtch
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match => mtch
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);
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);
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my_analyzer: analyze
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my_analyzer: analyze
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port map (
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port map (
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clear => clear,
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clear => clear,
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start => str,
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start => str,
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match => mtch,
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match => mtch,
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col_0 => col_0,
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col_0 => col_0,
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col_1 => col_1,
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col_1 => col_1,
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col_2 => col_2,
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col_2 => col_2,
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col_3 => col_3,
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col_3 => col_3,
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result => bit_error
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result => bit_error
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);
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);
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end structural;
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end structural;
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