//-------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------
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//
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//
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// Author: John Clayton
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// Author: John Clayton
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// Date : April 30, 2001
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// Date : April 30, 2001
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// Update: 6/06/01 copied this file from ps2.v (pared down).
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// Update: 6/06/01 copied this file from ps2.v (pared down).
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// Update: 6/07/01 Finished initial coding efforts.
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// Update: 6/07/01 Finished initial coding efforts.
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// Update: 6/09/01 Made minor changes to state machines during debugging.
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// Update: 6/09/01 Made minor changes to state machines during debugging.
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// Fixed errors in state transitions. Added state to m2
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// Fixed errors in state transitions. Added state to m2
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// so that "reset" causes the mouse to be initialized.
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// so that "reset" causes the mouse to be initialized.
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// Removed debug port.
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// Removed debug port.
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//
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//
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//
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//
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//
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//
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//
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//
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//
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//
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// Description
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// Description
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//-------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------
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// This is a state-machine driven serial-to-parallel and parallel-to-serial
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// This is a state-machine driven serial-to-parallel and parallel-to-serial
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// interface to the ps2 style mouse. The state diagram for part of the
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// interface to the ps2 style mouse. The state diagram for part of the
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// m2 state machine was obtained from the work of Rob Chapman, as published
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// m2 state machine was obtained from the work of Rob Chapman, as published
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// at:
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// at:
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// www.ee.ualberta.ca/~elliott/ee552/studentAppNotes/1998_w/mouse_notes.html
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// www.ee.ualberta.ca/~elliott/ee552/studentAppNotes/1998_w/mouse_notes.html
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//
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//
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//
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//
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// Some aspects of the mouse interface are not implemented (e.g, verifying
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// Some aspects of the mouse interface are not implemented (e.g, verifying
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// the FA response code from the mouse when enabling streaming mode.)
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// the FA response code from the mouse when enabling streaming mode.)
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// However, the mouse interface was designed so that "hot plugging" a mouse
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// However, the mouse interface was designed so that "hot plugging" a mouse
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// into the connector should cause the interface to send the F4 code to the
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// into the connector should cause the interface to send the F4 code to the
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// mouse in order to enable streaming. By this means, the mouse begins to
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// mouse in order to enable streaming. By this means, the mouse begins to
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// operate, and no reset pulse should be needed.
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// operate, and no reset pulse should be needed.
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//
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//
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// Similarly, there is a "watchdog" timer implemented, so that during periods
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// Similarly, there is a "watchdog" timer implemented, so that during periods
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// of inactivity, the bit_count is cleared to zero. Therefore, the effects of
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// of inactivity, the bit_count is cleared to zero. Therefore, the effects of
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// a bad count value are corrected, and internal errors of that type are not
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// a bad count value are corrected, and internal errors of that type are not
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// propagated into subsequent packet receive operations.
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// propagated into subsequent packet receive operations.
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//
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//
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// To enable the streaming mode, F4 is sent to the mouse.
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// To enable the streaming mode, F4 is sent to the mouse.
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// The mouse responds with FA to acknowledge the command, and then enters
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// The mouse responds with FA to acknowledge the command, and then enters
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// streaming mode at the default rate of 100 packets per second (transmission
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// streaming mode at the default rate of 100 packets per second (transmission
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// of packets ceases when the activity at the mouse is not longer sensed.)
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// of packets ceases when the activity at the mouse is not longer sensed.)
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//
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//
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// There are additional commands to change the sampling rate and resolution
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// There are additional commands to change the sampling rate and resolution
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// of the mouse reported data. Those commands are not implemented here.
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// of the mouse reported data. Those commands are not implemented here.
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// (E8,XX = set resolution 0,1,2,3)
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// (E8,XX = set resolution 0,1,2,3)
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// (E7 = set scaling 2:1)
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// (E7 = set scaling 2:1)
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// (E6 = reset scaling)
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// (E6 = reset scaling)
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// (F3,XX = set sampling rate to XX packets per second.)
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// (F3,XX = set sampling rate to XX packets per second.)
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//
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//
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// At this time I do not know any of the command related to using the
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// At this time I do not know any of the command related to using the
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// wheel of a "wheel mouse."
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// wheel of a "wheel mouse."
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//
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//
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// The packets consists of three bytes transmitted in sequence. The interval
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// The packets consists of three bytes transmitted in sequence. The interval
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// between these bytes has been measured on two different mice, and found to
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// between these bytes has been measured on two different mice, and found to
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// be different. On the slower (older) mouse it was approximately 345
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// be different. On the slower (older) mouse it was approximately 345
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// microseconds, while on a newer "wheel" mouse it was approximately 125
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// microseconds, while on a newer "wheel" mouse it was approximately 125
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// microseconds. The watchdog timer is designed to cause processing of a
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// microseconds. The watchdog timer is designed to cause processing of a
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// complete packet when it expires. Therefore, the watchdog timer must last
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// complete packet when it expires. Therefore, the watchdog timer must last
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// for longer than the "inter-byte delay" between bytes of the packet.
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// for longer than the "inter-byte delay" between bytes of the packet.
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// I have set the default timer value to 400 usec, for my 49.152 MHz clock.
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// I have set the default timer value to 400 usec, for my 49.152 MHz clock.
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// The timer value and size of the timer counter is settable by parameters,
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// The timer value and size of the timer counter is settable by parameters,
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// so that other clock frequencies and settings may be used. The setting for
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// so that other clock frequencies and settings may be used. The setting for
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// the watchdog timeout is not critical -- it only needs to be greater than
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// the watchdog timeout is not critical -- it only needs to be greater than
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// the inter-byte delay as data is transmitted from the mouse, and no less
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// the inter-byte delay as data is transmitted from the mouse, and no less
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// than 60usec.
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// than 60usec.
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//
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//
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// Each "byte" of the packet is transmitted from the mouse as follows:
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// Each "byte" of the packet is transmitted from the mouse as follows:
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//
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//
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// 1 start bit, 8 data bits, 1 odd parity bit, 1 stop bit. == 11 bits total.
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// 1 start bit, 8 data bits, 1 odd parity bit, 1 stop bit. == 11 bits total.
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// (The data bits are sent LSB first)
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// (The data bits are sent LSB first)
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//
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//
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// The data bits are formatted as follows:
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// The data bits are formatted as follows:
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//
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//
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// byte 0: YV, XV, YS, XS, 1, 0, R, L
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// byte 0: YV, XV, YS, XS, 1, 0, R, L
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// byte 1: X7..X0
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// byte 1: X7..X0
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// byte 2: Y7..Y0
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// byte 2: Y7..Y0
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//
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//
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// Where YV, XV are set to indicate overflow conditions.
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// Where YV, XV are set to indicate overflow conditions.
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// XS, YS are set to indicate negative quantities (sign bits).
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// XS, YS are set to indicate negative quantities (sign bits).
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// R, L are set to indicate buttons pressed, left and right.
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// R, L are set to indicate buttons pressed, left and right.
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//
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//
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//
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//
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//
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//
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// The interface to the ps2 mouse (like the keyboard) uses clock rates of
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// The interface to the ps2 mouse (like the keyboard) uses clock rates of
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// 30-40 kHz, dependent upon the mouse itself. The mouse generates the
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// 30-40 kHz, dependent upon the mouse itself. The mouse generates the
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// clock.
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// clock.
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// The rate at which the state machine runs should be at least twice the
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// The rate at which the state machine runs should be at least twice the
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// rate of the ps2_clk, so that the states can accurately follow the clock
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// rate of the ps2_clk, so that the states can accurately follow the clock
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// signal itself. Four times oversampling is better. Say 200kHz at least.
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// signal itself. Four times oversampling is better. Say 200kHz at least.
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// In order to run the state machine extremely fast, synchronizing flip-flops
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// In order to run the state machine extremely fast, synchronizing flip-flops
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// have been added to the ps2_clk and ps2_data inputs of the state machine.
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// have been added to the ps2_clk and ps2_data inputs of the state machine.
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// This avoids poor performance related to slow transitions of the inputs.
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// This avoids poor performance related to slow transitions of the inputs.
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//
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//
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// Because this is a bi-directional interface, while reading from the mouse
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// Because this is a bi-directional interface, while reading from the mouse
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// the ps2_clk and ps2_data lines are used as inputs. While writing to the
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// the ps2_clk and ps2_data lines are used as inputs. While writing to the
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// mouse, however (which is done when a "packet" of less than 33 bits is
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// mouse, however (which is done when a "packet" of less than 33 bits is
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// received), both the ps2_clk and ps2_data lines are sometime pulled low by
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// received), both the ps2_clk and ps2_data lines are sometime pulled low by
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// this interface. As such, they are bidirectional, and pullups are used to
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// this interface. As such, they are bidirectional, and pullups are used to
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// return them to the "high" state, whenever the drivers are set to the
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// return them to the "high" state, whenever the drivers are set to the
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// high impedance state.
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// high impedance state.
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//
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//
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// Pullups MUST BE USED on the ps2_clk and ps2_data lines for this design,
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// Pullups MUST BE USED on the ps2_clk and ps2_data lines for this design,
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// whether they be internal to an FPGA I/O pad, or externally placed.
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// whether they be internal to an FPGA I/O pad, or externally placed.
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// If internal pullups are used, they may be fairly weak, causing bounces
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// If internal pullups are used, they may be fairly weak, causing bounces
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// due to crosstalk, etc. There is a "debounce timer" implemented in order
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// due to crosstalk, etc. There is a "debounce timer" implemented in order
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// to eliminate erroneous state transitions which would occur based on bounce.
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// to eliminate erroneous state transitions which would occur based on bounce.
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// Parameters are provided to configure the debounce timer for different
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// Parameters are provided to configure the debounce timer for different
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// clock frequencies. 2 or 3 microseconds of debounce should be plenty.
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// clock frequencies. 2 or 3 microseconds of debounce should be plenty.
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// You may possibly use much less, if your pullups are strong.
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// You may possibly use much less, if your pullups are strong.
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//
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//
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// A parameters is provided to configure a 60 microsecond period used while
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// A parameters is provided to configure a 60 microsecond period used while
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// transmitting to the mouse. The 60 microsecond period is guaranteed to be
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// transmitting to the mouse. The 60 microsecond period is guaranteed to be
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// more than one period of the ps2_clk signal.
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// more than one period of the ps2_clk signal.
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//
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//
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//
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//
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//-------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------
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`resetall
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`resetall
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`timescale 1ns/100ps
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`timescale 1ns/100ps
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`define TOTAL_BITS 33 // Number of bits in one full packet
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`define TOTAL_BITS 33 // Number of bits in one full packet
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module ps2_mouse_interface (
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module ps2_mouse_interface (
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clk,
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clk,
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reset,
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reset,
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ps2_clk,
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ps2_clk,
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ps2_data,
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ps2_data,
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left_button,
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left_button,
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right_button,
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right_button,
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x_increment,
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x_increment,
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y_increment,
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y_increment,
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data_ready, // rx_read_o
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data_ready, // rx_read_o
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read, // rx_read_ack_i
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read, // rx_read_ack_i
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error_no_ack
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error_no_ack
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);
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);
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// Parameters
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// Parameters
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// The timer value can be up to (2^bits) inclusive.
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// The timer value can be up to (2^bits) inclusive.
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parameter WATCHDOG_TIMER_VALUE_PP = 19660; // Number of sys_clks for 400usec.
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parameter WATCHDOG_TIMER_VALUE_PP = 19660; // Number of sys_clks for 400usec.
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parameter WATCHDOG_TIMER_BITS_PP = 15; // Number of bits needed for timer
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parameter WATCHDOG_TIMER_BITS_PP = 15; // Number of bits needed for timer
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parameter DEBOUNCE_TIMER_VALUE_PP = 186; // Number of sys_clks for debounce
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parameter DEBOUNCE_TIMER_VALUE_PP = 186; // Number of sys_clks for debounce
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parameter DEBOUNCE_TIMER_BITS_PP = 8; // Number of bits needed for timer
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parameter DEBOUNCE_TIMER_BITS_PP = 8; // Number of bits needed for timer
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// State encodings, provided as parameters
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// State encodings, provided as parameters
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// for flexibility to the one instantiating the module.
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// for flexibility to the one instantiating the module.
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// In general, the default values need not be changed.
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// In general, the default values need not be changed.
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// There are three state machines: m1, m2 and m3.
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// There are three state machines: m1, m2 and m3.
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// States chosen as "default" states upon power-up and configuration:
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// States chosen as "default" states upon power-up and configuration:
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// "m1_clk_h"
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// "m1_clk_h"
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// "m2_wait"
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// "m2_wait"
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// "m3_data_ready_ack"
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// "m3_data_ready_ack"
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parameter m1_clk_h = 0;
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parameter m1_clk_h = 0;
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parameter m1_falling_edge = 1;
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parameter m1_falling_edge = 1;
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parameter m1_falling_wait = 3;
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parameter m1_falling_wait = 3;
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parameter m1_clk_l = 2;
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parameter m1_clk_l = 2;
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parameter m1_rising_edge = 6;
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parameter m1_rising_edge = 6;
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parameter m1_rising_wait = 4;
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parameter m1_rising_wait = 4;
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|
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parameter m2_reset = 14;
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parameter m2_reset = 14;
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parameter m2_wait = 0;
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parameter m2_wait = 0;
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parameter m2_gather = 1;
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parameter m2_gather = 1;
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parameter m2_verify = 3;
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parameter m2_verify = 3;
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parameter m2_use = 2;
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parameter m2_use = 2;
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parameter m2_hold_clk_l = 6;
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parameter m2_hold_clk_l = 6;
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parameter m2_data_low_1 = 4;
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parameter m2_data_low_1 = 4;
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parameter m2_data_high_1 = 5;
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parameter m2_data_high_1 = 5;
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parameter m2_data_low_2 = 7;
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parameter m2_data_low_2 = 7;
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parameter m2_data_high_2 = 8;
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parameter m2_data_high_2 = 8;
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parameter m2_data_low_3 = 9;
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parameter m2_data_low_3 = 9;
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parameter m2_data_high_3 = 11;
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parameter m2_data_high_3 = 11;
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parameter m2_error_no_ack = 15;
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parameter m2_error_no_ack = 15;
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parameter m2_await_response = 10;
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parameter m2_await_response = 10;
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|
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parameter m3_data_ready = 1;
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parameter m3_data_ready = 1;
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parameter m3_data_ready_ack = 0;
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parameter m3_data_ready_ack = 0;
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// I/O declarations
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// I/O declarations
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input clk;
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input clk;
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input reset;
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input reset;
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inout ps2_clk;
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inout ps2_clk;
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inout ps2_data;
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inout ps2_data;
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output left_button;
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output left_button;
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output right_button;
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output right_button;
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output [8:0] x_increment;
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output [8:0] x_increment;
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output [8:0] y_increment;
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output [8:0] y_increment;
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output data_ready;
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output data_ready;
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input read;
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input read;
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output error_no_ack;
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output error_no_ack;
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|
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reg left_button;
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reg left_button;
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reg right_button;
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reg right_button;
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reg [8:0] x_increment;
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reg [8:0] x_increment;
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reg [8:0] y_increment;
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reg [8:0] y_increment;
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reg data_ready;
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reg data_ready;
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reg error_no_ack;
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reg error_no_ack;
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// Internal signal declarations
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// Internal signal declarations
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wire watchdog_timer_done;
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wire watchdog_timer_done;
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wire debounce_timer_done;
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wire debounce_timer_done;
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wire packet_good;
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wire packet_good;
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reg [`TOTAL_BITS-1:0] q; // Shift register
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reg [`TOTAL_BITS-1:0] q; // Shift register
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reg [2:0] m1_state;
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reg [2:0] m1_state;
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reg [2:0] m1_next_state;
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reg [2:0] m1_next_state;
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reg [3:0] m2_state;
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reg [3:0] m2_state;
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reg [3:0] m2_next_state;
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reg [3:0] m2_next_state;
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reg m3_state;
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reg m3_state;
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reg m3_next_state;
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reg m3_next_state;
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reg [5:0] bit_count; // Bit counter
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reg [5:0] bit_count; // Bit counter
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reg [WATCHDOG_TIMER_BITS_PP-1:0] watchdog_timer_count;
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reg [WATCHDOG_TIMER_BITS_PP-1:0] watchdog_timer_count;
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reg [DEBOUNCE_TIMER_BITS_PP-1:0] debounce_timer_count;
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reg [DEBOUNCE_TIMER_BITS_PP-1:0] debounce_timer_count;
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reg ps2_clk_hi_z; // Without keyboard, high Z equals 1 due to pullups.
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reg ps2_clk_hi_z; // Without keyboard, high Z equals 1 due to pullups.
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reg ps2_data_hi_z; // Without keyboard, high Z equals 1 due to pullups.
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reg ps2_data_hi_z; // Without keyboard, high Z equals 1 due to pullups.
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reg clean_clk; // Debounced output from m1, follows ps2_clk.
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reg clean_clk; // Debounced output from m1, follows ps2_clk.
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reg rising_edge; // Output from m1 state machine.
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reg rising_edge; // Output from m1 state machine.
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reg falling_edge; // Output from m1 state machine.
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reg falling_edge; // Output from m1 state machine.
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reg output_strobe; // Latches data data into the output registers
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reg output_strobe; // Latches data data into the output registers
|
|
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//--------------------------------------------------------------------------
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//--------------------------------------------------------------------------
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// Module code
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// Module code
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|
|
assign ps2_clk = ps2_clk_hi_z?1'bZ:1'b0;
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assign ps2_clk = ps2_clk_hi_z?1'bZ:1'b0;
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assign ps2_data = ps2_data_hi_z?1'bZ:1'b0;
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assign ps2_data = ps2_data_hi_z?1'bZ:1'b0;
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|
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// State register
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// State register
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always @(posedge clk)
|
always @(posedge clk)
|
begin : m1_state_register
|
begin : m1_state_register
|
if (reset) m1_state <= m1_clk_h;
|
if (reset) m1_state <= m1_clk_h;
|
else m1_state <= m1_next_state;
|
else m1_state <= m1_next_state;
|
end
|
end
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|
|
// State transition logic
|
// State transition logic
|
always @(m1_state
|
always @(m1_state
|
or ps2_clk
|
or ps2_clk
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or debounce_timer_done
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or debounce_timer_done
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or watchdog_timer_done
|
or watchdog_timer_done
|
)
|
)
|
begin : m1_state_logic
|
begin : m1_state_logic
|
|
|
// Output signals default to this value, unless changed in a state condition.
|
// Output signals default to this value, unless changed in a state condition.
|
clean_clk <= 0;
|
clean_clk <= 0;
|
rising_edge <= 0;
|
rising_edge <= 0;
|
falling_edge <= 0;
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falling_edge <= 0;
|
|
|
case (m1_state)
|
case (m1_state)
|
m1_clk_h :
|
m1_clk_h :
|
begin
|
begin
|
clean_clk <= 1;
|
clean_clk <= 1;
|
if (~ps2_clk) m1_next_state <= m1_falling_edge;
|
if (~ps2_clk) m1_next_state <= m1_falling_edge;
|
else m1_next_state <= m1_clk_h;
|
else m1_next_state <= m1_clk_h;
|
end
|
end
|
|
|
m1_falling_edge :
|
m1_falling_edge :
|
begin
|
begin
|
falling_edge <= 1;
|
falling_edge <= 1;
|
m1_next_state <= m1_falling_wait;
|
m1_next_state <= m1_falling_wait;
|
end
|
end
|
|
|
m1_falling_wait :
|
m1_falling_wait :
|
begin
|
begin
|
if (debounce_timer_done) m1_next_state <= m1_clk_l;
|
if (debounce_timer_done) m1_next_state <= m1_clk_l;
|
else m1_next_state <= m1_falling_wait;
|
else m1_next_state <= m1_falling_wait;
|
end
|
end
|
|
|
m1_clk_l :
|
m1_clk_l :
|
begin
|
begin
|
if (ps2_clk) m1_next_state <= m1_rising_edge;
|
if (ps2_clk) m1_next_state <= m1_rising_edge;
|
else m1_next_state <= m1_clk_l;
|
else m1_next_state <= m1_clk_l;
|
end
|
end
|
|
|
m1_rising_edge :
|
m1_rising_edge :
|
begin
|
begin
|
rising_edge <= 1;
|
rising_edge <= 1;
|
m1_next_state <= m1_rising_wait;
|
m1_next_state <= m1_rising_wait;
|
end
|
end
|
|
|
m1_rising_wait :
|
m1_rising_wait :
|
begin
|
begin
|
clean_clk <= 1;
|
clean_clk <= 1;
|
if (debounce_timer_done) m1_next_state <= m1_clk_h;
|
if (debounce_timer_done) m1_next_state <= m1_clk_h;
|
else m1_next_state <= m1_rising_wait;
|
else m1_next_state <= m1_rising_wait;
|
end
|
end
|
default : m1_next_state <= m1_clk_h;
|
default : m1_next_state <= m1_clk_h;
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
// State register
|
// State register
|
always @(posedge clk)
|
always @(posedge clk)
|
begin : m2_state_register
|
begin : m2_state_register
|
if (reset) m2_state <= m2_reset;
|
if (reset) m2_state <= m2_reset;
|
else m2_state <= m2_next_state;
|
else m2_state <= m2_next_state;
|
end
|
end
|
|
|
// State transition logic
|
// State transition logic
|
always @(m2_state
|
always @(m2_state
|
or q
|
or q
|
or falling_edge
|
or falling_edge
|
or rising_edge
|
or rising_edge
|
or watchdog_timer_done
|
or watchdog_timer_done
|
or bit_count
|
or bit_count
|
or packet_good
|
or packet_good
|
or ps2_data
|
or ps2_data
|
or clean_clk
|
or clean_clk
|
)
|
)
|
begin : m2_state_logic
|
begin : m2_state_logic
|
|
|
// Output signals default to this value, unless changed in a state condition.
|
// Output signals default to this value, unless changed in a state condition.
|
ps2_clk_hi_z <= 1;
|
ps2_clk_hi_z <= 1;
|
ps2_data_hi_z <= 1;
|
ps2_data_hi_z <= 1;
|
error_no_ack <= 0;
|
error_no_ack <= 0;
|
output_strobe <= 0;
|
output_strobe <= 0;
|
|
|
case (m2_state)
|
case (m2_state)
|
|
|
m2_reset : // After reset, sends command to mouse.
|
m2_reset : // After reset, sends command to mouse.
|
begin
|
begin
|
m2_next_state <= m2_hold_clk_l;
|
m2_next_state <= m2_hold_clk_l;
|
end
|
end
|
|
|
m2_wait :
|
m2_wait :
|
begin
|
begin
|
if (falling_edge) m2_next_state <= m2_gather;
|
if (falling_edge) m2_next_state <= m2_gather;
|
else m2_next_state <= m2_wait;
|
else m2_next_state <= m2_wait;
|
end
|
end
|
|
|
m2_gather :
|
m2_gather :
|
begin
|
begin
|
if (watchdog_timer_done && (bit_count == `TOTAL_BITS))
|
if (watchdog_timer_done && (bit_count == `TOTAL_BITS))
|
m2_next_state <= m2_verify;
|
m2_next_state <= m2_verify;
|
else if (watchdog_timer_done && (bit_count < `TOTAL_BITS))
|
else if (watchdog_timer_done && (bit_count < `TOTAL_BITS))
|
m2_next_state <= m2_hold_clk_l;
|
m2_next_state <= m2_hold_clk_l;
|
else m2_next_state <= m2_gather;
|
else m2_next_state <= m2_gather;
|
end
|
end
|
|
|
m2_verify :
|
m2_verify :
|
begin
|
begin
|
if (packet_good) m2_next_state <= m2_use;
|
if (packet_good) m2_next_state <= m2_use;
|
else m2_next_state <= m2_wait;
|
else m2_next_state <= m2_wait;
|
end
|
end
|
|
|
m2_use :
|
m2_use :
|
begin
|
begin
|
output_strobe <= 1;
|
output_strobe <= 1;
|
m2_next_state <= m2_wait;
|
m2_next_state <= m2_wait;
|
end
|
end
|
|
|
// The following sequence of 9 states is designed to transmit the
|
// The following sequence of 9 states is designed to transmit the
|
// "enable streaming mode" command to the mouse, and then await the
|
// "enable streaming mode" command to the mouse, and then await the
|
// response from the mouse. Upon completion of this operation, the
|
// response from the mouse. Upon completion of this operation, the
|
// receive shift register contains 22 bits of data which are "invalid"
|
// receive shift register contains 22 bits of data which are "invalid"
|
// therefore, the m2_verify state will fail to validate the data, and
|
// therefore, the m2_verify state will fail to validate the data, and
|
// control will be passed into the m2_wait state once again (but the
|
// control will be passed into the m2_wait state once again (but the
|
// mouse will then be enabled, and valid data packets will ensue whenever
|
// mouse will then be enabled, and valid data packets will ensue whenever
|
// there is activity on the mouse.)
|
// there is activity on the mouse.)
|
m2_hold_clk_l :
|
m2_hold_clk_l :
|
begin
|
begin
|
ps2_clk_hi_z <= 0; // This starts the watchdog timer!
|
ps2_clk_hi_z <= 0; // This starts the watchdog timer!
|
if (watchdog_timer_done && ~clean_clk) m2_next_state <= m2_data_low_1;
|
if (watchdog_timer_done && ~clean_clk) m2_next_state <= m2_data_low_1;
|
else m2_next_state <= m2_hold_clk_l;
|
else m2_next_state <= m2_hold_clk_l;
|
end
|
end
|
|
|
m2_data_low_1 :
|
m2_data_low_1 :
|
begin
|
begin
|
ps2_data_hi_z <= 0; // Forms start bit, d[0] and d[1]
|
ps2_data_hi_z <= 0; // Forms start bit, d[0] and d[1]
|
if (rising_edge && (bit_count == 3))
|
if (rising_edge && (bit_count == 3))
|
m2_next_state <= m2_data_high_1;
|
m2_next_state <= m2_data_high_1;
|
else m2_next_state <= m2_data_low_1;
|
else m2_next_state <= m2_data_low_1;
|
end
|
end
|
|
|
m2_data_high_1 :
|
m2_data_high_1 :
|
begin
|
begin
|
ps2_data_hi_z <= 1; // Forms d[2]
|
ps2_data_hi_z <= 1; // Forms d[2]
|
if (rising_edge && (bit_count == 4))
|
if (rising_edge && (bit_count == 4))
|
m2_next_state <= m2_data_low_2;
|
m2_next_state <= m2_data_low_2;
|
else m2_next_state <= m2_data_high_1;
|
else m2_next_state <= m2_data_high_1;
|
end
|
end
|
|
|
m2_data_low_2 :
|
m2_data_low_2 :
|
begin
|
begin
|
ps2_data_hi_z <= 0; // Forms d[3]
|
ps2_data_hi_z <= 0; // Forms d[3]
|
if (rising_edge && (bit_count == 5))
|
if (rising_edge && (bit_count == 5))
|
m2_next_state <= m2_data_high_2;
|
m2_next_state <= m2_data_high_2;
|
else m2_next_state <= m2_data_low_2;
|
else m2_next_state <= m2_data_low_2;
|
end
|
end
|
|
|
m2_data_high_2 :
|
m2_data_high_2 :
|
begin
|
begin
|
ps2_data_hi_z <= 1; // Forms d[4],d[5],d[6],d[7]
|
ps2_data_hi_z <= 1; // Forms d[4],d[5],d[6],d[7]
|
if (rising_edge && (bit_count == 9))
|
if (rising_edge && (bit_count == 9))
|
m2_next_state <= m2_data_low_3;
|
m2_next_state <= m2_data_low_3;
|
else m2_next_state <= m2_data_high_2;
|
else m2_next_state <= m2_data_high_2;
|
end
|
end
|
|
|
m2_data_low_3 :
|
m2_data_low_3 :
|
begin
|
begin
|
ps2_data_hi_z <= 0; // Forms parity bit
|
ps2_data_hi_z <= 0; // Forms parity bit
|
if (rising_edge) m2_next_state <= m2_data_high_3;
|
if (rising_edge) m2_next_state <= m2_data_high_3;
|
else m2_next_state <= m2_data_low_3;
|
else m2_next_state <= m2_data_low_3;
|
end
|
end
|
|
|
m2_data_high_3 :
|
m2_data_high_3 :
|
begin
|
begin
|
ps2_data_hi_z <= 1; // Allow mouse to pull low (ack pulse)
|
ps2_data_hi_z <= 1; // Allow mouse to pull low (ack pulse)
|
if (falling_edge && ps2_data) m2_next_state <= m2_error_no_ack;
|
if (falling_edge && ps2_data) m2_next_state <= m2_error_no_ack;
|
else if (falling_edge && ~ps2_data)
|
else if (falling_edge && ~ps2_data)
|
m2_next_state <= m2_await_response;
|
m2_next_state <= m2_await_response;
|
else m2_next_state <= m2_data_high_3;
|
else m2_next_state <= m2_data_high_3;
|
end
|
end
|
|
|
m2_error_no_ack :
|
m2_error_no_ack :
|
begin
|
begin
|
error_no_ack <= 1;
|
error_no_ack <= 1;
|
m2_next_state <= m2_error_no_ack;
|
m2_next_state <= m2_error_no_ack;
|
end
|
end
|
|
|
// In order to "cleanly" exit the setting of the mouse into "streaming"
|
// In order to "cleanly" exit the setting of the mouse into "streaming"
|
// data mode, the state machine should wait for a long enough time to
|
// data mode, the state machine should wait for a long enough time to
|
// ensure the FA response is done being sent by the mouse. Unfortunately,
|
// ensure the FA response is done being sent by the mouse. Unfortunately,
|
// this is tough to figure out, since the watchdog timeout might be longer
|
// this is tough to figure out, since the watchdog timeout might be longer
|
// or shorter depending upon the user. If the watchdog timeout is set to
|
// or shorter depending upon the user. If the watchdog timeout is set to
|
// a small enough value (less than about 560 usec?) then the bit_count
|
// a small enough value (less than about 560 usec?) then the bit_count
|
// will get reset to zero by the watchdog before the FA response is
|
// will get reset to zero by the watchdog before the FA response is
|
// received. In that case, bit_count will be 11.
|
// received. In that case, bit_count will be 11.
|
// If the bit_count is not reset by the watchdog, then the
|
// If the bit_count is not reset by the watchdog, then the
|
// total bit_count will be 22.
|
// total bit_count will be 22.
|
// In either case, when this state is reached, the watchdog timer is still
|
// In either case, when this state is reached, the watchdog timer is still
|
// running and it is best to let it expire before returning to normal
|
// running and it is best to let it expire before returning to normal
|
// operation. One easy way to do this is to check for the bit_count to
|
// operation. One easy way to do this is to check for the bit_count to
|
// reach 22 (which it will always do when receiving a normal packet) and
|
// reach 22 (which it will always do when receiving a normal packet) and
|
// then jump to "verify" which will always fail for that time.
|
// then jump to "verify" which will always fail for that time.
|
m2_await_response :
|
m2_await_response :
|
begin
|
begin
|
if (bit_count == 22) m2_next_state <= m2_verify;
|
if (bit_count == 22) m2_next_state <= m2_verify;
|
else m2_next_state <= m2_await_response;
|
else m2_next_state <= m2_await_response;
|
end
|
end
|
|
|
default : m2_next_state <= m2_wait;
|
default : m2_next_state <= m2_wait;
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
|
|
// State register
|
// State register
|
always @(posedge clk)
|
always @(posedge clk)
|
begin : m3_state_register
|
begin : m3_state_register
|
if (reset) m3_state <= m3_data_ready_ack;
|
if (reset) m3_state <= m3_data_ready_ack;
|
else m3_state <= m3_next_state;
|
else m3_state <= m3_next_state;
|
end
|
end
|
|
|
// State transition logic
|
// State transition logic
|
always @(m3_state or output_strobe or read)
|
always @(m3_state or output_strobe or read)
|
begin : m3_state_logic
|
begin : m3_state_logic
|
case (m3_state)
|
case (m3_state)
|
m3_data_ready_ack:
|
m3_data_ready_ack:
|
begin
|
begin
|
data_ready <= 1'b0;
|
data_ready <= 1'b0;
|
if (output_strobe) m3_next_state <= m3_data_ready;
|
if (output_strobe) m3_next_state <= m3_data_ready;
|
else m3_next_state <= m3_data_ready_ack;
|
else m3_next_state <= m3_data_ready_ack;
|
end
|
end
|
m3_data_ready:
|
m3_data_ready:
|
begin
|
begin
|
data_ready <= 1'b1;
|
data_ready <= 1'b1;
|
if (read) m3_next_state <= m3_data_ready_ack;
|
if (read) m3_next_state <= m3_data_ready_ack;
|
else m3_next_state <= m3_data_ready;
|
else m3_next_state <= m3_data_ready;
|
end
|
end
|
default : m3_next_state <= m3_data_ready_ack;
|
default : m3_next_state <= m3_data_ready_ack;
|
endcase
|
endcase
|
end
|
end
|
|
|
// This is the bit counter
|
// This is the bit counter
|
always @(posedge clk)
|
always @(posedge clk)
|
begin
|
begin
|
if (reset) bit_count <= 0; // normal reset
|
if (reset) bit_count <= 0; // normal reset
|
else if (falling_edge) bit_count <= bit_count + 1;
|
else if (falling_edge) bit_count <= bit_count + 1;
|
else if (watchdog_timer_done) bit_count <= 0; // rx watchdog timer reset
|
else if (watchdog_timer_done) bit_count <= 0; // rx watchdog timer reset
|
end
|
end
|
|
|
// This is the shift register
|
// This is the shift register
|
always @(posedge clk)
|
always @(posedge clk)
|
begin
|
begin
|
if (reset) q <= 0;
|
if (reset) q <= 0;
|
else if (falling_edge) q <= {ps2_data,q[`TOTAL_BITS-1:1]};
|
else if (falling_edge) q <= {ps2_data,q[`TOTAL_BITS-1:1]};
|
end
|
end
|
|
|
// This is the watchdog timer counter
|
// This is the watchdog timer counter
|
// The watchdog timer is always "enabled" to operate.
|
// The watchdog timer is always "enabled" to operate.
|
always @(posedge clk)
|
always @(posedge clk)
|
begin
|
begin
|
if (reset || rising_edge || falling_edge) watchdog_timer_count <= 0;
|
if (reset || rising_edge || falling_edge) watchdog_timer_count <= 0;
|
else if (~watchdog_timer_done)
|
else if (~watchdog_timer_done)
|
watchdog_timer_count <= watchdog_timer_count + 1;
|
watchdog_timer_count <= watchdog_timer_count + 1;
|
end
|
end
|
assign watchdog_timer_done = (watchdog_timer_count==WATCHDOG_TIMER_VALUE_PP-1);
|
assign watchdog_timer_done = (watchdog_timer_count==WATCHDOG_TIMER_VALUE_PP-1);
|
|
|
// This is the debounce timer counter
|
// This is the debounce timer counter
|
always @(posedge clk)
|
always @(posedge clk)
|
begin
|
begin
|
if (reset || falling_edge || rising_edge) debounce_timer_count <= 0;
|
if (reset || falling_edge || rising_edge) debounce_timer_count <= 0;
|
// else if (~debounce_timer_done)
|
// else if (~debounce_timer_done)
|
else debounce_timer_count <= debounce_timer_count + 1;
|
else debounce_timer_count <= debounce_timer_count + 1;
|
end
|
end
|
assign debounce_timer_done = (debounce_timer_count==DEBOUNCE_TIMER_VALUE_PP-1);
|
assign debounce_timer_done = (debounce_timer_count==DEBOUNCE_TIMER_VALUE_PP-1);
|
|
|
// This is the logic to verify that a received data packet is "valid"
|
// This is the logic to verify that a received data packet is "valid"
|
// or good.
|
// or good.
|
assign packet_good = (
|
assign packet_good = (
|
(q[0] == 0)
|
(q[0] == 0)
|
&& (q[10] == 1)
|
&& (q[10] == 1)
|
&& (q[11] == 0)
|
&& (q[11] == 0)
|
&& (q[21] == 1)
|
&& (q[21] == 1)
|
&& (q[22] == 0)
|
&& (q[22] == 0)
|
&& (q[32] == 1)
|
&& (q[32] == 1)
|
&& (q[9] == ~^q[8:1]) // odd parity bit
|
&& (q[9] == ~^q[8:1]) // odd parity bit
|
&& (q[20] == ~^q[19:12]) // odd parity bit
|
&& (q[20] == ~^q[19:12]) // odd parity bit
|
&& (q[31] == ~^q[30:23]) // odd parity bit
|
&& (q[31] == ~^q[30:23]) // odd parity bit
|
);
|
);
|
|
|
// Output the special scan code flags, the scan code and the ascii
|
// Output the special scan code flags, the scan code and the ascii
|
always @(posedge clk)
|
always @(posedge clk)
|
begin
|
begin
|
if (reset)
|
if (reset)
|
begin
|
begin
|
left_button <= 0;
|
left_button <= 0;
|
right_button <= 0;
|
right_button <= 0;
|
x_increment <= 0;
|
x_increment <= 0;
|
y_increment <= 0;
|
y_increment <= 0;
|
end
|
end
|
else if (output_strobe)
|
else if (output_strobe)
|
begin
|
begin
|
left_button <= q[1];
|
left_button <= q[1];
|
right_button <= q[2];
|
right_button <= q[2];
|
x_increment <= {q[5],q[19:12]};
|
x_increment <= {q[5],q[19:12]};
|
y_increment <= {q[6],q[30:23]};
|
y_increment <= {q[6],q[30:23]};
|
end
|
end
|
end
|
end
|
|
|
|
|
endmodule
|
endmodule
|
|
|
//`undefine TOTAL_BITS
|
//`undefine TOTAL_BITS
|
|
|
|
|