/*
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/*
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PSS
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PSS
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Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru>
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Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru>
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All rights reserved.
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All rights reserved.
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Version 0.99
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Version 0.99
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The FreeBSD license
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The FreeBSD license
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Redistribution and use in source and binary forms, with or without
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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modification, are permitted provided that the following conditions
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are met:
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are met:
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1. Redistributions of source code must retain the above copyright
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above
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2. Redistributions in binary form must reproduce the above
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copyright notice, this list of conditions and the following
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copyright notice, this list of conditions and the following
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disclaimer in the documentation and/or other materials
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disclaimer in the documentation and/or other materials
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provided with the distribution.
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provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
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THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
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EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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PSS PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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PSS PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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module pss
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module pss
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#(
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#(
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parameter CPU_PRESENT = 1,
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parameter CPU_PRESENT = 1,
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parameter CPU_RESET_DEFAULT = 1,
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parameter CPU_RESET_DEFAULT = 1,
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parameter EXT_RESET_DEFAULT = 1,
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parameter A31_DEFAULT = 1,
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parameter A31_DEFAULT = 1,
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parameter MEM_SIZE_KB = 1,
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parameter MEM_SIZE_KB = 1,
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parameter MEM_DATA = ""
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parameter MEM_DATA = ""
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)
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)
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(
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(
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input clk_i,
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input clk_i,
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input arst_i, srst_i,
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input arst_i, srst_i,
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output srst_o, ext_rst_o,
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output srst_o, ext_rst_o,
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input rx_i,
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input rx_i,
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output tx_o,
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output tx_o,
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input [3:0] INT_bi,
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input [3:0] INT_bi,
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// Expansion bus
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// Expansion bus
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output xport_req_o,
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output xport_req_o,
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input xport_ack_i,
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input xport_ack_i,
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input xport_err_i,
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input xport_err_i,
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output xport_we_o,
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output xport_we_o,
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output [31:0] xport_addr_bo,
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output [31:0] xport_addr_bo,
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output [31:0] xport_wdata_bo,
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output [31:0] xport_wdata_bo,
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input xport_resp_i,
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input xport_resp_i,
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input [31:0] xport_rdata_bi
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input [31:0] xport_rdata_bi
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);
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);
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wire zpu_uc_srst, udm_rst;
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wire zpu_uc_srst, udm_rst;
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assign zpu_uc_srst = srst_i | udm_rst;
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assign zpu_uc_srst = srst_i | udm_rst;
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wire dbg_bus_enb;
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wire dbg_bus_enb;
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wire dbg_bus_we;
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wire dbg_bus_we;
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wire [31:0] dbg_bus_addr;
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wire [31:0] dbg_bus_addr;
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wire [31:0] dbg_bus_wdata;
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wire [31:0] dbg_bus_wdata;
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wire [31:0] dbg_bus_rdata;
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wire [31:0] dbg_bus_rdata;
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wire dbg_bus_resp;
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wire dbg_bus_resp;
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udm udm
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udm udm
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(
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(
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.clk_i(clk_i),
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.clk_i(clk_i),
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.rst_i(srst_o),
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.rst_i(srst_o),
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.rx_i(rx_i),
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.rx_i(rx_i),
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.tx_o(tx_o),
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.tx_o(tx_o),
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.rst_o(udm_rst),
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.rst_o(udm_rst),
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.bus_enb_o(dbg_bus_enb),
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.bus_enb_o(dbg_bus_enb),
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.bus_we_o(dbg_bus_we),
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.bus_we_o(dbg_bus_we),
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.bus_addr_bo(dbg_bus_addr),
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.bus_addr_bo(dbg_bus_addr),
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.bus_wdata_bo(dbg_bus_wdata),
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.bus_wdata_bo(dbg_bus_wdata),
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.bus_ack_i(dbg_bus_resp),
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.bus_ack_i(dbg_bus_resp),
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.bus_rdata_bi(dbg_bus_rdata)
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.bus_rdata_bi(dbg_bus_rdata)
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);
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);
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ZPU_uC
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ZPU_uC
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#(
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#(
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.CPU_PRESENT(CPU_PRESENT),
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.CPU_PRESENT(CPU_PRESENT),
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.CPU_RESET_DEFAULT(CPU_RESET_DEFAULT),
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.CPU_RESET_DEFAULT(CPU_RESET_DEFAULT),
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.EXT_RESET_DEFAULT(EXT_RESET_DEFAULT),
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.A31_DEFAULT(A31_DEFAULT),
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.A31_DEFAULT(A31_DEFAULT),
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.MEM_DATA(MEM_DATA),
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.MEM_DATA(MEM_DATA),
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.MEM_SIZE_KB(MEM_SIZE_KB)
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.MEM_SIZE_KB(MEM_SIZE_KB)
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)
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)
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ZPU_uC
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ZPU_uC
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(
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(
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.clk_i(clk_i),
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.clk_i(clk_i),
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.arst_i(arst_i),
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.arst_i(arst_i),
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.srst_o(srst_o),
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.srst_o(srst_o),
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.srst_i(zpu_uc_srst),
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.srst_i(zpu_uc_srst),
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.ext_rst_o(ext_rst_o),
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.ext_rst_o(ext_rst_o),
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.INT_bi(INT_bi),
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.INT_bi(INT_bi),
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// Expansion bus
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// Expansion bus
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.xport_req_o(xport_req_o),
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.xport_req_o(xport_req_o),
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.xport_ack_i(xport_ack_i),
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.xport_ack_i(xport_ack_i),
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.xport_err_i(xport_err_i),
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.xport_err_i(xport_err_i),
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.xport_we_o(xport_we_o),
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.xport_we_o(xport_we_o),
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.xport_addr_bo(xport_addr_bo),
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.xport_addr_bo(xport_addr_bo),
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.xport_wdata_bo(xport_wdata_bo),
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.xport_wdata_bo(xport_wdata_bo),
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.xport_resp_i(xport_resp_i),
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.xport_resp_i(xport_resp_i),
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.xport_rdata_bi(xport_rdata_bi),
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.xport_rdata_bi(xport_rdata_bi),
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//Debug interface
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//Debug interface
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.dbg_enb_i(dbg_bus_enb),
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.dbg_enb_i(dbg_bus_enb),
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.dbg_wr_i(dbg_bus_we),
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.dbg_wr_i(dbg_bus_we),
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.dbg_addr_bi(dbg_bus_addr),
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.dbg_addr_bi(dbg_bus_addr),
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.dbg_data_bi(dbg_bus_wdata),
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.dbg_data_bi(dbg_bus_wdata),
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.dbg_resp_o(dbg_bus_resp),
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.dbg_resp_o(dbg_bus_resp),
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.dbg_data_bo(dbg_bus_rdata)
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.dbg_data_bo(dbg_bus_rdata)
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);
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);
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endmodule
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endmodule
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