/*
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/*
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PSS
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PSS
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Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru>
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Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru>
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All rights reserved.
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All rights reserved.
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Version 0.9
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Version 0.99
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The FreeBSD license
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The FreeBSD license
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Redistribution and use in source and binary forms, with or without
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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modification, are permitted provided that the following conditions
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are met:
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are met:
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1. Redistributions of source code must retain the above copyright
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above
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2. Redistributions in binary form must reproduce the above
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copyright notice, this list of conditions and the following
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copyright notice, this list of conditions and the following
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disclaimer in the documentation and/or other materials
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disclaimer in the documentation and/or other materials
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provided with the distribution.
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provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
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THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
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EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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PSS PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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PSS PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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module uart_tx
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module uart_tx
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(
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(
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input clk_i, rst_i,
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input clk_i, rst_i,
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input tx_start_i,
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input tx_start_i,
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input [7:0] din_bi,
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input [7:0] din_bi,
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input locked_i,
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input locked_i,
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input [28:0] bitperiod_i,
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input [28:0] bitperiod_i,
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output reg tx_done_tick_o,
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output reg tx_done_tick_o,
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output reg tx_o
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output reg tx_o
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);
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);
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reg [7:0] databuf;
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reg [7:0] databuf;
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reg [3:0] state;
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reg [3:0] state;
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reg [31:0] clk_counter;
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reg [31:0] clk_counter;
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reg [2:0] bit_counter;
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reg [2:0] bit_counter;
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localparam ST_IDLE = 8'h0;
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localparam ST_IDLE = 8'h0;
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localparam ST_START = 8'h1;
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localparam ST_START = 8'h1;
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localparam ST_TX_DATA = 8'h2;
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localparam ST_TX_DATA = 8'h2;
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localparam ST_STOP = 8'h3;
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localparam ST_STOP = 8'h3;
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always @(posedge clk_i)
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always @(posedge clk_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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begin
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begin
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state <= ST_IDLE;
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state <= ST_IDLE;
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databuf <= 8'h0;
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databuf <= 8'h0;
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clk_counter <= 32'h0;
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clk_counter <= 32'h0;
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tx_o <= 1'b1;
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tx_o <= 1'b1;
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tx_done_tick_o <= 1'b0;
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tx_done_tick_o <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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tx_done_tick_o <= 1'b0;
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tx_done_tick_o <= 1'b0;
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case (state)
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case (state)
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ST_IDLE:
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ST_IDLE:
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begin
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begin
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tx_o <= 1'b1;
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tx_o <= 1'b1;
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if ((tx_start_i == 1'b1) && (locked_i == 1'b1))
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if ((tx_start_i == 1'b1) && (locked_i == 1'b1))
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begin
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begin
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tx_o <= 1'b0;
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tx_o <= 1'b0;
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state <= ST_START;
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state <= ST_START;
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databuf <= din_bi;
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databuf <= din_bi;
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clk_counter <= 32'h0;
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clk_counter <= 32'h0;
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end
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end
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end
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end
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ST_START:
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ST_START:
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begin
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begin
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clk_counter <= clk_counter + 32'h1;
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clk_counter <= clk_counter + 32'h1;
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if (clk_counter == {3'h0, bitperiod_i})
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if (clk_counter == {3'h0, bitperiod_i})
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begin
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begin
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state <= ST_TX_DATA;
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state <= ST_TX_DATA;
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clk_counter <= 32'h0;
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clk_counter <= 32'h0;
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bit_counter <= 3'h0;
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bit_counter <= 3'h0;
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tx_o <= databuf[0];
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tx_o <= databuf[0];
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databuf <= {1'b0, databuf[7:1]};
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databuf <= {1'b0, databuf[7:1]};
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end
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end
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end
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end
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ST_TX_DATA:
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ST_TX_DATA:
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begin
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begin
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clk_counter <= clk_counter + 32'h1;
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clk_counter <= clk_counter + 32'h1;
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if (clk_counter == {3'h0, bitperiod_i})
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if (clk_counter == {3'h0, bitperiod_i})
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begin
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begin
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clk_counter <= 32'h0;
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clk_counter <= 32'h0;
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bit_counter <= bit_counter + 3'h1;
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bit_counter <= bit_counter + 3'h1;
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if (bit_counter == 3'h7)
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if (bit_counter == 3'h7)
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begin
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begin
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tx_o <= 1'b1;
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tx_o <= 1'b1;
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state <= ST_STOP;
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state <= ST_STOP;
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end
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end
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else
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else
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begin
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begin
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tx_o <= databuf[0];
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tx_o <= databuf[0];
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databuf <= {1'b0, databuf[7:1]};
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databuf <= {1'b0, databuf[7:1]};
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end
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end
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end
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end
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end
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end
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ST_STOP:
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ST_STOP:
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begin
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begin
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clk_counter <= clk_counter + 32'h1;
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clk_counter <= clk_counter + 32'h1;
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if (clk_counter == {2'h0, bitperiod_i, 1'b0}) // 2 * bit
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if (clk_counter == {2'h0, bitperiod_i, 1'b0}) // 2 * bit
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begin
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begin
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tx_o <= 1'b1;
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tx_o <= 1'b1;
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tx_done_tick_o <= 1'b1;
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tx_done_tick_o <= 1'b1;
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state <= ST_IDLE;
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state <= ST_IDLE;
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end
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end
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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endmodule
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endmodule
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