/*
|
/*
|
PSS
|
PSS
|
|
|
Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru>
|
Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru>
|
All rights reserved.
|
All rights reserved.
|
|
|
Version 0.9.0
|
Version 0.9.0
|
|
|
The FreeBSD license
|
The FreeBSD license
|
|
|
Redistribution and use in source and binary forms, with or without
|
Redistribution and use in source and binary forms, with or without
|
modification, are permitted provided that the following conditions
|
modification, are permitted provided that the following conditions
|
are met:
|
are met:
|
|
|
1. Redistributions of source code must retain the above copyright
|
1. Redistributions of source code must retain the above copyright
|
notice, this list of conditions and the following disclaimer.
|
notice, this list of conditions and the following disclaimer.
|
2. Redistributions in binary form must reproduce the above
|
2. Redistributions in binary form must reproduce the above
|
copyright notice, this list of conditions and the following
|
copyright notice, this list of conditions and the following
|
disclaimer in the documentation and/or other materials
|
disclaimer in the documentation and/or other materials
|
provided with the distribution.
|
provided with the distribution.
|
|
|
THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
|
THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
|
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
|
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
|
PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
PSS PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
PSS PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
*/
|
*/
|
|
|
|
|
module PSS_BusBridge
|
module PSS_BusBridge
|
(
|
(
|
input clk_i, rst_i,
|
input clk_i, rst_i,
|
|
|
input xport_busy_i,
|
input xport_busy_i,
|
output xport_busy_o,
|
output xport_busy_o,
|
|
|
input a31_i,
|
input a31_i,
|
|
|
//// Masters ////
|
//// Masters ////
|
// Debug bus //
|
// Debug bus //
|
input bus_enb_i,
|
input bus_enb_i,
|
input bus_we_i,
|
input bus_we_i,
|
input [31:0] bus_addr_bi,
|
input [31:0] bus_addr_bi,
|
input [31:0] bus_wdata_bi,
|
input [31:0] bus_wdata_bi,
|
input [3:0] bus_writemask_bi,
|
input [3:0] bus_writemask_bi,
|
output reg bus_ack_o,
|
output reg bus_ack_o,
|
output reg [31:0] bus_rdata_bo,
|
output reg [31:0] bus_rdata_bo,
|
|
|
// Expansion bus //
|
// Expansion bus //
|
output reg xport_req_o,
|
output reg xport_req_o,
|
input xport_ack_i,
|
input xport_ack_i,
|
input xport_err_i,
|
input xport_err_i,
|
output reg xport_we_o,
|
output reg xport_we_o,
|
output reg [31:0] xport_addr_bo,
|
output reg [31:0] xport_addr_bo,
|
output reg [31:0] xport_wdata_bo,
|
output reg [31:0] xport_wdata_bo,
|
output reg [3:0] xport_writemask_bo,
|
output reg [3:0] xport_writemask_bo,
|
input xport_resp_i,
|
input xport_resp_i,
|
input [31:0] xport_rdata_bi
|
input [31:0] xport_rdata_bi
|
);
|
);
|
|
|
localparam ST_IDLE = 2'h0;
|
localparam ST_IDLE = 2'h0;
|
localparam ST_WR_WAIT_ACK = 2'h1;
|
localparam ST_WR_WAIT_ACK = 2'h1;
|
localparam ST_RD_WAIT_ACK = 2'h2;
|
localparam ST_RD_WAIT_ACK = 2'h2;
|
localparam ST_RD_WAIT_RESP = 2'h3;
|
localparam ST_RD_WAIT_RESP = 2'h3;
|
|
|
reg [1:0] bb_state;
|
reg [1:0] bb_state;
|
|
|
assign xport_busy_o = bus_enb_i;
|
assign xport_busy_o = bus_enb_i;
|
|
|
assign rdata_bo = xport_rdata_bi;
|
assign rdata_bo = xport_rdata_bi;
|
|
|
always @(posedge clk_i)
|
always @(posedge clk_i)
|
begin
|
begin
|
if (rst_i)
|
if (rst_i)
|
begin
|
begin
|
bb_state <= ST_IDLE;
|
bb_state <= ST_IDLE;
|
|
|
bus_ack_o <= 1'b0;
|
bus_ack_o <= 1'b0;
|
bus_rdata_bo <= 32'hx;
|
bus_rdata_bo <= 32'hx;
|
|
|
xport_req_o <= 1'b0;
|
xport_req_o <= 1'b0;
|
xport_we_o <= 1'b0;
|
xport_we_o <= 1'b0;
|
xport_addr_bo <= 32'hx;
|
xport_addr_bo <= 32'hx;
|
xport_wdata_bo <= 32'hx;
|
xport_wdata_bo <= 32'hx;
|
xport_writemask_bo <= 4'hx;
|
xport_writemask_bo <= 4'hx;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
|
|
bus_ack_o <= 1'b0;
|
bus_ack_o <= 1'b0;
|
bus_rdata_bo <= 32'hx;
|
bus_rdata_bo <= 32'hx;
|
|
|
case (bb_state)
|
case (bb_state)
|
|
|
ST_IDLE:
|
ST_IDLE:
|
begin
|
begin
|
if ((bus_enb_i == 1'b1) && (bus_ack_o == 1'b0))
|
if ((bus_enb_i == 1'b1) && (bus_ack_o == 1'b0))
|
begin
|
begin
|
if (bus_we_i == 1'b1)
|
if (bus_we_i == 1'b1)
|
begin
|
begin
|
xport_req_o <= 1'b1;
|
xport_req_o <= 1'b1;
|
xport_we_o <= 1'b1;
|
xport_we_o <= 1'b1;
|
xport_addr_bo <= bus_addr_bi;
|
xport_addr_bo <= {a31_i, bus_addr_bi[30:0]};
|
xport_wdata_bo <= bus_wdata_bi;
|
xport_wdata_bo <= bus_wdata_bi;
|
xport_writemask_bo <= bus_writemask_bi;
|
xport_writemask_bo <= bus_writemask_bi;
|
bb_state <= ST_WR_WAIT_ACK;
|
bb_state <= ST_WR_WAIT_ACK;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
xport_req_o <= 1'b1;
|
xport_req_o <= 1'b1;
|
xport_we_o <= 1'b0;
|
xport_we_o <= 1'b0;
|
xport_addr_bo <= bus_addr_bi;
|
xport_addr_bo <= {a31_i, bus_addr_bi[30:0]};
|
xport_wdata_bo <= bus_wdata_bi;
|
xport_wdata_bo <= bus_wdata_bi;
|
xport_writemask_bo <= bus_writemask_bi;
|
xport_writemask_bo <= bus_writemask_bi;
|
bb_state <= ST_RD_WAIT_ACK;
|
bb_state <= ST_RD_WAIT_ACK;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
ST_WR_WAIT_ACK:
|
ST_WR_WAIT_ACK:
|
begin
|
begin
|
if (xport_ack_i == 1'b1)
|
if (xport_ack_i == 1'b1)
|
begin
|
begin
|
xport_req_o <= 1'b0;
|
xport_req_o <= 1'b0;
|
xport_we_o <= 1'b0;
|
xport_we_o <= 1'b0;
|
xport_addr_bo <= 32'hx;
|
xport_addr_bo <= 32'hx;
|
xport_wdata_bo <= 32'hx;
|
xport_wdata_bo <= 32'hx;
|
xport_writemask_bo <= 4'hx;
|
xport_writemask_bo <= 4'hx;
|
|
|
bus_ack_o <= 1'b1;
|
bus_ack_o <= 1'b1;
|
|
|
bb_state <= ST_IDLE;
|
bb_state <= ST_IDLE;
|
end
|
end
|
end
|
end
|
|
|
ST_RD_WAIT_ACK:
|
ST_RD_WAIT_ACK:
|
begin
|
begin
|
if (xport_ack_i == 1'b1)
|
if (xport_ack_i == 1'b1)
|
begin
|
begin
|
xport_req_o <= 1'b0;
|
xport_req_o <= 1'b0;
|
xport_we_o <= 1'b0;
|
xport_we_o <= 1'b0;
|
xport_addr_bo <= 32'hx;
|
xport_addr_bo <= 32'hx;
|
xport_wdata_bo <= 32'hx;
|
xport_wdata_bo <= 32'hx;
|
xport_writemask_bo <= 4'hx;
|
xport_writemask_bo <= 4'hx;
|
|
|
bb_state <= ST_RD_WAIT_RESP;
|
bb_state <= ST_RD_WAIT_RESP;
|
end
|
end
|
end
|
end
|
|
|
ST_RD_WAIT_RESP:
|
ST_RD_WAIT_RESP:
|
begin
|
begin
|
if (xport_resp_i == 1'b1)
|
if (xport_resp_i == 1'b1)
|
begin
|
begin
|
bus_ack_o <= 1'b1;
|
bus_ack_o <= 1'b1;
|
bus_rdata_bo <= xport_rdata_bi;
|
bus_rdata_bo <= xport_rdata_bi;
|
|
|
bb_state <= ST_IDLE;
|
bb_state <= ST_IDLE;
|
end
|
end
|
end
|
end
|
|
|
endcase
|
endcase
|
|
|
end
|
end
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
