/*
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/*
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PSS
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PSS
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Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru>
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Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru>
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All rights reserved.
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All rights reserved.
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Version 0.9.0
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Version 0.9.0
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The FreeBSD license
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The FreeBSD license
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Redistribution and use in source and binary forms, with or without
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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modification, are permitted provided that the following conditions
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are met:
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are met:
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1. Redistributions of source code must retain the above copyright
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above
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2. Redistributions in binary form must reproduce the above
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copyright notice, this list of conditions and the following
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copyright notice, this list of conditions and the following
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disclaimer in the documentation and/or other materials
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disclaimer in the documentation and/or other materials
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provided with the distribution.
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provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
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THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
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EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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PSS PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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PSS PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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module PSS_MotherBlock
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module PSS_MotherBlock
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#(
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#(
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parameter A31_DEFAULT = 1,
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parameter A31_DEFAULT = 1,
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parameter CPU_RESET_DEFAULT = 1,
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parameter CPU_RESET_DEFAULT = 1,
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parameter EXT_RESET_DEFAULT = 1,
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parameter MEM_SIZE_KB = 1
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parameter MEM_SIZE_KB = 1
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)
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)
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(
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(
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input clk_i,
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input clk_i,
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input arst_i,
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input arst_i,
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output srst_o,
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output srst_o,
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input srst_i,
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input srst_i,
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output ext_rst_o,
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output ext_rst_o,
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input [3:0] INT_bi,
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input [3:0] INT_bi,
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output cpu_ireq_o,
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output cpu_ireq_o,
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input cpu_iack_i,
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input cpu_iack_i,
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|
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//// Masters ////
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//// Masters ////
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// Debug bus //
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// Debug bus //
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input dbg_enb_i,
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input dbg_enb_i,
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input dbg_we_i,
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input dbg_we_i,
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input [31:0] dbg_addr_bi,
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input [31:0] dbg_addr_bi,
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input [31:0] dbg_wdata_bi,
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input [31:0] dbg_wdata_bi,
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output dbg_ack_o,
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output dbg_ack_o,
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output [31:0] dbg_rdata_bo,
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output [31:0] dbg_rdata_bo,
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// ZPU bus //
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// ZPU bus //
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input cpu_enb_i,
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input cpu_enb_i,
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input cpu_we_i,
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input cpu_we_i,
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input [31:0] cpu_wdata_bi,
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input [31:0] cpu_wdata_bi,
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input [31:0] cpu_addr_bi,
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input [31:0] cpu_addr_bi,
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input [3:0] cpu_writemask_bi,
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input [3:0] cpu_writemask_bi,
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output cpu_ack_o,
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output cpu_ack_o,
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output [31:0] cpu_rdata_bo,
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output [31:0] cpu_rdata_bo,
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//// Slaves ////
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//// Slaves ////
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// RAM0 bus //
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// RAM0 bus //
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output [31:0] ram0_addr_bo,
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output [31:0] ram0_addr_bo,
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output ram0_we_o,
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output ram0_we_o,
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output [31:0] ram0_wdata_bo,
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output [31:0] ram0_wdata_bo,
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input [31:0] ram0_rdata_bi,
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input [31:0] ram0_rdata_bi,
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// RAM1 bus //
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// RAM1 bus //
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output [31:0] ram1_addr_bo,
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output [31:0] ram1_addr_bo,
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output ram1_we_o,
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output ram1_we_o,
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output [31:0] ram1_wdata_bo,
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output [31:0] ram1_wdata_bo,
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input [31:0] ram1_rdata_bi,
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input [31:0] ram1_rdata_bi,
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// Expansion bus //
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// Expansion bus //
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output reg xport_req_o,
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output reg xport_req_o,
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input xport_ack_i,
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input xport_ack_i,
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input xport_err_i,
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input xport_err_i,
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output reg xport_we_o,
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output reg xport_we_o,
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output reg [31:0] xport_addr_bo,
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output reg [31:0] xport_addr_bo,
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output reg [31:0] xport_wdata_bo,
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output reg [31:0] xport_wdata_bo,
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input xport_resp_i,
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input xport_resp_i,
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input [31:0] xport_rdata_bi,
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input [31:0] xport_rdata_bi,
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input cpu_present_i,
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input cpu_present_i,
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input [31:0] cpu_pc_bi,
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input [31:0] cpu_pc_bi,
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input cpu_break_i,
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input cpu_break_i,
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output cpu_reset_o,
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output cpu_reset_o,
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output cpu_enb_o
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output cpu_enb_o
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);
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);
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wire app_reset;
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wire app_reset;
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assign app_reset = srst_i | srst_o;
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assign app_reset = srst_i | srst_o;
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pss_reset_cntrl reset_cntrl
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pss_reset_cntrl reset_cntrl
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(
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(
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.clk_i(clk_i),
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.clk_i(clk_i),
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.arst_i(arst_i),
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.arst_i(arst_i),
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.srst_o(srst_o)
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.srst_o(srst_o)
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);
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);
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// interrupts
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// interrupts
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wire [3:0] INT;
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wire [3:0] INT;
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wire bus_error_int;
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wire bus_error_int;
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wire trap_int;
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wire trap_int;
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wire sgi_int;
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wire sgi_int;
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wire dma_int;
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wire dma_int;
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wire bus_error;
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wire bus_error;
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wire [31:0] bus_error_addr;
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wire [31:0] bus_error_addr;
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assign bus_error_int = bus_error;
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assign bus_error_int = bus_error;
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// INTC programming interface
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// INTC programming interface
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wire intc_ie;
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wire intc_ie;
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wire intc_ie_we;
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wire intc_ie_we;
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wire intc_ie_data;
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wire intc_ie_data;
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wire [7:0] intc_mask;
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wire [7:0] intc_mask;
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wire [7:0] intc_pending;
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wire [7:0] intc_pending;
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wire intc_clr_cmd;
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wire intc_clr_cmd;
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wire [7:0] intc_clr_code;
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wire [7:0] intc_clr_code;
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pss_edge_detector edge_det0
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pss_edge_detector edge_det0
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( .clk_i(clk_i), .rst_i(rst_i), .in(INT_bi[0]), .out(INT[0]) );
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( .clk_i(clk_i), .rst_i(rst_i), .in(INT_bi[0]), .out(INT[0]) );
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pss_edge_detector edge_det1
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pss_edge_detector edge_det1
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( .clk_i(clk_i), .rst_i(rst_i), .in(INT_bi[1]), .out(INT[1]) );
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( .clk_i(clk_i), .rst_i(rst_i), .in(INT_bi[1]), .out(INT[1]) );
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pss_edge_detector edge_det2
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pss_edge_detector edge_det2
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( .clk_i(clk_i), .rst_i(rst_i), .in(INT_bi[2]), .out(INT[2]) );
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( .clk_i(clk_i), .rst_i(rst_i), .in(INT_bi[2]), .out(INT[2]) );
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pss_edge_detector edge_det3
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pss_edge_detector edge_det3
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( .clk_i(clk_i), .rst_i(rst_i), .in(INT_bi[3]), .out(INT[3]) );
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( .clk_i(clk_i), .rst_i(rst_i), .in(INT_bi[3]), .out(INT[3]) );
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// Interrupt controller
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// Interrupt controller
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pss_int_controller int_controller
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pss_int_controller int_controller
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(
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(
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.clk_i(clk_i),
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.clk_i(clk_i),
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.rst_i(rst_i),
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.rst_i(rst_i),
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.interrupt_bi({INT, dma_int, sgi_int, trap_int, bus_error_int}),
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.interrupt_bi({INT, dma_int, sgi_int, trap_int, bus_error_int}),
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.ie_o(intc_ie),
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.ie_o(intc_ie),
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.ie_we_i(intc_ie_we),
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.ie_we_i(intc_ie_we),
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.ie_data_i(intc_ie_data),
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.ie_data_i(intc_ie_data),
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.mask_bi(intc_mask),
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.mask_bi(intc_mask),
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.pending_bo(intc_pending),
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.pending_bo(intc_pending),
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.clr_cmd_i(intc_clr_cmd),
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.clr_cmd_i(intc_clr_cmd),
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.clr_code_bi(intc_clr_code),
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.clr_code_bi(intc_clr_code),
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.cpu_req_o(cpu_ireq_o),
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.cpu_req_o(cpu_ireq_o),
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.cpu_ack_i(cpu_iack_i)
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.cpu_ack_i(cpu_iack_i)
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);
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);
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assign cpu_enb_o = 1'b1;
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assign cpu_enb_o = 1'b1;
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reg trap_enable;
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reg trap_enable;
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reg [31:0] trap_addr;
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reg [31:0] trap_addr;
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wire dma_req, dma_cmd, dma_autoinc;
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wire dma_req, dma_cmd, dma_autoinc;
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wire [31:0] dma_sourceaddr;
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wire [31:0] dma_sourceaddr;
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wire [31:0] dma_destaddr;
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wire [31:0] dma_destaddr;
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wire [31:0] dma_size;
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wire [31:0] dma_size;
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wire a31;
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wire a31;
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wire dma_works, bb_works;
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wire dma_works, bb_works;
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////////
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////////
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wire sfr_enb;
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wire sfr_enb;
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wire sfr_we;
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wire sfr_we;
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wire [31:0] sfr_wdata;
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wire [31:0] sfr_wdata;
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wire [31:0] sfr_addr;
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wire [31:0] sfr_addr;
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wire [3:0] sfr_writemask;
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wire [3:0] sfr_writemask;
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wire sfr_ack;
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wire sfr_ack;
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wire [31:0] sfr_rdata;
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wire [31:0] sfr_rdata;
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wire ext_enb;
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wire ext_enb;
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wire ext_we;
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wire ext_we;
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wire [31:0] ext_wdata;
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wire [31:0] ext_wdata;
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wire [31:0] ext_addr;
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wire [31:0] ext_addr;
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wire [3:0] ext_writemask;
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wire [3:0] ext_writemask;
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wire ext_ack;
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wire ext_ack;
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wire [31:0] ext_rdata;
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wire [31:0] ext_rdata;
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// RAM0 control //
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// RAM0 control //
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wire ram0_enb;
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wire ram0_enb;
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reg ram0_ack, ram0_ack_rd;
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reg ram0_ack, ram0_ack_rd;
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always @(posedge clk_i)
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always @(posedge clk_i)
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begin
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begin
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if (app_reset == 1'b1) ram0_ack_rd <= 1'b0;
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if (app_reset == 1'b1) ram0_ack_rd <= 1'b0;
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else if ((ram0_enb == 1'b1) && (ram0_we_o == 1'b0) && (ram0_ack_rd == 1'b0)) ram0_ack_rd <= 1'b1;
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else if ((ram0_enb == 1'b1) && (ram0_we_o == 1'b0) && (ram0_ack_rd == 1'b0)) ram0_ack_rd <= 1'b1;
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else ram0_ack_rd <= 1'b0;
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else ram0_ack_rd <= 1'b0;
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end
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end
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always @*
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always @*
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begin
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begin
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if ((ram0_enb == 1'b1) && (ram0_we_o == 1'b1)) ram0_ack = 1'b1;
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if ((ram0_enb == 1'b1) && (ram0_we_o == 1'b1)) ram0_ack = 1'b1;
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else ram0_ack = ram0_ack_rd;
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else ram0_ack = ram0_ack_rd;
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end
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end
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PSS_IC
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PSS_IC
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#(
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#(
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.MEM_SIZE_KB(MEM_SIZE_KB)
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.MEM_SIZE_KB(MEM_SIZE_KB)
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)
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)
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IC_fabric
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IC_fabric
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(
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(
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.clk_i(clk_i),
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.clk_i(clk_i),
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.rst_i(app_reset),
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.rst_i(app_reset),
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|
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//// Masters ////
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//// Masters ////
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.m0_enb_i(dbg_enb_i),
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.m0_enb_i(dbg_enb_i),
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.m0_we_i(dbg_we_i),
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.m0_we_i(dbg_we_i),
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.m0_addr_bi(dbg_addr_bi),
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.m0_addr_bi(dbg_addr_bi),
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.m0_wdata_bi(dbg_wdata_bi),
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.m0_wdata_bi(dbg_wdata_bi),
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.m0_writemask_bi(dbg_writemask_bi),
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.m0_writemask_bi(dbg_writemask_bi),
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.m0_ack_o(dbg_ack_o),
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.m0_ack_o(dbg_ack_o),
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.m0_rdata_bo(dbg_rdata_bo),
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.m0_rdata_bo(dbg_rdata_bo),
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.m1_enb_i(cpu_enb_i),
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.m1_enb_i(cpu_enb_i),
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.m1_we_i(cpu_we_i),
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.m1_we_i(cpu_we_i),
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.m1_addr_bi(cpu_addr_bi),
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.m1_addr_bi(cpu_addr_bi),
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.m1_wdata_bi(cpu_wdata_bi),
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.m1_wdata_bi(cpu_wdata_bi),
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.m1_writemask_bi(cpu_writemask_bi),
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.m1_writemask_bi(cpu_writemask_bi),
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.m1_ack_o(cpu_ack_o),
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.m1_ack_o(cpu_ack_o),
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.m1_rdata_bo(cpu_rdata_bo),
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.m1_rdata_bo(cpu_rdata_bo),
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//// Slaves ////
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//// Slaves ////
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.s0_enb_o(ram0_enb),
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.s0_enb_o(ram0_enb),
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.s0_we_o(ram0_we_o),
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.s0_we_o(ram0_we_o),
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.s0_addr_bo(ram0_addr_bo),
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.s0_addr_bo(ram0_addr_bo),
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.s0_wdata_bo(ram0_wdata_bo),
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.s0_wdata_bo(ram0_wdata_bo),
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.s0_writemask_bo(ram0_writemask_bo),
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.s0_writemask_bo(ram0_writemask_bo),
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.s0_ack_i(ram0_ack),
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.s0_ack_i(ram0_ack),
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.s0_rdata_bi(ram0_rdata_bi),
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.s0_rdata_bi(ram0_rdata_bi),
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|
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.s1_enb_o(sfr_enb),
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.s1_enb_o(sfr_enb),
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.s1_we_o(sfr_we),
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.s1_we_o(sfr_we),
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.s1_addr_bo(sfr_addr),
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.s1_addr_bo(sfr_addr),
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.s1_wdata_bo(sfr_wdata),
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.s1_wdata_bo(sfr_wdata),
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.s1_writemask_bo(sfr_writemask),
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.s1_writemask_bo(sfr_writemask),
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.s1_ack_i(sfr_ack),
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.s1_ack_i(sfr_ack),
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.s1_rdata_bi(sfr_rdata),
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.s1_rdata_bi(sfr_rdata),
|
|
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.s2_enb_o(ext_enb),
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.s2_enb_o(ext_enb),
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.s2_we_o(ext_we),
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.s2_we_o(ext_we),
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.s2_addr_bo(ext_addr),
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.s2_addr_bo(ext_addr),
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.s2_wdata_bo(ext_wdata),
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.s2_wdata_bo(ext_wdata),
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.s2_writemask_bo(ext_writemask),
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.s2_writemask_bo(ext_writemask),
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.s2_ack_i(ext_ack),
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.s2_ack_i(ext_ack),
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.s2_rdata_bi(ext_rdata),
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.s2_rdata_bi(ext_rdata),
|
|
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.error_o(bus_error),
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.error_o(bus_error),
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.error_addr_bo(bus_error_addr)
|
.error_addr_bo(bus_error_addr)
|
);
|
);
|
|
|
|
|
PSS_SFR
|
PSS_SFR
|
#(
|
#(
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.CPU_RESET_DEFAULT(CPU_RESET_DEFAULT),
|
.CPU_RESET_DEFAULT(CPU_RESET_DEFAULT),
|
|
.EXT_RESET_DEFAULT(EXT_RESET_DEFAULT),
|
.A31_DEFAULT(A31_DEFAULT),
|
.A31_DEFAULT(A31_DEFAULT),
|
.MEM_SIZE_KB(MEM_SIZE_KB)
|
.MEM_SIZE_KB(MEM_SIZE_KB)
|
)
|
)
|
SFR
|
SFR
|
(
|
(
|
.clk_i(clk_i),
|
.clk_i(clk_i),
|
.rst_i(app_reset),
|
.rst_i(app_reset),
|
|
|
.bus_enb_i(sfr_enb),
|
.bus_enb_i(sfr_enb),
|
.bus_we_i(sfr_we),
|
.bus_we_i(sfr_we),
|
.bus_wdata_bi(sfr_wdata),
|
.bus_wdata_bi(sfr_wdata),
|
.bus_addr_bi(sfr_addr),
|
.bus_addr_bi(sfr_addr),
|
.bus_writemask_bi(sfr_writemask),
|
.bus_writemask_bi(sfr_writemask),
|
.bus_ack_o(sfr_ack),
|
.bus_ack_o(sfr_ack),
|
.bus_rdata_bo(sfr_rdata),
|
.bus_rdata_bo(sfr_rdata),
|
|
|
.cpu_present_i(cpu_present_i),
|
.cpu_present_i(cpu_present_i),
|
.cpu_break_i(cpu_break_i),
|
.cpu_break_i(cpu_break_i),
|
.cpu_pc_bi(cpu_pc_bi),
|
.cpu_pc_bi(cpu_pc_bi),
|
|
|
.trap_cpu_enb_i(cpu_enb_i),
|
.trap_cpu_enb_i(cpu_enb_i),
|
.trap_cpu_addr_bi(cpu_addr_bi),
|
.trap_cpu_addr_bi(cpu_addr_bi),
|
|
|
.cpu_reset_o(cpu_reset_o),
|
.cpu_reset_o(cpu_reset_o),
|
|
.ext_reset_o(ext_rst_o),
|
.a31_o(a31),
|
.a31_o(a31),
|
|
|
.bus_error_i(bus_error),
|
.bus_error_i(bus_error),
|
.bus_error_addr_bi(bus_error_addr),
|
.bus_error_addr_bi(bus_error_addr),
|
|
|
.sgi_int_o(sgi_int),
|
.sgi_int_o(sgi_int),
|
.trap_int_o(trap_int),
|
.trap_int_o(trap_int),
|
|
|
.intc_ie_i(intc_ie),
|
.intc_ie_i(intc_ie),
|
.intc_pending_bi(intc_pending),
|
.intc_pending_bi(intc_pending),
|
.intc_ie_we_o(intc_ie_we),
|
.intc_ie_we_o(intc_ie_we),
|
.intc_ie_data_o(intc_ie_data),
|
.intc_ie_data_o(intc_ie_data),
|
.intc_mask_bo(intc_mask),
|
.intc_mask_bo(intc_mask),
|
.intc_clr_cmd_o(intc_clr_cmd),
|
.intc_clr_cmd_o(intc_clr_cmd),
|
.intc_clr_code_bo(intc_clr_code),
|
.intc_clr_code_bo(intc_clr_code),
|
|
|
.dma_req_o(dma_req),
|
.dma_req_o(dma_req),
|
.dma_cmd_o(dma_cmd),
|
.dma_cmd_o(dma_cmd),
|
.dma_autoinc_o(dma_autoinc),
|
.dma_autoinc_o(dma_autoinc),
|
.dma_size_bo(dma_size),
|
.dma_size_bo(dma_size),
|
.dma_sourceaddr_bo(dma_sourceaddr),
|
.dma_sourceaddr_bo(dma_sourceaddr),
|
.dma_destaddr_bo(dma_destaddr)
|
.dma_destaddr_bo(dma_destaddr)
|
);
|
);
|
|
|
|
|
wire bb_xport_req;
|
wire bb_xport_req;
|
reg bb_xport_ack;
|
reg bb_xport_ack;
|
reg bb_xport_err;
|
reg bb_xport_err;
|
wire bb_xport_we;
|
wire bb_xport_we;
|
wire [31:0] bb_xport_addr;
|
wire [31:0] bb_xport_addr;
|
wire [31:0] bb_xport_wdata;
|
wire [31:0] bb_xport_wdata;
|
reg bb_xport_resp;
|
reg bb_xport_resp;
|
reg [31:0] bb_xport_rdata;
|
reg [31:0] bb_xport_rdata;
|
|
|
wire dma_xport_req;
|
wire dma_xport_req;
|
reg dma_xport_ack;
|
reg dma_xport_ack;
|
reg dma_xport_err;
|
reg dma_xport_err;
|
wire dma_xport_we;
|
wire dma_xport_we;
|
wire [31:0] dma_xport_addr;
|
wire [31:0] dma_xport_addr;
|
wire [31:0] dma_xport_wdata;
|
wire [31:0] dma_xport_wdata;
|
reg dma_xport_resp;
|
reg dma_xport_resp;
|
reg [31:0] dma_xport_rdata;
|
reg [31:0] dma_xport_rdata;
|
|
|
|
|
PSS_DMA DMA
|
PSS_DMA DMA
|
(
|
(
|
.clk_i(clk_i),
|
.clk_i(clk_i),
|
.rst_i(app_reset),
|
.rst_i(app_reset),
|
|
|
.xport_busy_i(bb_works),
|
.xport_busy_i(bb_works),
|
.xport_busy_o(dma_works),
|
.xport_busy_o(dma_works),
|
|
|
.dma_int_o(dma_int),
|
.dma_int_o(dma_int),
|
|
|
.dma_req_i(dma_req),
|
.dma_req_i(dma_req),
|
.dma_cmd_i(dma_cmd),
|
.dma_cmd_i(dma_cmd),
|
.dma_autoinc_i(dma_autoinc),
|
.dma_autoinc_i(dma_autoinc),
|
.dma_size_bi(REG_DMA_SIZE),
|
.dma_size_bi(REG_DMA_SIZE),
|
.dma_sourceaddr_bi(REG_DMA_SOURCEADDR),
|
.dma_sourceaddr_bi(REG_DMA_SOURCEADDR),
|
.dma_destaddr_bi(REG_DMA_DESTADDR),
|
.dma_destaddr_bi(REG_DMA_DESTADDR),
|
|
|
.ram_addr_bo(ram1_addr_bo),
|
.ram_addr_bo(ram1_addr_bo),
|
.ram_we_o(ram1_we_o),
|
.ram_we_o(ram1_we_o),
|
.ram_wdata_bo(ram1_wdata_bo),
|
.ram_wdata_bo(ram1_wdata_bo),
|
.ram_rdata_bi(ram1_rdata_bi),
|
.ram_rdata_bi(ram1_rdata_bi),
|
|
|
.xport_req_o(dma_xport_req),
|
.xport_req_o(dma_xport_req),
|
.xport_ack_i(dma_xport_ack),
|
.xport_ack_i(dma_xport_ack),
|
.xport_err_i(dma_xport_err),
|
.xport_err_i(dma_xport_err),
|
.xport_we_o(dma_xport_we),
|
.xport_we_o(dma_xport_we),
|
.xport_addr_bo(dma_xport_addr),
|
.xport_addr_bo(dma_xport_addr),
|
.xport_wdata_bo(dma_xport_wdata),
|
.xport_wdata_bo(dma_xport_wdata),
|
.xport_resp_i(dma_xport_resp),
|
.xport_resp_i(dma_xport_resp),
|
.xport_rdata_bi(dma_xport_rdata)
|
.xport_rdata_bi(dma_xport_rdata)
|
);
|
);
|
|
|
|
|
PSS_BusBridge BusBridge
|
PSS_BusBridge BusBridge
|
(
|
(
|
.clk_i(clk_i),
|
.clk_i(clk_i),
|
.rst_i(app_reset),
|
.rst_i(app_reset),
|
|
|
.xport_busy_i(dma_works),
|
.xport_busy_i(dma_works),
|
.xport_busy_o(bb_works),
|
.xport_busy_o(bb_works),
|
|
|
.a31_i(a31),
|
.a31_i(a31),
|
|
|
.bus_enb_i(ext_enb),
|
.bus_enb_i(ext_enb),
|
.bus_we_i(ext_we),
|
.bus_we_i(ext_we),
|
.bus_addr_bi(ext_addr),
|
.bus_addr_bi(ext_addr),
|
.bus_wdata_bi(ext_wdata),
|
.bus_wdata_bi(ext_wdata),
|
.bus_writemask_bi(ext_writemask),
|
.bus_writemask_bi(ext_writemask),
|
.bus_ack_o(ext_ack),
|
.bus_ack_o(ext_ack),
|
.bus_rdata_bo(ext_rdata),
|
.bus_rdata_bo(ext_rdata),
|
|
|
// Expansion bus //
|
// Expansion bus //
|
.xport_req_o(bb_xport_req),
|
.xport_req_o(bb_xport_req),
|
.xport_ack_i(bb_xport_ack),
|
.xport_ack_i(bb_xport_ack),
|
.xport_err_i(bb_xport_err),
|
.xport_err_i(bb_xport_err),
|
.xport_we_o(bb_xport_we),
|
.xport_we_o(bb_xport_we),
|
.xport_addr_bo(bb_xport_addr),
|
.xport_addr_bo(bb_xport_addr),
|
.xport_wdata_bo(bb_xport_wdata),
|
.xport_wdata_bo(bb_xport_wdata),
|
.xport_resp_i(bb_xport_resp),
|
.xport_resp_i(bb_xport_resp),
|
.xport_rdata_bi(bb_xport_rdata)
|
.xport_rdata_bi(bb_xport_rdata)
|
);
|
);
|
|
|
// bus switch
|
// bus switch
|
always @*
|
always @*
|
begin
|
begin
|
|
|
bb_xport_ack = 1'b0;
|
bb_xport_ack = 1'b0;
|
bb_xport_err = 1'b0;
|
bb_xport_err = 1'b0;
|
bb_xport_resp = 1'b0;
|
bb_xport_resp = 1'b0;
|
bb_xport_rdata = 32'bx;
|
bb_xport_rdata = 32'bx;
|
|
|
dma_xport_ack = 1'b0;
|
dma_xport_ack = 1'b0;
|
dma_xport_err = 1'b0;
|
dma_xport_err = 1'b0;
|
dma_xport_resp = 1'b0;
|
dma_xport_resp = 1'b0;
|
dma_xport_rdata = 32'bx;
|
dma_xport_rdata = 32'bx;
|
|
|
if (dma_works == 1'b0) // switch to bus bridge
|
if (dma_works == 1'b0) // switch to bus bridge
|
begin
|
begin
|
|
|
bb_xport_ack = xport_ack_i;
|
bb_xport_ack = xport_ack_i;
|
bb_xport_err = xport_err_i;
|
bb_xport_err = xport_err_i;
|
bb_xport_resp = xport_resp_i;
|
bb_xport_resp = xport_resp_i;
|
bb_xport_rdata = xport_rdata_bi;
|
bb_xport_rdata = xport_rdata_bi;
|
|
|
xport_req_o = bb_xport_req;
|
xport_req_o = bb_xport_req;
|
xport_we_o = bb_xport_we;
|
xport_we_o = bb_xport_we;
|
xport_addr_bo = bb_xport_addr;
|
xport_addr_bo = bb_xport_addr;
|
xport_wdata_bo = bb_xport_wdata;
|
xport_wdata_bo = bb_xport_wdata;
|
|
|
end
|
end
|
|
|
else // switch to dma
|
else // switch to dma
|
begin
|
begin
|
|
|
dma_xport_ack = xport_ack_i;
|
dma_xport_ack = xport_ack_i;
|
dma_xport_err = xport_err_i;
|
dma_xport_err = xport_err_i;
|
dma_xport_resp = xport_resp_i;
|
dma_xport_resp = xport_resp_i;
|
dma_xport_rdata = xport_rdata_bi;
|
dma_xport_rdata = xport_rdata_bi;
|
|
|
xport_req_o = dma_xport_req;
|
xport_req_o = dma_xport_req;
|
xport_we_o = dma_xport_we;
|
xport_we_o = dma_xport_we;
|
xport_addr_bo = dma_xport_addr;
|
xport_addr_bo = dma_xport_addr;
|
xport_wdata_bo = dma_xport_wdata;
|
xport_wdata_bo = dma_xport_wdata;
|
|
|
end
|
end
|
|
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
