/*
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/*
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PSS
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PSS
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Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru>
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Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru>
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All rights reserved.
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All rights reserved.
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Version 0.9
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Version 0.99
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The FreeBSD license
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The FreeBSD license
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Redistribution and use in source and binary forms, with or without
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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modification, are permitted provided that the following conditions
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are met:
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are met:
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1. Redistributions of source code must retain the above copyright
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above
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2. Redistributions in binary form must reproduce the above
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copyright notice, this list of conditions and the following
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copyright notice, this list of conditions and the following
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disclaimer in the documentation and/or other materials
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disclaimer in the documentation and/or other materials
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provided with the distribution.
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provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
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THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
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EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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PSS PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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PSS PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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module pss_soc_top
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module pss_soc_top
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(
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(
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input clk_i, rst_i,
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input clk_i, rst_i,
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input rx_i,
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input rx_i,
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output tx_o,
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output tx_o,
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input ext_int_i,
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input ext_int_i,
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input [7:0] SW,
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input [7:0] SW,
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output reg [7:0] LED
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output reg [7:0] LED
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);
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);
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wire sync_reset;
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wire sync_reset;
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wire uc_bus_enb;
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wire uc_bus_enb;
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wire uc_bus_we;
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wire uc_bus_we;
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wire [31:0] uc_bus_addr;
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wire [31:0] uc_bus_addr;
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wire [31:0] uc_bus_wdata;
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wire [31:0] uc_bus_wdata;
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reg [31:0] uc_bus_rdata;
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reg [31:0] uc_bus_rdata;
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reg uc_bus_resp;
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reg uc_bus_resp;
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wire ext_int;
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wire ext_int;
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debouncer debouncer
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debouncer debouncer
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(
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(
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.clk_i(clk_i),
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.clk_i(clk_i),
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.rst_i(rst_i),
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.rst_i(rst_i),
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.in_i(ext_int_i),
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.in_i(ext_int_i),
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.out_o(ext_int)
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.out_o(ext_int)
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);
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);
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wire [3:0] interrupts;
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wire [3:0] interrupts;
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assign interrupts = {3'h0, ext_int};
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assign interrupts = {3'h0, ext_int};
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pss
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pss
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#(
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#(
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.CPU_PRESENT(1),
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.CPU_PRESENT(1),
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.CPU_RESET_DEFAULT(0),
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.CPU_RESET_DEFAULT(0),
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.A31_DEFAULTS(1),
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.A31_DEFAULT(1),
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.MEM_DATA("print_your_full_hex_filename"),
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.MEM_DATA("D:/Research/Computer_Science/Projects/Practice/zpu/pss/pss/SW/onboard/Heartbeat/Heartbeat.hex"),
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.MEM_SIZE_KB(8)
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.MEM_SIZE_KB(8)
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)
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)
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pss
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PSS
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(
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(
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.clk_i(clk_i),
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.clk_i(clk_i),
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.arst_i(rst_i),
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.arst_i(rst_i),
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.srst_i(0),
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.srst_o(sync_reset),
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.srst_o(sync_reset),
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.rx_i(rx_i),
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.rx_i(rx_i),
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.tx_o(tx_o),
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.tx_o(tx_o),
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.INT_i(interrupts),
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.INT_bi(interrupts),
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.xport_req_o(uc_bus_enb),
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.xport_req_o(uc_bus_enb),
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.xport_ack_i(1'b1),
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.xport_ack_i(1'b1),
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.xport_err_i(1'b0),
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.xport_err_i(1'b0),
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.xport_we_o(uc_bus_we),
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.xport_we_o(uc_bus_we),
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.xport_addr_bo(uc_bus_addr),
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.xport_addr_bo(uc_bus_addr),
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.xport_wdata_bo(uc_bus_wdata),
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.xport_wdata_bo(uc_bus_wdata),
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.xport_resp_i(uc_bus_resp),
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.xport_resp_i(uc_bus_resp),
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.xport_rdata_bi(uc_bus_rdata)
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.xport_rdata_bi(uc_bus_rdata)
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);
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);
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always @(posedge clk_i)
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always @(posedge clk_i)
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begin
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begin
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if (rst_i) uc_bus_rdata <= 32'h0;
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if (rst_i) uc_bus_rdata <= 32'h0;
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else if (uc_bus_addr == 32'h8A000000) uc_bus_rdata <= SW;
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else if (uc_bus_addr == 32'h8A000000) uc_bus_rdata <= SW;
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else uc_bus_rdata <= uc_bus_addr;
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else uc_bus_rdata <= uc_bus_addr;
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end
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end
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always @(posedge clk_i)
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always @(posedge clk_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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uc_bus_resp <= 1'b0;
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uc_bus_resp <= 1'b0;
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else if ( (uc_bus_enb == 1'b1) && (uc_bus_we == 1'b0) )
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else if ( (uc_bus_enb == 1'b1) && (uc_bus_we == 1'b0) )
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uc_bus_resp <= 1'b1;
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uc_bus_resp <= 1'b1;
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else
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else
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uc_bus_resp <= 1'b0;
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uc_bus_resp <= 1'b0;
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end
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end
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always @(posedge clk_i)
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always @(posedge clk_i)
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begin
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begin
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if (sync_reset)
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if (sync_reset)
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LED <= 8'hAA;
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LED <= 8'hAA;
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else if (uc_bus_we)
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else if (uc_bus_we)
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LED <= uc_bus_wdata;
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LED <= uc_bus_wdata;
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end
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end
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//assign uc_bus_rdata = uc_bus_addr;
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//assign uc_bus_rdata = uc_bus_addr;
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endmodule
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endmodule
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