/*
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/*
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PSS
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PSS
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Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru>
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Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru>
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All rights reserved.
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All rights reserved.
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Version 0.9
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Version 0.99
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The FreeBSD license
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The FreeBSD license
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Redistribution and use in source and binary forms, with or without
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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modification, are permitted provided that the following conditions
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are met:
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are met:
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1. Redistributions of source code must retain the above copyright
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above
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2. Redistributions in binary form must reproduce the above
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copyright notice, this list of conditions and the following
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copyright notice, this list of conditions and the following
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disclaimer in the documentation and/or other materials
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disclaimer in the documentation and/or other materials
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provided with the distribution.
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provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
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THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
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EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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PSS PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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PSS PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`define HALF_PERIOD 10 //external 50 MHZ
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`define HALF_PERIOD 10 //external 50 MHZ
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`define DIVIDER_115200 32'd8680
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`define DIVIDER_115200 32'd8680
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`define DIVIDER_19200 32'd52083
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`define DIVIDER_19200 32'd52083
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`define DIVIDER_9600 32'd104166
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`define DIVIDER_9600 32'd104166
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`define DIVIDER_4800 32'd208333
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`define DIVIDER_4800 32'd208333
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`define DIVIDER_2400 32'd416666
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`define DIVIDER_2400 32'd416666
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|
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// udm interface
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// udm interface
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`define SYNC_BYTE 8'h55
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`define SYNC_BYTE 8'h55
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`define ESCAPE_BYTE 8'h5a
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`define ESCAPE_BYTE 8'h5a
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`define IDCODE_CMD 8'h00 // check udm accessibility
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`define IDCODE_CMD 8'h00 // check udm accessibility
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`define RST_CMD 8'h80 // Reset slave
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`define RST_CMD 8'h80 // Reset slave
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`define WR_CMD 8'h81 // Write slave with autoincrement
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`define WR_CMD 8'h81 // Write slave with autoincrement
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`define RD_CMD 8'h82 // Read slave with autoincrement
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`define RD_CMD 8'h82 // Read slave with autoincrement
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`define WR_CMD_NOINC 8'h83 // Write slave without autoincrement
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`define WR_CMD_NOINC 8'h83 // Write slave without autoincrement
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`define RD_CMD_NOINC 8'h84 // Read slave without autoincrement
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`define RD_CMD_NOINC 8'h84 // Read slave without autoincrement
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module PSS_SoC_tb ();
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module PSS_SoC_tb ();
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//
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//
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localparam REG_CPU_CONTROL_ADDR = 32'h40000000;
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localparam REG_CPU_CONTROL_ADDR = 32'h40000000;
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localparam REG_CPU_PC_ADDR = 32'h40000004;
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localparam REG_CPU_PC_ADDR = 32'h40000004;
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localparam REG_CPU_A31 = 32'h40000008;
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localparam REG_CPU_A31 = 32'h40000008;
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localparam REG_DBG_A31 = 32'h4000000C;
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localparam REG_DBG_A31 = 32'h4000000C;
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localparam REG_INTC_CONTROL_ADDR = 32'h40000010;
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localparam REG_INTC_CONTROL_ADDR = 32'h40000010;
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localparam REG_INTC_MASK_ADDR = 32'h40000014;
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localparam REG_INTC_MASK_ADDR = 32'h40000014;
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localparam REG_INTC_REQ_ADDR = 32'h40000018;
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localparam REG_INTC_REQ_ADDR = 32'h40000018;
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localparam REG_MEM_SIZE_KB = 32'h4000001C;
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localparam REG_MEM_SIZE_KB = 32'h4000001C;
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localparam REG_DMA_CONTROL_ADDR = 32'h40000020;
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localparam REG_DMA_CONTROL_ADDR = 32'h40000020;
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localparam REG_DMA_SOURCEADDR_ADDR = 32'h40000024;
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localparam REG_DMA_SOURCEADDR_ADDR = 32'h40000024;
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localparam REG_DMA_DESTADDR_ADDR = 32'h40000028;
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localparam REG_DMA_DESTADDR_ADDR = 32'h40000028;
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localparam REG_DMA_SIZE_ADDR = 32'h4000002C;
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localparam REG_DMA_SIZE_ADDR = 32'h4000002C;
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localparam REG_SGI_ADDR = 32'h40000030;
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localparam REG_SGI_ADDR = 32'h40000030;
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localparam REG_BUS_ERROR_ADDR_ADDR = 32'h40000038;
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localparam REG_BUS_ERROR_ADDR_ADDR = 32'h40000038;
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localparam REG_BUS_ERROR_PC_ADDR = 32'h4000003C;
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localparam REG_BUS_ERROR_PC_ADDR = 32'h4000003C;
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localparam REG_TRAP_CONTROL_ADDR = 32'h40000040;
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localparam REG_TRAP_CONTROL_ADDR = 32'h40000040;
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localparam REG_TRAP_ADDR_ADDR = 32'h40000044;
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localparam REG_TRAP_ADDR_ADDR = 32'h40000044;
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//
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//
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reg CLK_50MHZ, RST, rx;
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reg CLK_50MHZ, RST, rx;
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reg [7:0] SW;
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reg [7:0] SW;
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wire [7:0] LED;
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wire [7:0] LED;
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//instantiating PSS
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//instantiating PSS
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pss_soc_top DUT(
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pss_soc_top DUT(
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.clk_i(CLK_50MHZ),
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.clk_i(CLK_50MHZ),
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.rst_i(RST),
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.rst_i(RST),
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.rx_i(rx),
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.rx_i(rx),
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.ext_int_i(0),
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.ext_int_i(0),
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.SW(SW),
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.SW(SW),
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.LED(LED));
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.LED(LED));
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//////////////////////////
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//////////////////////////
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/////////tasks////////////
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/////////tasks////////////
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//////////////////////////
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//////////////////////////
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reg parity;
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reg parity;
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integer i, j, k;
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integer i, j, k;
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reg [32:0] rate;
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reg [32:0] rate;
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reg [1:0] configuration;
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reg [1:0] configuration;
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////wait////
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////wait////
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task WAIT
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task WAIT
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(
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(
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input reg [15:0] periods
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input reg [15:0] periods
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);
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);
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begin
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begin
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for (i=0; i<periods; i=i+1)
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for (i=0; i<periods; i=i+1)
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begin
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begin
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#(`HALF_PERIOD*2);
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#(`HALF_PERIOD*2);
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end
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end
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end
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end
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endtask
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endtask
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////reset all////
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////reset all////
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task RESET_ALL ();
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task RESET_ALL ();
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begin
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begin
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CLK_50MHZ = 1'b0;
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CLK_50MHZ = 1'b0;
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RST = 1'b1;
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RST = 1'b1;
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rx = 1'b1;
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rx = 1'b1;
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#(`HALF_PERIOD/2);
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#(`HALF_PERIOD/2);
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RST = 1;
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RST = 1;
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#(`HALF_PERIOD*6);
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#(`HALF_PERIOD*6);
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RST = 0;
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RST = 0;
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end
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end
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endtask
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endtask
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task UART_CFG
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task UART_CFG
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(
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(
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input reg [32:0] rate_i,
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input reg [32:0] rate_i,
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input reg [1:0] configuration_i
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input reg [1:0] configuration_i
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);
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);
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begin
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begin
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rate = rate_i;
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rate = rate_i;
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configuration = configuration_i;
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configuration = configuration_i;
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end
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end
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endtask
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endtask
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////Send byte to UART////
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////Send byte to UART////
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task UART_SEND
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task UART_SEND
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(
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(
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input reg [7:0] send_byte
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input reg [7:0] send_byte
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);
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);
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begin
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begin
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parity = 0;
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parity = 0;
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//start
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//start
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rx = 1'b0;
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rx = 1'b0;
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#rate;
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#rate;
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//sending data
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//sending data
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for (i=0; i<8; i=i+1)
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for (i=0; i<8; i=i+1)
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begin
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begin
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rx = send_byte[0];
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rx = send_byte[0];
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#rate;
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#rate;
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parity = parity ^ send_byte[0];
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parity = parity ^ send_byte[0];
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send_byte = send_byte >> 1;
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send_byte = send_byte >> 1;
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end
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end
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//parity
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//parity
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if (configuration != 2'b00)
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if (configuration != 2'b00)
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begin
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begin
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if (configuration == 2'b10)
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if (configuration == 2'b10)
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begin
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begin
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rx = parity;
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rx = parity;
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#rate;
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#rate;
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end
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end
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else if (configuration == 2'b01)
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else if (configuration == 2'b01)
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begin
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begin
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rx = ~parity;
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rx = ~parity;
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#rate;
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#rate;
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end
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end
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end
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end
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//stop;
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//stop;
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rx = 1'b1;
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rx = 1'b1;
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#rate;
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#rate;
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end
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end
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endtask
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endtask
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task pss_hreset ();
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task pss_hreset ();
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begin
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begin
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UART_SEND(`SYNC_BYTE);
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UART_SEND(`SYNC_BYTE);
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UART_SEND(`RST_CMD);
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UART_SEND(`RST_CMD);
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end
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end
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endtask
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endtask
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task pss_sendbyte
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task pss_sendbyte
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(
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(
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input reg [7:0] databyte
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input reg [7:0] databyte
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);
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);
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begin
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begin
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if ((databyte == `SYNC_BYTE) || (databyte == `ESCAPE_BYTE))
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if ((databyte == `SYNC_BYTE) || (databyte == `ESCAPE_BYTE))
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UART_SEND(`ESCAPE_BYTE);
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UART_SEND(`ESCAPE_BYTE);
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end
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end
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UART_SEND(databyte);
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UART_SEND(databyte);
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endtask
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endtask
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task pss_sendword_le
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task pss_sendword_le
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(
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(
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input reg [31:0] dataword
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input reg [31:0] dataword
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);
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);
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begin
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begin
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pss_sendbyte(dataword[7:0]);
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pss_sendbyte(dataword[7:0]);
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pss_sendbyte(dataword[15:8]);
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pss_sendbyte(dataword[15:8]);
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pss_sendbyte(dataword[23:16]);
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pss_sendbyte(dataword[23:16]);
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pss_sendbyte(dataword[31:24]);
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pss_sendbyte(dataword[31:24]);
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end
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end
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endtask
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endtask
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task pss_sendword_be
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task pss_sendword_be
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(
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(
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input reg [31:0] dataword
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input reg [31:0] dataword
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);
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);
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begin
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begin
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pss_sendbyte(dataword[31:24]);
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pss_sendbyte(dataword[31:24]);
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pss_sendbyte(dataword[23:16]);
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pss_sendbyte(dataword[23:16]);
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pss_sendbyte(dataword[15:8]);
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pss_sendbyte(dataword[15:8]);
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pss_sendbyte(dataword[7:0]);
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pss_sendbyte(dataword[7:0]);
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end
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end
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endtask
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endtask
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task pss_wr_single
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task pss_wr_single
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(
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(
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input reg [31:0] wr_addr,
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input reg [31:0] wr_addr,
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input reg [31:0] wr_data
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input reg [31:0] wr_data
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);
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);
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begin
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begin
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// header
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// header
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UART_SEND(`SYNC_BYTE);
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UART_SEND(`SYNC_BYTE);
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UART_SEND(`WR_CMD);
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UART_SEND(`WR_CMD);
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// address
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// address
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pss_sendword_le(wr_addr);
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pss_sendword_le(wr_addr);
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// length
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// length
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pss_sendword_le(32'h4);
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pss_sendword_le(32'h4);
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// data
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// data
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pss_sendword_le(wr_data);
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pss_sendword_le(wr_data);
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|
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end
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end
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endtask
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endtask
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task pss_rd_single
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task pss_rd_single
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(
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(
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input reg [31:0] wr_addr
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input reg [31:0] wr_addr
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);
|
);
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begin
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begin
|
|
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// header
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// header
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UART_SEND(`SYNC_BYTE);
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UART_SEND(`SYNC_BYTE);
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UART_SEND(`RD_CMD);
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UART_SEND(`RD_CMD);
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|
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// address
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// address
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pss_sendword_le(wr_addr);
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pss_sendword_le(wr_addr);
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|
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// length
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// length
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pss_sendword_le(32'h4);
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pss_sendword_le(32'h4);
|
|
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end
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end
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endtask
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endtask
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|
|
|
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task pss_reset ();
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task pss_reset ();
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begin
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begin
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pss_wr_single(REG_CPU_CONTROL_ADDR, 32'h1);
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pss_wr_single(REG_CPU_CONTROL_ADDR, 32'h1);
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end
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end
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endtask
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endtask
|
|
|
|
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task pss_start ();
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task pss_start ();
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begin
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begin
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pss_wr_single(REG_CPU_CONTROL_ADDR, 32'h0);
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pss_wr_single(REG_CPU_CONTROL_ADDR, 32'h0);
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end
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end
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endtask
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endtask
|
|
|
|
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task pss_restart ();
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task pss_restart ();
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begin
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begin
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pss_reset();
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pss_reset();
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pss_start();
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pss_start();
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end
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end
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endtask
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endtask
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|
|
|
|
task pss_sgi ();
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task pss_sgi ();
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begin
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begin
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pss_wr_single(REG_SGI_ADDR, 32'h0);
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pss_wr_single(REG_SGI_ADDR, 32'h0);
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end
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end
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endtask
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endtask
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|
|
|
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task dma_test_wr ();
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task dma_test_wr ();
|
begin
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begin
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// data
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// data
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pss_wr_single(32'h00000008, 32'h123455aa);
|
pss_wr_single(32'h00000008, 32'h123455aa);
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pss_wr_single(32'h0000000C, 32'h07bb07bb);
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pss_wr_single(32'h0000000C, 32'h07bb07bb);
|
pss_wr_single(32'h00000010, 32'h23344556);
|
pss_wr_single(32'h00000010, 32'h23344556);
|
pss_wr_single(32'h00000014, 32'h89abcdef);
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pss_wr_single(32'h00000014, 32'h89abcdef);
|
|
|
// source address
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// source address
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pss_wr_single(REG_DMA_SOURCEADDR_ADDR, 32'h00000008);
|
pss_wr_single(REG_DMA_SOURCEADDR_ADDR, 32'h00000008);
|
|
|
// dest address
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// dest address
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pss_wr_single(REG_DMA_DESTADDR_ADDR, 32'h8a000000);
|
pss_wr_single(REG_DMA_DESTADDR_ADDR, 32'h8a000000);
|
|
|
// size
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// size
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pss_wr_single(REG_DMA_SIZE_ADDR, 32'd16);
|
pss_wr_single(REG_DMA_SIZE_ADDR, 32'd16);
|
|
|
// command
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// command
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pss_wr_single(REG_DMA_CONTROL_ADDR, 32'h00000006);
|
pss_wr_single(REG_DMA_CONTROL_ADDR, 32'h00000006);
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
task dma_test_rd ();
|
task dma_test_rd ();
|
begin
|
begin
|
// source address
|
// source address
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pss_wr_single(REG_DMA_SOURCEADDR_ADDR, 32'h8C000000);
|
pss_wr_single(REG_DMA_SOURCEADDR_ADDR, 32'h8C000000);
|
|
|
// dest address
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// dest address
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pss_wr_single(REG_DMA_DESTADDR_ADDR, 32'h00000010);
|
pss_wr_single(REG_DMA_DESTADDR_ADDR, 32'h00000010);
|
|
|
// size
|
// size
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pss_wr_single(REG_DMA_SIZE_ADDR, 32'd16);
|
pss_wr_single(REG_DMA_SIZE_ADDR, 32'd16);
|
|
|
// command
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// command
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pss_wr_single(REG_DMA_CONTROL_ADDR, 32'h00000004);
|
pss_wr_single(REG_DMA_CONTROL_ADDR, 32'h00000004);
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
//////////////////////////
|
//////////////////////////
|
//initial block
|
//initial block
|
initial
|
initial
|
begin
|
begin
|
$display ("### SIMULATION STARTED ###");
|
$display ("### SIMULATION STARTED ###");
|
|
|
SW = 8'h0;
|
SW = 8'h0;
|
RESET_ALL();
|
RESET_ALL();
|
UART_CFG(`DIVIDER_115200, 2'b00);
|
UART_CFG(`DIVIDER_115200, 2'b00);
|
WAIT(50000);
|
WAIT(50000);
|
UART_SEND(`SYNC_BYTE);
|
UART_SEND(`SYNC_BYTE);
|
UART_SEND(`IDCODE_CMD);
|
UART_SEND(`IDCODE_CMD);
|
pss_hreset();
|
pss_hreset();
|
|
|
dma_test_rd();
|
//dma_test_rd();
|
/*
|
|
pss_restart();
|
pss_restart();
|
pss_sgi();
|
//pss_sgi();
|
pss_sgi();
|
//pss_sgi();
|
pss_sgi();
|
//pss_sgi();
|
pss_wr_single(32'h8a000000, 32'h5aaa5aaa);
|
pss_wr_single(32'h8a000000, 32'h5aaa5aaa);
|
WAIT(50000);
|
WAIT(50000);
|
$display ("### READING MEMORY ###");
|
$display ("### READING MEMORY ###");
|
pss_rd_single(32'h00000000);
|
pss_rd_single(32'h00000000);
|
pss_rd_single(32'h00000004);
|
pss_rd_single(32'h00000004);
|
pss_rd_single(32'h00000008);
|
pss_rd_single(32'h00000008);
|
pss_rd_single(32'h0000000C);
|
pss_rd_single(32'h0000000C);
|
WAIT(777);
|
WAIT(777);
|
pss_rd_single(32'h00000000);
|
pss_rd_single(32'h00000000);
|
pss_rd_single(32'h00000004);
|
pss_rd_single(32'h00000004);
|
pss_rd_single(32'h00000008);
|
pss_rd_single(32'h00000008);
|
pss_rd_single(32'h0000000C);
|
pss_rd_single(32'h0000000C);
|
*/
|
|
|
|
WAIT(50000);
|
WAIT(50000);
|
|
|
$display ("### TEST PROCEDURE FINISHED ###");
|
$display ("### TEST PROCEDURE FINISHED ###");
|
$stop;
|
$stop;
|
end
|
end
|
//
|
//
|
always #`HALF_PERIOD CLK_50MHZ = ~CLK_50MHZ;
|
always #`HALF_PERIOD CLK_50MHZ = ~CLK_50MHZ;
|
|
|
always #50000 SW = SW + 8'h1;
|
always #50000 SW = SW + 8'h1;
|
//
|
//
|
endmodule
|
endmodule
|
|
|
