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[/] [pwm/] [trunk/] [RTL/] [down_clocking_even.v] - Diff between revs 2 and 6
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Rev 6 |
/*Author: Zhuxu
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/*Down clocking module
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m99a1@yahoo.cn
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Down clocking module
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Output clock frequency is the original frequency divided by an even number
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Output clock frequency is the original frequency divided by an even number
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*/
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*/
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module down_clocking_even(
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module down_clocking_even(
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input i_clk,
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input i_clk,
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input i_rst,
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input i_rst,
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input [15:0]i_divisor,
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input [15:0]i_divisor,
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output o_clk
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output o_clk
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);
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);
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wire [15:0]divisor;
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wire [15:0]divisor;
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wire borrow;
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wire borrow;
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minus_one minus_one_0(
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minus_one minus_one_0(
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i_divisor,
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i_divisor,
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divisor,
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divisor,
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borrow
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borrow
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);
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);
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wire go;
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wire go;
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assign go=((i_divisor!=0)&&i_rst);
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assign go=((i_divisor!=0)&&i_rst);
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reg [15:0]ct;
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reg [15:0]ct;
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reg clk;
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reg clk;
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always@(posedge i_clk or i_rst)
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always@(posedge i_clk or negedge i_rst)
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if(!i_rst)begin
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if(!i_rst)begin
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ct<=0;
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ct<=0;
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clk<=0;
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clk<=0;
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end
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end
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else if(go)begin
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else if(go)begin
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if(ct>=divisor)begin
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if(ct>=divisor)begin
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ct<=0;
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ct<=0;
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clk<=~clk;
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clk<=~clk;
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end
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end
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else ct<=ct+1;
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else ct<=ct+1;
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end
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end
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assign o_clk=go?clk:i_clk;
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assign o_clk=go?clk:i_clk;
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