Timing and usage after synthesis reported for Xilinx Artix7 (XC7A100T-2csg324) with bits=16 and dithering=5. Xilinx ISE 14.7 was used, with default settings. No optimizations of any parameters or tool settings were applied. Also, all of the code is in pure VHDL, and no Xilinx specific IP blocks or hard macros have been used.
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Timing and usage after synthesis reported for Xilinx Artix7 (XC7A100T-2csg324) with bits=16 and dithering=5. Xilinx ISE 14.7 was used, with default settings. No optimizations of any parameters or tool settings were applied. Also, all of the code is in pure VHDL, and no Xilinx specific IP blocks or hard macros have been used.
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Summary:
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minimal ineq reg p_small pipelined
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LUTs 36 43 35 40 49
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REGs 17 17 30 31 43
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MHz 259 211 382 437 483
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sensitive yes no no no no
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latency none none 1sc 1sc+1c 1sc+2c
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Where sensitive means that the implementation can produce incorrect output for a short duration during input value change, and latency units are sc = subcycle, c = clock cycle.
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For minimal implementation:
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For minimal implementation:
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Device utilization summary:
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Device utilization summary:
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---------------------------
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---------------------------
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Selected Device : 7a100tcsg324-2
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Selected Device : 7a100tcsg324-2
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Slice Logic Utilization:
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Slice Logic Utilization:
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Number of Slice Registers: 17 out of 126800 0%
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Number of Slice Registers: 17 out of 126800 0%
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Number of Slice LUTs: 36 out of 63400 0%
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Number of Slice LUTs: 36 out of 63400 0%
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Number used as Logic: 36 out of 63400 0%
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Number used as Logic: 36 out of 63400 0%
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Slice Logic Distribution:
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Slice Logic Distribution:
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Number of LUT Flip Flop pairs used: 36
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Number of LUT Flip Flop pairs used: 36
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Number with an unused Flip Flop: 19 out of 36 52%
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Number with an unused Flip Flop: 19 out of 36 52%
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Number with an unused LUT: 0 out of 36 0%
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Number with an unused LUT: 0 out of 36 0%
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Number of fully used LUT-FF pairs: 17 out of 36 47%
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Number of fully used LUT-FF pairs: 17 out of 36 47%
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Number of unique control sets: 1
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Number of unique control sets: 1
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IO Utilization:
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IO Utilization:
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Number of IOs: 18
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Number of IOs: 18
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Number of bonded IOBs: 18 out of 210 8%
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Number of bonded IOBs: 18 out of 210 8%
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Specific Feature Utilization:
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Specific Feature Utilization:
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Number of BUFG/BUFGCTRLs: 1 out of 32 3%
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Number of BUFG/BUFGCTRLs: 1 out of 32 3%
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Timing Summary: (after synthesis)
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Timing Summary: (after synthesis)
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---------------
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---------------
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Minimum period: 3.854ns (Maximum Frequency: 259.491MHz)
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Minimum period: 3.854ns (Maximum Frequency: 259.491MHz)
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Minimum input arrival time before clock: 3.646ns
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Minimum input arrival time before clock: 3.646ns
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Maximum output required time after clock: 0.742ns
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Maximum output required time after clock: 0.742ns
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Maximum combinational path delay: No path found
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Maximum combinational path delay: No path found
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After place and route:
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After place and route:
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----------------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------------
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Constraint | Check | Worst Case | Best Case | Timing | Timing
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Constraint | Check | Worst Case | Best Case | Timing | Timing
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| | Slack | Achievable | Errors | Score
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| | Slack | Achievable | Errors | Score
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----------------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------------
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Autotimespec constraint for clock net clk | SETUP | N/A| 3.387ns| N/A| 0
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Autotimespec constraint for clock net clk | SETUP | N/A| 3.387ns| N/A| 0
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_BUFGP | HOLD | 0.287ns| | 0| 0
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_BUFGP | HOLD | 0.287ns| | 0| 0
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----------------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------------
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For pipelined implementation:
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For pipelined implementation:
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Device utilization summary:
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Device utilization summary:
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---------------------------
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---------------------------
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Selected Device : 7a100tcsg324-2
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Selected Device : 7a100tcsg324-2
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Slice Logic Utilization:
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Slice Logic Utilization:
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Number of Slice Registers: 43 out of 126800 0%
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Number of Slice Registers: 43 out of 126800 0%
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Number of Slice LUTs: 49 out of 63400 0%
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Number of Slice LUTs: 49 out of 63400 0%
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Number used as Logic: 49 out of 63400 0%
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Number used as Logic: 49 out of 63400 0%
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Slice Logic Distribution:
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Slice Logic Distribution:
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Number of LUT Flip Flop pairs used: 50
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Number of LUT Flip Flop pairs used: 50
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Number with an unused Flip Flop: 7 out of 50 14%
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Number with an unused Flip Flop: 7 out of 50 14%
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Number with an unused LUT: 1 out of 50 2%
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Number with an unused LUT: 1 out of 50 2%
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Number of fully used LUT-FF pairs: 42 out of 50 84%
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Number of fully used LUT-FF pairs: 42 out of 50 84%
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Number of unique control sets: 2
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Number of unique control sets: 2
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IO Utilization:
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IO Utilization:
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Number of IOs: 18
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Number of IOs: 18
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Number of bonded IOBs: 18 out of 210 8%
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Number of bonded IOBs: 18 out of 210 8%
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Specific Feature Utilization:
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Specific Feature Utilization:
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Number of BUFG/BUFGCTRLs: 1 out of 32 3%
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Number of BUFG/BUFGCTRLs: 1 out of 32 3%
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Timing Summary: (after synthesis)
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Timing Summary: (after synthesis)
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---------------
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---------------
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Minimum period: 2.069ns (Maximum Frequency: 483.255MHz)
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Minimum period: 2.069ns (Maximum Frequency: 483.255MHz)
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Minimum input arrival time before clock: 1.606ns
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Minimum input arrival time before clock: 1.606ns
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Maximum output required time after clock: 0.742ns
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Maximum output required time after clock: 0.742ns
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Maximum combinational path delay: No path found
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Maximum combinational path delay: No path found
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After place and route:
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After place and route:
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----------------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------------
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Constraint | Check | Worst Case | Best Case | Timing | Timing
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Constraint | Check | Worst Case | Best Case | Timing | Timing
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| | Slack | Achievable | Errors | Score
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| | Slack | Achievable | Errors | Score
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----------------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------------
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Autotimespec constraint for clock net clk | SETUP | N/A| 2.027ns| N/A| 0
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Autotimespec constraint for clock net clk | SETUP | N/A| 2.027ns| N/A| 0
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_BUFGP | HOLD | 0.209ns| | 0| 0
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_BUFGP | HOLD | 0.209ns| | 0| 0
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----------------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------------
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For inequality based implementation:
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For inequality based implementation:
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Device utilization summary:
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Device utilization summary:
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---------------------------
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---------------------------
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Selected Device : 7a100tcsg324-2
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Selected Device : 7a100tcsg324-2
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Slice Logic Utilization:
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Slice Logic Utilization:
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Number of Slice Registers: 17 out of 126800 0%
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Number of Slice Registers: 17 out of 126800 0%
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Number of Slice LUTs: 43 out of 63400 0%
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Number of Slice LUTs: 43 out of 63400 0%
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Number used as Logic: 43 out of 63400 0%
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Number used as Logic: 43 out of 63400 0%
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Slice Logic Distribution:
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Slice Logic Distribution:
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Number of LUT Flip Flop pairs used: 44
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Number of LUT Flip Flop pairs used: 44
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Number with an unused Flip Flop: 27 out of 44 61%
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Number with an unused Flip Flop: 27 out of 44 61%
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Number with an unused LUT: 1 out of 44 2%
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Number with an unused LUT: 1 out of 44 2%
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Number of fully used LUT-FF pairs: 16 out of 44 36%
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Number of fully used LUT-FF pairs: 16 out of 44 36%
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Number of unique control sets: 2
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Number of unique control sets: 2
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IO Utilization:
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IO Utilization:
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Number of IOs: 18
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Number of IOs: 18
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Number of bonded IOBs: 18 out of 210 8%
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Number of bonded IOBs: 18 out of 210 8%
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Specific Feature Utilization:
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Specific Feature Utilization:
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Number of BUFG/BUFGCTRLs: 1 out of 32 3%
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Number of BUFG/BUFGCTRLs: 1 out of 32 3%
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Timing Summary: (after synthesis)
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Timing Summary: (after synthesis)
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---------------
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---------------
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Minimum period: 4.737ns (Maximum Frequency: 211.113MHz)
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Minimum period: 4.737ns (Maximum Frequency: 211.113MHz)
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Minimum input arrival time before clock: 4.529ns
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Minimum input arrival time before clock: 4.529ns
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Maximum output required time after clock: 0.742ns
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Maximum output required time after clock: 0.742ns
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Maximum combinational path delay: No path found
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Maximum combinational path delay: No path found
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After place and route:
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After place and route:
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----------------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------------
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Constraint | Check | Worst Case | Best Case | Timing | Timing
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Constraint | Check | Worst Case | Best Case | Timing | Timing
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| | Slack | Achievable | Errors | Score
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| | Slack | Achievable | Errors | Score
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----------------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------------
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Autotimespec constraint for clock net clk | SETUP | N/A| 4.390ns| N/A| 0
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Autotimespec constraint for clock net clk | SETUP | N/A| 4.390ns| N/A| 0
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_BUFGP | HOLD | 0.287ns| | 0| 0
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_BUFGP | HOLD | 0.287ns| | 0| 0
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----------------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------------
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For register based implementation:
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For register based implementation:
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Device utilization summary:
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Device utilization summary:
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---------------------------
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---------------------------
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Selected Device : 7a100tcsg324-2
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Selected Device : 7a100tcsg324-2
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Slice Logic Utilization:
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Slice Logic Utilization:
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Number of Slice Registers: 30 out of 126800 0%
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Number of Slice Registers: 30 out of 126800 0%
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Number of Slice LUTs: 35 out of 63400 0%
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Number of Slice LUTs: 35 out of 63400 0%
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Number used as Logic: 35 out of 63400 0%
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Number used as Logic: 35 out of 63400 0%
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Slice Logic Distribution:
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Slice Logic Distribution:
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Number of LUT Flip Flop pairs used: 36
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Number of LUT Flip Flop pairs used: 36
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Number with an unused Flip Flop: 6 out of 36 16%
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Number with an unused Flip Flop: 6 out of 36 16%
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Number with an unused LUT: 1 out of 36 2%
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Number with an unused LUT: 1 out of 36 2%
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Number of fully used LUT-FF pairs: 29 out of 36 80%
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Number of fully used LUT-FF pairs: 29 out of 36 80%
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Number of unique control sets: 2
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Number of unique control sets: 2
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IO Utilization:
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IO Utilization:
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Number of IOs: 18
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Number of IOs: 18
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Number of bonded IOBs: 18 out of 210 8%
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Number of bonded IOBs: 18 out of 210 8%
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Specific Feature Utilization:
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Specific Feature Utilization:
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Number of BUFG/BUFGCTRLs: 1 out of 32 3%
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Number of BUFG/BUFGCTRLs: 1 out of 32 3%
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Timing Summary: (after synthesis)
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Timing Summary: (after synthesis)
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Minimum period: 2.618ns (Maximum Frequency: 381.912MHz)
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Minimum period: 2.618ns (Maximum Frequency: 381.912MHz)
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Minimum input arrival time before clock: 2.410ns
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Minimum input arrival time before clock: 2.410ns
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Maximum output required time after clock: 0.742ns
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Maximum output required time after clock: 0.742ns
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Maximum combinational path delay: No path found
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Maximum combinational path delay: No path found
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After place and route:
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After place and route:
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----------------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------------
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Constraint | Check | Worst Case | Best Case | Timing | Timing
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Constraint | Check | Worst Case | Best Case | Timing | Timing
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| | Slack | Achievable | Errors | Score
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| | Slack | Achievable | Errors | Score
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----------------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------------
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Autotimespec constraint for clock net clk | SETUP | N/A| 2.436ns| N/A| 0
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Autotimespec constraint for clock net clk | SETUP | N/A| 2.436ns| N/A| 0
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_BUFGP | HOLD | 0.212ns| | 0| 0
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_BUFGP | HOLD | 0.212ns| | 0| 0
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----------------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------------
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For small pipelined implementation:
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For small pipelined implementation:
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Device utilization summary:
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Device utilization summary:
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---------------------------
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---------------------------
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Selected Device : 7a100tcsg324-2
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Selected Device : 7a100tcsg324-2
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Slice Logic Utilization:
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Slice Logic Utilization:
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Number of Slice Registers: 31 out of 126800 0%
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Number of Slice Registers: 31 out of 126800 0%
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Number of Slice LUTs: 40 out of 63400 0%
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Number of Slice LUTs: 40 out of 63400 0%
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Number used as Logic: 40 out of 63400 0%
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Number used as Logic: 40 out of 63400 0%
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Slice Logic Distribution:
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Slice Logic Distribution:
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Number of LUT Flip Flop pairs used: 41
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Number of LUT Flip Flop pairs used: 41
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Number with an unused Flip Flop: 10 out of 41 24%
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Number with an unused Flip Flop: 10 out of 41 24%
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Number with an unused LUT: 1 out of 41 2%
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Number with an unused LUT: 1 out of 41 2%
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Number of fully used LUT-FF pairs: 30 out of 41 73%
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Number of fully used LUT-FF pairs: 30 out of 41 73%
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Number of unique control sets: 3
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Number of unique control sets: 3
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IO Utilization:
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IO Utilization:
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Number of IOs: 18
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Number of IOs: 18
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Number of bonded IOBs: 18 out of 210 8%
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Number of bonded IOBs: 18 out of 210 8%
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Specific Feature Utilization:
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Specific Feature Utilization:
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Number of BUFG/BUFGCTRLs: 1 out of 32 3%
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Number of BUFG/BUFGCTRLs: 1 out of 32 3%
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Timing Summary: (after synthesis)
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Timing Summary: (after synthesis)
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Minimum period: 2.286ns (Maximum Frequency: 437.350MHz)
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Minimum period: 2.286ns (Maximum Frequency: 437.350MHz)
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Minimum input arrival time before clock: 1.868ns
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Minimum input arrival time before clock: 1.868ns
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Maximum output required time after clock: 0.742ns
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Maximum output required time after clock: 0.742ns
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Maximum combinational path delay: No path found
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Maximum combinational path delay: No path found
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After place and route:
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After place and route:
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----------------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------------
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Constraint | Check | Worst Case | Best Case | Timing | Timing
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Constraint | Check | Worst Case | Best Case | Timing | Timing
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| | Slack | Achievable | Errors | Score
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| | Slack | Achievable | Errors | Score
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----------------------------------------------------------------------------------------------------------
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Autotimespec constraint for clock net clk | SETUP | N/A| 2.083ns| N/A| 0
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Autotimespec constraint for clock net clk | SETUP | N/A| 2.083ns| N/A| 0
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_BUFGP | HOLD | 0.201ns| | 0| 0
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_BUFGP | HOLD | 0.201ns| | 0| 0
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