//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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module
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module
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riffa_chn_rx
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riffa_chn_rx
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#(
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#(
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N // data bus width in bytes
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N // data bus width in bytes
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)
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)
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(
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(
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riffa_chnl_if chnl_bus,
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riffa_chnl_if chnl_bus,
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input rx_ready,
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input rx_ready,
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output rx_done,
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output rx_done,
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output reg [30:0] rx_index,
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output reg [30:0] rx_index,
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output reg rx_last,
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output reg rx_last,
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output reg [31:0] rx_len,
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output reg [31:0] rx_len,
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output reg [30:0] rx_off,
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output reg [30:0] rx_off,
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// output rx_data_ren, // shouldn't be here??
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// output rx_data_ren, // shouldn't be here??
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output rd_empty,
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output rd_empty,
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output [(8*N)-1:0] rd_data,
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output [(8*N)-1:0] rd_data,
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input rd_en,
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input rd_en,
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input clk,
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input clk,
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input reset
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input reset
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);
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);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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riffa_chnl_rx_fsm
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riffa_chnl_rx_fsm
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riffa_chnl_rx_fsm_i
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riffa_chnl_rx_fsm_i
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(
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(
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.rx(chnl_bus.rx),
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.rx(chnl_bus.rx),
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.rx_data_valid(chnl_bus.rx_data_valid),
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.rx_data_valid(chnl_bus.rx_data_valid),
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.rx_ack(chnl_bus.rx_ack),
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.rx_ack(chnl_bus.rx_ack),
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.*
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.*
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);
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);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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always_ff @(posedge clk)
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always_ff @(posedge clk)
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if(chnl_bus.rx & chnl_bus.rx_ack)
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if(chnl_bus.rx & chnl_bus.rx_ack)
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begin
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begin
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rx_last <= chnl_bus.rx_last;
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rx_last <= chnl_bus.rx_last;
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rx_len <= chnl_bus.rx_len;
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rx_len <= chnl_bus.rx_len;
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rx_off <= chnl_bus.rx_off;
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rx_off <= chnl_bus.rx_off;
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end
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end
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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wire [(8*N)-1:0] wr_data = chnl_bus.rx_data;
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wire [(8*N)-1:0] wr_data = chnl_bus.rx_data;
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wire wr_full;
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wire wr_full;
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wire wr_en = chnl_bus.rx_data_ren & chnl_bus.rx_data_valid;
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wire wr_en = chnl_bus.rx_data_ren & chnl_bus.rx_data_valid;
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tiny_sync_fifo #(.W((8*N)))
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tiny_sync_fifo #(.W((8*N)))
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tiny_sync_fifo_i(.*);
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tiny_sync_fifo_i(.*);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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always_ff @(posedge clk)
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always_ff @(posedge clk)
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if(reset | rx_done)
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if(reset | rx_done)
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rx_index = 0;
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rx_index <= 0;
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else if(rd_en)
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else if(rd_en)
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rx_index <= rx_index + (N/4); // increment by 32 bit words
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rx_index <= rx_index + (N/4); // increment by 32 bit words
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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// assign rx_data_ren = ~wr_full; // shouldn't be here??
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// assign rx_data_ren = ~wr_full; // shouldn't be here??
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assign chnl_bus.rx_data_ren = ~wr_full;
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assign chnl_bus.rx_data_ren = ~wr_full;
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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endmodule
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endmodule
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