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-- Copyright (c) 2013 Malte Graeper (mgraep@t-online.de) All rights reserved.
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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library work;
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library work;
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use work.qfp32_unit_p.all;
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use work.qfp32_unit_p.all;
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use work.qfp_p.all;
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use work.qfp_p.all;
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entity Top is
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entity Top is
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port (
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port (
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clock_50 : in std_ulogic;
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clock_50 : in std_ulogic;
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key : in std_ulogic_vector(1 downto 0);
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key : in std_ulogic_vector(1 downto 0);
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sw : in std_ulogic_vector(3 downto 0);
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sw : in std_ulogic_vector(3 downto 0);
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led : out std_ulogic_vector(7 downto 0));
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led : out std_ulogic_vector(7 downto 0));
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end Top;
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end Top;
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architecture Rtl of Top is
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architecture Rtl of Top is
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component qfp_unit
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component qfp_unit
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generic (
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generic (
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config : natural);
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config : natural);
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port (
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port (
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clk_i : in std_ulogic;
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clk_i : in std_ulogic;
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reset_n_i : in std_ulogic;
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reset_n_i : in std_ulogic;
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cmd_i : in qfp_cmd_t;
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cmd_i : in qfp_cmd_t;
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ready_o : out std_ulogic;
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ready_o : out std_ulogic;
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start_i : in std_ulogic;
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start_i : in std_ulogic;
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regA_i : in std_ulogic_vector(31 downto 0);
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regA_i : in std_ulogic_vector(31 downto 0);
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regB_i : in std_ulogic_vector(31 downto 0);
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regB_i : in std_ulogic_vector(31 downto 0);
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result_o : out std_ulogic_vector(31 downto 0);
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result_o : out std_ulogic_vector(31 downto 0);
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cmp_gt_o : out std_ulogic;
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cmp_gt_o : out std_ulogic;
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cmp_z_o : out std_ulogic;
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cmp_z_o : out std_ulogic;
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complete_o : out std_ulogic);
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complete_o : out std_ulogic);
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end component;
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end component;
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signal din : std_ulogic_vector(69 downto 0);
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signal din : std_ulogic_vector(69 downto 0);
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signal dout : std_ulogic_vector(35 downto 0);
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signal dout : std_ulogic_vector(35 downto 0);
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signal count : unsigned(4 downto 0);
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signal count : unsigned(4 downto 0);
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signal clk : std_ulogic;
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signal clk : std_ulogic;
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signal reset_n : std_ulogic;
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signal reset_n : std_ulogic;
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signal cmd : qfp_cmd_t;
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signal cmd : qfp_cmd_t;
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signal ready : std_ulogic;
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signal ready : std_ulogic;
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signal start : std_ulogic;
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signal start : std_ulogic;
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signal regA : std_ulogic_vector(31 downto 0);
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signal regA : std_ulogic_vector(31 downto 0);
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signal regB : std_ulogic_vector(31 downto 0);
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signal regB : std_ulogic_vector(31 downto 0);
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signal result : std_ulogic_vector(31 downto 0);
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signal result : std_ulogic_vector(31 downto 0);
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signal cmp_gt : std_ulogic;
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signal cmp_gt : std_ulogic;
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signal cmp_z : std_ulogic;
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signal cmp_z : std_ulogic;
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signal complete : std_ulogic;
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signal complete : std_ulogic;
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begin -- Rtl
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begin -- Rtl
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clk <= clock_50;
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clk <= clock_50;
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reset_n <= key(0);
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reset_n <= key(0);
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process (clk, reset_n)
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process (clk, reset_n)
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begin -- process
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begin -- process
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if reset_n = '0' then -- asynchronous reset (active low)
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if reset_n = '0' then -- asynchronous reset (active low)
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din <= (others => '0');
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din <= (others => '0');
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dout <= (others => '0');
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dout <= (others => '0');
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count <= to_unsigned(0,5);
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count <= to_unsigned(0,5);
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elsif clk'event and clk = '1' then -- rising clock edge
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elsif clk'event and clk = '1' then -- rising clock edge
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if count = to_unsigned(21,5) then
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if count = to_unsigned(21,5) then
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count <= to_unsigned(0,5);
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count <= to_unsigned(0,5);
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din <= (others => '0');
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din <= (others => '0');
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dout <= result & cmp_gt & cmp_z & complete & ready;
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dout <= result & cmp_gt & cmp_z & complete & ready;
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else
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else
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din <= din(din'length-5 downto 0) & sw;-- shift in
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din <= din(din'length-5 downto 0) & sw;-- shift in
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dout <= "0000" & dout(dout'length-1 downto 4);
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dout <= "0000" & dout(dout'length-1 downto 4);
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count <= count+1;
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count <= count+1;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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cmd.unit <= unsigned(din(2 downto 0));
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cmd.unit <= unsigned(din(2 downto 0));
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cmd.sub_cmd <= din(4 downto 3);
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cmd.sub_cmd <= din(4 downto 3);
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start <= din(5);
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start <= din(5);
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regA <= din(37 downto 6);
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regA <= din(37 downto 6);
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regB <= din(69 downto 38);
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regB <= din(69 downto 38);
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led(3 downto 0) <= dout(3 downto 0);
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led(3 downto 0) <= dout(3 downto 0);
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qfp_unit_1: qfp_unit
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qfp_unit_1: qfp_unit
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generic map (
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generic map (
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config => qfp_config_add+qfp_config_mul+qfp_config_recp+qfp_config_misc)
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config => qfp_config_add+qfp_config_mul+qfp_config_recp+qfp_config_misc)
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port map (
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port map (
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clk_i => clk,
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clk_i => clk,
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reset_n_i => reset_n,
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reset_n_i => reset_n,
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cmd_i => cmd,
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cmd_i => cmd,
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ready_o => ready,
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ready_o => ready,
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start_i => start,
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start_i => start,
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regA_i => regA,
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regA_i => regA,
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regB_i => regB,
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regB_i => regB,
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result_o => result,
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result_o => result,
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cmp_gt_o => cmp_gt,
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cmp_gt_o => cmp_gt,
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cmp_z_o => cmp_z,
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cmp_z_o => cmp_z,
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complete_o => complete);
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complete_o => complete);
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end Rtl;
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end Rtl;
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