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-- Copyright (c) 2013 Malte Graeper (mgraep@t-online.de) All rights reserved.
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Title : Testbench for design "qfp_unit"
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-- Testbench for design "qfp_unit"
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-- Project :
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-------------------------------------------------------------------------------
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-- File : qfp_unit_tb.vhd
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-- Author : <Malte@MALTE>
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-- Company :
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-- Created : 2013-08-18
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-- Last update: 2014-06-30
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-- Platform :
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-- Standard : VHDL'93/02
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-------------------------------------------------------------------------------
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-- Description:
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-------------------------------------------------------------------------------
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-- Copyright (c) 2013
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 2013-08-18 1.0 Malte Created
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_textio.all; -- read std_ulogic etc
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use ieee.std_logic_textio.all; -- read std_ulogic etc
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library work;
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library work;
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use work.qfp_p.all;
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use work.qfp_p.all;
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use work.qfp32_add_p.all;
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use work.qfp32_add_p.all;
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use work.qfp32_misc_p.all;
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use work.qfp32_misc_p.all;
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use work.qfp32_unit_p.all;
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use work.qfp32_unit_p.all;
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use work.qfp32_test_p.all;
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use work.qfp32_test_p.all;
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library std;
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library std;
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use std.textio.all;
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use std.textio.all;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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entity qfp_unit_tb is
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entity qfp_unit_tb is
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end entity qfp_unit_tb;
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end entity qfp_unit_tb;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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architecture Behav of qfp_unit_tb is
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architecture Behav of qfp_unit_tb is
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type cmd_vector_t is array (natural range <>) of qfp_cmd_t;
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type cmd_vector_t is array (natural range <>) of qfp_cmd_t;
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constant cmds : cmd_vector_t(6 downto 0) :=
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constant cmds : cmd_vector_t(6 downto 0) :=
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(
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(
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(QFP_UNIT_ADD,QFP_SCMD_ADD), -- add
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(QFP_UNIT_ADD,QFP_SCMD_ADD), -- add
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(QFP_UNIT_ADD,QFP_SCMD_SUB), -- sub
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(QFP_UNIT_ADD,QFP_SCMD_SUB), -- sub
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(QFP_UNIT_MUL,"00"), -- mul
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(QFP_UNIT_MUL,"00"), -- mul
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(QFP_UNIT_RECP,"00"), -- recp
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(QFP_UNIT_RECP,"00"), -- recp
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(QFP_UNIT_MISC,QFP_SCMD_Q2I), -- convert qfp to integer
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(QFP_UNIT_MISC,QFP_SCMD_Q2I), -- convert qfp to integer
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(QFP_UNIT_MISC,QFP_SCMD_I2Q), -- convert integer to qfp
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(QFP_UNIT_MISC,QFP_SCMD_I2Q), -- convert integer to qfp
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(QFP_UNIT_DIV,"00") -- division
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(QFP_UNIT_DIV,"00") -- division
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);
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);
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-- component ports
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-- component ports
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signal clk : std_ulogic := '1';
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signal clk : std_ulogic := '1';
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signal reset_n : std_ulogic;
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signal reset_n : std_ulogic;
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signal cmd : qfp_cmd_t;
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signal cmd : qfp_cmd_t;
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signal idle : std_ulogic;
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signal idle : std_ulogic;
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signal start : std_ulogic;
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signal start : std_ulogic;
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signal regA : std_ulogic_vector(31 downto 0);
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signal regA : std_ulogic_vector(31 downto 0);
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signal regB : std_ulogic_vector(31 downto 0);
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signal regB : std_ulogic_vector(31 downto 0);
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signal result : std_ulogic_vector(31 downto 0);
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signal result : std_ulogic_vector(31 downto 0);
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signal gt : std_ulogic;
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signal gt : std_ulogic;
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signal z : std_ulogic;
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signal z : std_ulogic;
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signal complete : std_ulogic;
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signal complete : std_ulogic;
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signal i : integer;
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signal i : integer;
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file test_file : text;
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file test_file : text;
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signal test : qfp_test_t;
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signal test : qfp_test_t;
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begin -- architecture Behav
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begin -- architecture Behav
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-- component instantiation
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-- component instantiation
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DUT: entity work.qfp_unit
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DUT: entity work.qfp_unit
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generic map (
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generic map (
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config => qfp_config_all)
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config => qfp_config_all)
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port map (
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port map (
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clk_i => clk,
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clk_i => clk,
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reset_n_i => reset_n,
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reset_n_i => reset_n,
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cmd_i => cmd,
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cmd_i => cmd,
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ready_o => idle,
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ready_o => idle,
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start_i => start,
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start_i => start,
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regA_i => regA,
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regA_i => regA,
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regB_i => regB,
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regB_i => regB,
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result_o => result,
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result_o => result,
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cmp_gt_o => gt, -- regB > regA
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cmp_gt_o => gt, -- regB > regA
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cmp_z_o => z,
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cmp_z_o => z,
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complete_o => complete);
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complete_o => complete);
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-- clock generation
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-- clock generation
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clk <= not clk after 10 ns;
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clk <= not clk after 10 ns;
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-- waveform generation
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-- waveform generation
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process
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process
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variable l : line;
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variable l : line;
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variable test_as_var : qfp_test_t;
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variable test_as_var : qfp_test_t;
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variable dummy : character;
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variable dummy : character;
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begin
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begin
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reset_n <= '0';
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reset_n <= '0';
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regA <= (others => '0');
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regA <= (others => '0');
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regB <= (others => '0');
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regB <= (others => '0');
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start <= '0';
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start <= '0';
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cmd <= (QFP_UNIT_NONE,"00");
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cmd <= (QFP_UNIT_NONE,"00");
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file_open(test_file,"test.vector");
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file_open(test_file,"test.vector");
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i <= 0;
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i <= 0;
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test <= (X"00000000",X"00000000",'0','0',(X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000"));
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test <= (X"00000000",X"00000000",'0','0',(X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000"));
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wait for 33 ns;
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wait for 33 ns;
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reset_n <= '1';
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reset_n <= '1';
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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while not endfile(test_file) loop
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while not endfile(test_file) loop
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-- read entry from file
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-- read entry from file
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readline(test_file,l);
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readline(test_file,l);
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hread(l,test_as_var.a);
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hread(l,test_as_var.a);
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read(l,dummy);
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read(l,dummy);
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hread(l,test_as_var.b);
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hread(l,test_as_var.b);
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read(l,dummy);
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read(l,dummy);
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read(l,test_as_var.gt);
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read(l,test_as_var.gt);
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read(l,dummy);
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read(l,dummy);
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read(l,test_as_var.eq);
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read(l,test_as_var.eq);
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read(l,dummy);
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read(l,dummy);
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hread(l,test_as_var.results(6));
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hread(l,test_as_var.results(6));
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read(l,dummy);
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read(l,dummy);
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for k in 1 to 6 loop
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for k in 1 to 6 loop
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hread(l,test_as_var.results(6-k));
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hread(l,test_as_var.results(6-k));
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read(l,dummy);
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read(l,dummy);
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end loop; -- k
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end loop; -- k
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test <= test_as_var;
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test <= test_as_var;
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wait for 1 ns;
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wait for 1 ns;
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regA <= test.a;
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regA <= test.a;
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regB <= test.b;
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regB <= test.b;
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-- for each instruction
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-- for each instruction
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for j in 0 to cmds'length-1 loop
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for j in 0 to cmds'length-1 loop
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wait for 1 ns;
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wait for 1 ns;
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cmd <= cmds(j);
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cmd <= cmds(j);
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start <= '1';
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start <= '1';
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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start <= '0';
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start <= '0';
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if complete = '0' then
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if complete = '0' then
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wait until rising_edge(clk) and complete = '1';
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wait until rising_edge(clk) and complete = '1';
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end if;
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end if;
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assert result = test.results(j) report "result error" severity failure;
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assert result = test.results(j) report "result error" severity failure;
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if j = cmds'length-2 then -- if op = sub
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if j = cmds'length-2 then -- if op = sub
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assert gt = test.gt and z = test.eq report "compare flag error" severity failure;
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assert gt = test.gt and z = test.eq report "compare flag error" severity failure;
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end if;
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end if;
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end loop; -- j
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end loop; -- j
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i <= i+1;
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i <= i+1;
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end loop;
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end loop;
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file_close(test_file);
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file_close(test_file);
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wait;
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wait;
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end process;
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end process;
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end architecture Behav;
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end architecture Behav;
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