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Raptor CPU Core Reference
SHAPE \* MERGEFORMAT
Robert Finch
2007
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Revision History
Rev.DateAuthorDescription1.02005-08-18Robert FinchFirst Draft1.12007-06-28Robert FinchSwitched to SETHI, SETLO, added data type field1.22012-04-26Robert Finch32 regs
Raptor CPU Core 2007 Robert Finch HYPERLINK "http://www.birdcomputer.ca/index.html" Home
Table of Contents
TOC \o "1-3" \h \z \u HYPERLINK \l "_Toc170779354" 1 Overview PAGEREF _Toc170779354 \h 7
HYPERLINK \l "_Toc170779355" 1.1 Design Objectives PAGEREF _Toc170779355 \h 7
HYPERLINK \l "_Toc170779356" 1.2 Unique Features PAGEREF _Toc170779356 \h 8
HYPERLINK \l "_Toc170779357" 1.3 Definitions PAGEREF _Toc170779357 \h 8
HYPERLINK \l "_Toc170779358" 2 Programming Model PAGEREF _Toc170779358 \h 9
HYPERLINK \l "_Toc170779359" 2.1 Execution Contexts PAGEREF _Toc170779359 \h 9
HYPERLINK \l "_Toc170779360" 2.2 General Registers PAGEREF _Toc170779360 \h 9
HYPERLINK \l "_Toc170779361" 2.2.1 Register Format PAGEREF _Toc170779361 \h 10
HYPERLINK \l "_Toc170779362" 2.2.2 Floating Point Format PAGEREF _Toc170779362 \h 10
HYPERLINK \l "_Toc170779363" 2.3 Program Counter (R45) PAGEREF _Toc170779363 \h 11
HYPERLINK \l "_Toc170779364" 2.3.1 Instruction Packets PAGEREF _Toc170779364 \h 11
HYPERLINK \l "_Toc170779365" 2.3.2 Program Counter Format PAGEREF _Toc170779365 \h 11
HYPERLINK \l "_Toc170779366" 2.3.3 Program Counter Relative Addressing PAGEREF _Toc170779366 \h 11
HYPERLINK \l "_Toc170779367" 2.4 Special Purpose Registers PAGEREF _Toc170779367 \h 12
HYPERLINK \l "_Toc170779368" 2.4.1 Status Register (SR) PAGEREF _Toc170779368 \h 13
HYPERLINK \l "_Toc170779369" 2.4.2 Core Number (COR) PAGEREF _Toc170779369 \h 14
HYPERLINK \l "_Toc170779370" 2.4.3 Version Register PAGEREF _Toc170779370 \h 15
HYPERLINK \l "_Toc170779371" 2.4.4 Random Number Register (RND) PAGEREF _Toc170779371 \h 16
HYPERLINK \l "_Toc170779372" 2.4.5 #32 Vector Table Base Address Register (VBA) PAGEREF _Toc170779372 \h 17
HYPERLINK \l "_Toc170779373" 2.4.6 #5 Tick Count Register (TIC) PAGEREF _Toc170779373 \h 18
HYPERLINK \l "_Toc170779374" 2.4.7 Active Executive Context (AXC) PAGEREF _Toc170779374 \h 19
HYPERLINK \l "_Toc170779375" 2.4.8 Execution Pattern Registers (EP0-3) PAGEREF _Toc170779375 \h 19
HYPERLINK \l "_Toc170779376" 2.4.9 #30 Floating Point Status and Control Register (FPC) PAGEREF _Toc170779376 \h 20
HYPERLINK \l "_Toc170779377" 3 Hyper-Threading PAGEREF _Toc170779377 \h 22
HYPERLINK \l "_Toc170779378" 4 Interrupts PAGEREF _Toc170779378 \h 22
HYPERLINK \l "_Toc170779379" 4.1 Interrupt Vector Table PAGEREF _Toc170779379 \h 23
HYPERLINK \l "_Toc170779380" 5 Program Flow Control PAGEREF _Toc170779380 \h 24
HYPERLINK \l "_Toc170779381" 5.1 Compare Operation PAGEREF _Toc170779381 \h 24
HYPERLINK \l "_Toc170779382" 5.2 Branches PAGEREF _Toc170779382 \h 25
HYPERLINK \l "_Toc170779383" 5.2.1 Overview PAGEREF _Toc170779383 \h 25
HYPERLINK \l "_Toc170779384" 5.2.2 Targets PAGEREF _Toc170779384 \h 25
HYPERLINK \l "_Toc170779385" 5.2.3 Branch Conditions PAGEREF _Toc170779385 \h 26
HYPERLINK \l "_Toc170779386" Branch Conditions PAGEREF _Toc170779386 \h 26
HYPERLINK \l "_Toc170779387" 5.3 Method Invocation (Jumps and Calls) PAGEREF _Toc170779387 \h 27
HYPERLINK \l "_Toc170779388" 5.4 System Calls and Interrupts PAGEREF _Toc170779388 \h 27
HYPERLINK \l "_Toc170779389" 6 Datapath Operations PAGEREF _Toc170779389 \h 28
HYPERLINK \l "_Toc170779390" 6.1 Immediate Constants PAGEREF _Toc170779390 \h 28
HYPERLINK \l "_Toc170779391" 6.2 Integer Operations PAGEREF _Toc170779391 \h 28
HYPERLINK \l "_Toc170779392" 6.2.1 Addition / Subtraction / Multiply / Divide PAGEREF _Toc170779392 \h 28
HYPERLINK \l "_Toc170779393" 6.2.2 Comparisons PAGEREF _Toc170779393 \h 28
HYPERLINK \l "_Toc170779394" 6.2.3 Logical Operations PAGEREF _Toc170779394 \h 28
HYPERLINK \l "_Toc170779395" 6.2.4 Shifts PAGEREF _Toc170779395 \h 28
HYPERLINK \l "_Toc170779396" 6.2.5 BitField Operations PAGEREF _Toc170779396 \h 28
HYPERLINK \l "_Toc170779397" 6.3 Floating Point Operations PAGEREF _Toc170779397 \h 29
HYPERLINK \l "_Toc170779398" 6.3.1 Addition / Subtraction / Multiply / Divide PAGEREF _Toc170779398 \h 29
HYPERLINK \l "_Toc170779399" 6.3.2 Absolute Value / Negation / Sign Determination / Fractional Extraction PAGEREF _Toc170779399 \h 29
HYPERLINK \l "_Toc170779400" 6.3.3 Numeric Conversions PAGEREF _Toc170779400 \h 29
HYPERLINK \l "_Toc170779401" 6.3.4 Comparisons PAGEREF _Toc170779401 \h 29
HYPERLINK \l "_Toc170779402" 6.3.5 Other Instructions PAGEREF _Toc170779402 \h 29
HYPERLINK \l "_Toc170779403" 7 Memory Operations PAGEREF _Toc170779403 \h 30
HYPERLINK \l "_Toc170779404" 7.1 Endian PAGEREF _Toc170779404 \h 30
HYPERLINK \l "_Toc170779405" 7.2 Operations PAGEREF _Toc170779405 \h 30
HYPERLINK \l "_Toc170779406" 7.3 Alignment PAGEREF _Toc170779406 \h 30
HYPERLINK \l "_Toc170779407" 7.4 Memory Map PAGEREF _Toc170779407 \h 30
HYPERLINK \l "_Toc170779408" 8 Opcode Formats PAGEREF _Toc170779408 \h 31
HYPERLINK \l "_Toc170779409" 8.1 Instruction Layout PAGEREF _Toc170779409 \h 31
HYPERLINK \l "_Toc170779410" 8.2 Opcode Formats PAGEREF _Toc170779410 \h 32
HYPERLINK \l "_Toc170779411" 8.3 Detailed Opcode Formats PAGEREF _Toc170779411 \h 33
HYPERLINK \l "_Toc170779412" 8.4 Data Type PAGEREF _Toc170779412 \h 34
HYPERLINK \l "_Toc170779413" 8.5 Opcode Maps PAGEREF _Toc170779413 \h 35
HYPERLINK \l "_Toc170779414" 8.5.1 Major Instruction Group PAGEREF _Toc170779414 \h 35
HYPERLINK \l "_Toc170779415" 8.5.2 Register Instruction Group PAGEREF _Toc170779415 \h 36
HYPERLINK \l "_Toc170779416" 8.5.3 Miscellaneous Control PAGEREF _Toc170779416 \h 37
HYPERLINK \l "_Toc170779417" 8.5.4 Floating Point Operations PAGEREF _Toc170779417 \h 38
HYPERLINK \l "_Toc170779418" 9 Instruction Set Description PAGEREF _Toc170779418 \h 40
Documentation Notes
This document refers to an eight bit quantity as a byte, a sixteen bit quantity as a character, a thirty-two bit quantity as a half-word, and a sixty-four bit quantity as a word.
Overview
The Raptor is a powerful multi-context 64 bit processor that represents a generational refinement of processor architecture. The processor contains 32, 32 bit general purpose registers which may be used for either integer or floating point operations. The Raptor uses a fixed 42 bit instruction and handles 8, 16, 32, and 64 bit data within a 64 bit address space.
Design Objectives
This processor is targeted towards high performance operation as a general purpose processor. Following are some of the criteria that were used on which to base the design.
Designed for Superscalar operation - the ability to execute more than one instruction at a time. To achieve high performance it is generally accepted that a processor must be able to execute more than a single instruction in any given clock cycle.
Simplicity - architectural simplicity leads to a design that is easy to implement resulting in reliability and assured correctness along with easy implementation of supporting tools such as compilers. Simplicity also makes it easier to obtain high performance and results in lower overall cost.Extensibility - the design must be extensible so that features not present in the first release can easily be added at a later date.
Low Cost
This design meets the above objectives in the following ways. The instruction set has been designed to minimize the interactions between instructions, allowing instructions to be executed as independent units for superscalar operation. There are a sufficient number of registers to allow the compiler to schedule parallel processing of code. A reasonably large general purpose register set is available making the design reasonably compatible with many existing compilers and assemblers. Where needed, additional specialized instructions have been added to the processor to support a sophisticated operating system and interrupt management.
Unique Features
Forty-two bit wide opcodes. The wider opcode format accommodates more registers, more operations, and larger constants while allowing for future extensibility.
Combined compare and branch operations. This is a code compression technique that both reduces code size and increases performance.
Evaluation of logical operations during branch condition determination in addition to the usual relational operations. This is another code compression and thus performance enhancing feature.
The processor supports mystery logical operations where the exact operation to be performed is unknown until runtime, at which point the operation to be performed is determined by the value of a register. This is useful in applications such as raster graphics operations and ciphering.
Definitions
Instruction Packet:
An instruction packet is a sixteen byte aligned block of memory that contains three instructions.
Programming Model
Execution Contexts
Internally the Raptor uses multiple register contexts in order to support hyper-threading. However, only a single set of registers is visible for programming at one time. A register context consists of the general registers and a program counter.
General Registers
There are 32 sixty-four bit registers - r0 to r31. All registers are available in supervisor mode. In user mode only registers r0 to r47 are available. Twenty-eight of the registers are available for any use. The other registers have dedicated uses.
R0 always reads as zero and cant be updated.
R45 reflects the address of the instruction and cant be updated. It may be used to generate program counter relative addresses.
R31 is automatically updated by hardware to store the current program counter when a subroutine call occurs.
Code
(6 bits)Register NameDescription / Suggested Usage Convention0R0 or 0This register always reads as zero1R1First return value / first argument2R2Second return value / second argument3 to 25R3-R25Application usage.26C0constant hold27C1constant hold28C2constant hold29PCProgram counter. This is an alias for the instruction address. This register is read only.30SPStack Pointer. Any hardware based stack operations will use this register.31RAReturn Address register. This register is used to store the return address from a subroutine or method call.
Programming Model
Special Registers63 23 22 063 0Program CounterPBPCR0/0Link RegisterPBPCR1Except. AddressPBPCR2R3R4System Vec.SVR5R6R7R8R9R10R1163 0R12Loop CounterLCR13TickTICKR14R15R16R17R18R19R20R21R22R23R24R25R26R27R28R29R30R31/LR
General purpose register R0 always contains the value zero.
The Tick register increments with every clock cycle. It may be set using the mtspr instruction.
Register Format
Integer values in registers are represented in twos complement format.
6362 0SignvalueFloating Point Format
Floating point values are represented as IEEE-754 standard single precision values. This is a sign-magnitude format.
SignExponentMantissa3130 2322 0
Program Counter
Instruction Packets
An instruction packet is just a fancy name for an aligned sixteen byte block of memory that contains three instructions.
The processor uses forty-two bit instructions with opcodes packed three per 128 bits as shown in the format below. There are two unused bits which should be set to zero.
127125 8483 4241 0--Opcode Slot 2Opcode Slot 1Opcode Slot 0Instruction addresses are composed of a packet number which indicates which sixteen byte memory area contains the instruction, and a slot number. The instruction slot number is one of zero, one, or two. The slot number indicates which opcode within the packet is active.
Any one of the opcodes within an instruction packet may be used as a target address. The program counter contains a packet address and slot number. As a program is executed the slot number increments from zero to one to two, then back to zero, while the packet number increments when the slot number changes from two to zero. The packet number matches with a sixteen-byte aligned data address. The slot number just indicates which opcode within the packet is active.
Program Counter Format
63 21 0Instruction Packet NumberSlot Number
Program Counter Relative Addressing
R29 contains the value of the program counter for the instruction currently being executed. R29 may be used to form program counter relative addresses.
Execution Contexts
There is a separate program counter register for each execution context. All program counter registers are initialized to the reset vector ($FFFF_FFFF_FFFF_FFF0) on reset. A context jump table may be setup in software to vector to different code by testing the contents of the active execution context (AXC) register.
Special Purpose Registers
There are several special purpose registers within the processor. The processor model may be extended to support additional functionality at a later date.
CodeRegister NameDescription0SRStatus Register1CORCORe number2THR{this register is reserved thread number}3VERProcessor Version / Features - major, minor, revision4RNDrandom number register5TICtick count registerExecution Context Control8EP0Execution Pattern9EP110EP211EP312AXCactive execution context15PTAPage Table Address1431{these register are reserved}30FPCfloating point control32VBAvector table base address33-47{reserved library registers}TLBPageMaskControls the memory page sizeTLBVirtAddrTLBPhysAddrTLBASIDASIDAddress space identifier (process id)These registers may be accessed using the HYPERLINK \l "TRS"TRS and HYPERLINK \l "TSR"TSR commands.
Status Register (SR)
This register contains bits that control the overall operation of the processor or reflect the processors state. Bits are included for interrupt masking, and system / application mode indicator. This register is split into two halves with both halves having the same format. The lower half of the register is what determines how the processor works. The upper half of the register maintains a backup copy of the lower half for interrupt processing. There are instructions provided for manipulating the interrupt mask. ( HYPERLINK \l "EI" EI, HYPERLINK \l "DI" DI, and HYPERLINK \l "RIF" RIF).
31..161514131211..0same format as 15..0Interrupt MaskReservedSystem / Application Mode IndicatorFloat Except. EnablereservedIM~SFXE~
Core Number (COR)
This register is used to identify which core is active in a multi-core system.
31 2827 2423 1615 0Board4Core4Process8Thread16
Version Register
This register contains the major, minor, and revision numbers of the processor. This register is read only.
31 2423 1615 87 0MajorMinorRevision{Reserved}1000
Random Number Register (RND)
This register contains a pseudo-random value based on a LCG (linear congruential generator). The value may be seeded by writing to the register. The register may contain either a random 32 bit integer or rand floating point value between 0.0 and 1.0. The GRAN instruction is used to generate a 32 bit integer value. The GRAF instruction is used to generate a floating point value.
LCG Parameters 32 bit
next = (cur * a + c) mod M
a = 69069 decimal
c = 1
M = 2^32
31 0random number
63 0random number
Vector Table Base Address Register (VBA)
This register establishes the base address of the interrupt vector table in memory. At reset it is set to zero, the first 4KB page of memory or $0000. The low order thirteen bits of this register are always zero. The vector number from the system call instruction is combined with this register to form the address from which the vector should be taken. This register is read only unless the processor is kernel mode.
63 1312 0FFFF_FFFF_FFFF_E000 Tick Count Register (TIC)
This register contains a count of the number of clock cycles that have passed since the last time the register was written. It may be useful for performance monitoring. This register is read only unless the processor is supervisor mode.
64 Bit Implementation:63 0clock cycle count
Active Executive Context (AXC)
This register contains a number identifying the currently active executive context. This register is read-only.
31 4 3 00Number
Execution Pattern Registers (EP0-3)
This set of four registers records the frequency of execution for each context. Each register is divided into eight buckets which record a four bit execution context number.
This set of registers is just a holding place for the pattern, in order to make the pattern active the execution pattern transfer register (EPT) must be updated.
Contexts are executed based on their frequency of appearance in the execution pattern registers.
31 2827 2423 2019 1615 1211 87 43 0EP0CTX7CTX6CTX5CTX4CTX3CTX2CTX1CTX0EP1CTX15CTX14CTX13CTX12CTX11CTX10CTX9CTX8EP2CTX23CTX22CTX21CTX20CTX19CTX18CTX17CTX16EP3CTX31CTX30CTX29CTX28CTX27CTX26CTX25CTX24
On reset, the execution pattern registers are all set to zero. This causes context zero to be the only executing context. The execution pattern registers must be set in order to allow other contexts to run.
The CTX0 bucket is fixed at context zero it canot be altered. This guarentees that context zero (the kernel context) always gets a chance to run.
Floating Point Status and Control Register (FPC)
This register contains control values for floating point and floating point status bits.
BitSymbolDescription31:30RMrmrounding mode29{reserved}28E5inexe- inexact exception enable27E4dbzxe- divide by zero exception enable26E3underxe- underflow exception enable25E2overxe- overflow exception enable24E1invopxe- invalid operation exception enable23NSns- non standard floating point indicatorResult Status22fractie- the last instruction (arithmetic or conversion) rounded intermediate result (or caused a disabled overflow exception)21RArawayzrounded away from zero (fraction incremented) 20SCCdenormalized, negative zero, or quiet NaN19SLneg <the result is negative (and not zero)18SGpos >the result is positive (and not zero)17SEzero =the result is zero (negative or positive)16SIinf ?the result is infinite or quiet NaNException Occurrence15X6swt{reserved} - set this bit using software to trigger an invalid operation14X5inerx- inexact result exception occurred (sticky)13X4dbzx- divide by zero exception occurred12X3underx- underflow exception occurred11X2overx- overflow exception occurred10X1giopx- global invalid operation exception set if any invalid operation exception has occurred9GXgx- global exception indicator set if any enabled exception has happened8SXsumx- summary exception set if any exception could occur if it was enabled
- can only be cleared by softwareException Type Resolution7X1Tcvt- attempt to convert NaN or too large to integer6X1Tsqrtx- square root of non-zero negative 5X1TNaNCmp- comparison of NaN not using unordered comparison instructions4X1Tinfzero- multiply infinity by zero3X1Tzerozero- division of zero by zero2X1Tinfdiv- division of infinities1X1Tsubinfx- subtraction of infinities 0X1Tsnanx- signaling NaN
RMRounding Mode0round towards nearest even1round towards zero (truncate)2round towards positive infinity3round towards negative infinity* add floating point invalid operation exception instruction
TLBPageMask
The TLBPageMask register contains a mask that controls which address bits are significant during a TLB lookup. If a mask bit is 1 then that address bit is not significant for comparison purposes. This allows the size of memory management pages to be varied.
63 3231 1312 0----Page Mask----
MaskPage Size00000000000000000008kB000000000000000001116KB00000000000000111164kB000000000000111111256kB0000000000111111111MB00000000011111111114MB00000001111111111116MB00000011111111111164MB000011111111111111256MB0011111111111111111GB1111111111111111114GBTLBPhysPage
The TLBPhysPage register is a holding register that contains the physical address for an associated virtual address. This register is transferred to or from the TLB by TLB instructions.
63 1312 0Physical Page Address----
TLBVirtPage
The TLBVirtPage register is a holding register that contains the virtual address for an associated physical address. This register is transferred to or from the TLB by TLB instructions.
63 1312 0Virtual Page Address----
TLBASID
The TLBASID register is a holding register that contains the address space identifier (ASID) , valid, dirty, global, and cachability bits associated with a TLB entry. This register is transferred to or from the TLB by TLB instructions.
63 16 15 86 4 210-----ASIDCGDV Hyper-Threading
The Raptor supports hyper-threading via the use of multiple contexts. The processor can switch in a controlled fashion between contexts on a cycle-by-cycle basis. Which context is active during any clock cycle depends on the list configured in the execution pattern registers (EPx). The core cycles through the entries in the execution registers using the context number (0-15) stored in the list register to determine the next context to use during execution. Execution context zero is reserved for processing hardware exceptions. When a hardware exception occurs, the processor automatically forces execution context zero to become active, overriding the contents of the execution pattern list.
Interrupts
Interrupts cause an automatic transfer of processor execution to context zero.
This processor supports interrupts and exceptions in the form of a system call instruction. When a hardware interrupt or program exception occurs the appropriate system call instruction is forced into the processor's internal instruction pipeline (this is accomplished by hardware internal to the processor). There are several pre-defined exception numbers for specific vectors in order to support hardware interrupts as listed in the table below. An exception vectors to the handler whose address is located by combining the exception number (a field in the system call instruction) with the base address stored in the vector base address register (VBA). The REX1 (return from exception) instruction is used to return from an exception routine.
Occurrence of an exception results in the status register being copied to the back up version, the maskable interrupt mask being set to disable further interrupts, and the exception return address being copied to XRA, so that these may be restored by the exception return operation. The processor is also switched to system mode, which enables registers and instructions available only to system mode.
Interrupt Vector Table
The interrupt vector table is a table of 512 entries containing the addresses of routines that may be called using the system call instruction (SYS). They may also be called during hardware interrupt processing. The location of the table in memory is controlled by the vector base address register (VBA) which on reset is set to $0000_0000_0000_0000, effectively placing the vector table in the first 4KiB of memory.
The reset vector and non-maskable interrupt vectors are not governed by the VBA and have fixed addresses in memory of $FFFF_FFFF_FFFF_FFF0 and $FFFFFFFF_FFFF_FFE0 respectively.
The last 64 entries in the table are reserved for interrupts that the processor might generate. The remaining entries are free for use as needed by the operating system.
Entry #DescriptionOperating System ( reserved)0BIOS (32 reserved)416RTC417KeyboardNetworkMass Storage447Processor Hardware Exceptions (64 reserved)448spurious interrupt449hardware interrupt level 1450hardware interrupt level 2......479hardware interrupt level 31480-487{reserved}488division by zero489-493{reserved}494illegal instruction address495unimplemented instruction496-509{reserved}510reserved - Non-maskable interrupt vector511reserved - Reset Vector Program Flow Control
There are four basic flow control instructions (JAL, Bcc, JMP, CALL, RET, and SYS).
JMP is an unconditional program flow transfer instruction.
JAL is an unconditional program flow transfer instruction.
The Bcc instructions are conditional transfers.
The RET instruction is a return instruction that also performs an add operation,
and the SYS instruction is used to invoke exception handlers.
The instruction prefix may be used with the JMP and CALL instructions to allow a full 64 bit address to be formed.
Compare Operation
Conditional program flow instructions are guided by comparisons. The comparisons may be performed directly by the branch instruction, or via one of the datapath comparison instructions such as a floating point comparison. The compare instruction compares either two registers or a register and an immediate value and writes the result of the comparison to the target register. The target register will be written with a one to represent a true value or a zero for false. There are six basic relational comparison operations than can be performed (equal, not equal, less than, less than or equal, greater than or greater than or equal).
There are ten integer comparison instructions which cover the standard relational comparisons for both signed and unsigned values.( HYPERLINK \l "CLT" SLT, HYPERLINK \l "CGE" SGE, HYPERLINK \l "CLE" SLE, HYPERLINK \l "CGT" SGT, HYPERLINK \l "CLT" SLTU, HYPERLINK \l "CGE" SGEU, HYPERLINK \l "CLE" SLEU, HYPERLINK \l "CGT" SGTU, HYPERLINK \l "CEQ" SEQ, HYPERLINK \l "CNE" SNE).
There are two additional comparison operations ( HYPERLINK \l "CMP" CMP, HYPERLINK \l "CMP" CMPU) which perform a relational comparison between a register and either another register or immediate value; and place the result of the comparison to the target register. For these two instructions the target register is written with -1 to indicate the first operand is less than the second, 0 to indicate that both operands are the same, and +1 to indicate that the first operand is greater than the second. CMP performs a signed comparison, CMPU performs an unsigned comparison.
Branches
Overview
Branches are the most frequent form of program flow control operation and are usually performed in a conditional manner.Branches are integrated with compare operations allowing a comparison and a branch to be processed as one unit for improved code density and performance.
The processor includes a (2,2) 64 entry correlating branch outcome predictor. This allows many branch instructions to execute in only a single clock cycle.
Targets
Branch target addresses are determined in one of two fashions; the branch target may be an absolute address stored in a register, or it may be a relative address specified by a field in the branch instruction itself. The processor allows a twelve bit target address field which covers virtually 100% of branch cases.
Packet-Relative Addresses
When the branch target is not coming from a register, the branch target field contains a packet relative address and an absolute instruction slot number. This mechanism allows for easy relocation of code on packet boundaries. The twelve bit target field is split into two subfields a relative packet displacement and the instruction slot number. The relative packet displacement is used to determine which instruction packet is the target relative to the packet of the branch instruction. The slot number indicates which slot within the target packet is the target for the branch. The slot number must have a value of 0, 1, or 2.
Packet displacements may vary from -512 to +511 packets.
Target Field Specifier (non-register targets)
11 21 0Packet DisplacementSlot
Branch Conditions
A standard set of branch conditions is provided, outlined in the table below. The branch conditional is determined by comparing the two registers or a register and a small immediate value specified by the branch instruction. The branch architecture is such that it is possible to branch based directly on a value in a register. The ISA features logical tests in addition to the regular relational tests.
Branch Conditions
MnemonicDescriptionConditional TestHYPERLINK \l "Bcc"BLTBranch if Less Thana < bHYPERLINK \l "Bcc"BGEBranch if Greater than or Equala >= bHYPERLINK \l "Bcc"BLEBranch if Less than or Equala <= bHYPERLINK \l "Bcc"BGTBranch if Greater Thana > bHYPERLINK \l "Bcc"BEQ / BXNORBranch if Equala == bHYPERLINK \l "Bcc"BLTUBranch if Less Thana < bHYPERLINK \l "Bcc"BGEUBranch if Greater than or Equala >= bHYPERLINK \l "Bcc"BLEUBranch if Less than or Equala <= bHYPERLINK \l "Bcc"BGTUBranch if Greater Thana > bHYPERLINK \l "Bcc"BNE / BXORBranch if Not Equala <> bHYPERLINK \l "Bcc"BANDBranch if both truea and bHYPERLINK \l "Bcc"BORBranch if either truea or b
Method Invocation (Jumps and Calls)
Methods may be invoked by the HYPERLINK \l "CALL"JAL. instruction. JAL automatically stores the method return address in the return address link register (R31). A method return instruction (HYPERLINK \l "RET"RET) is used to return from a method by restoring the program counter from the return address register.
The HYPERLINK \l "JAL"JAL instruction is a simple powerful instruction common in many newer architectures that provides for most common program flow transfer operations that are not covered by branches. The JAL instruction is a generic unconditional program flow control instruction. This single instruction can perform regular jump, method call and return operations, interrupt call and return operations, using absolute or register indirect addresses. The default form of the JAL instruction where the return address is stored in the return address register (R31) may referred to as a CALL in assembly language. When a jump (HYPERLINK \l "JMP"JMP) is required, the register to store the return address in may be specified as R0 (R0 will not be updated).
The JAL instruction may be used to perform program counter relative calls with the use of the program counter alias register, or program offset based calls by loading a register with the address of the program. JAL may target absolute addresses in memory by setting the target register field to R0.
JAL forms a target address by adding a register and immediate value, or two registers. The address generated is treated as an instruction address (Its not a byte address).
System Calls and Interrupts
Calls to the operating system or interrupt routines may be made using the system call (HYPERLINK \l "SYS"SYS) instruction. Returns from system routines may be made using the HYPERLINK \l "RTX"ERET instruction. System, interrupt calls and returns cause transfers between processor control bits and their alternates. The system call instruction automatically places the processor in system mode.
Datapath Operations
Immediate Constants
Large immediate values used in integer arithmetic operations may be created using the constant prefix instruction. This instruction adds thirty-nine more significant bits to the immediate constant thats encoded in the following instruction. The immediate prefix is useful only for instructions that support at least a thwenty-five bit constant field. This includes arithmetic, load and store, and jump and call instructions.
Integer Operations
Integers are represented using twos complement notation.
Addition / Subtraction / Multiply / Divide
Basic addition (HYPERLINK \l "ADD"ADD) and subtraction (HYPERLINK \l "SUB"SUB) operations are supported. Addition and subtraction work with both signed and unsigned values. The ADD and SUB instructions will cause an exception to occur if there is an overflow condition. The unsigned ADDU and SUBU instructions can be used as an alternate and do not cause an overflow exception.
Multiplication and division of signed numbers are supported by the ISA with the HYPERLINK \l "MUL"MUL, HYPERLINK \l "MULH"MULH and HYPERLINK \l "DIV"DIV instructions A remainder function (HYPERLINK \l "MOD"MOD) is also available. The MULH instruction returns the high order thirty-two bits of a signed multiply operation.
Comparisons
There are ten comparison instructions performing signed and unsigned comparisons between two registers or a register and an immediate value ( HYPERLINK \l "Ccc" SLT, HYPERLINK \l "Ccc" SLE, HYPERLINK \l "Ccc" SGT HYPERLINK \l "Ccc" SGE, HYPERLINK \l "Ccc" SLTU, HYPERLINK \l "Ccc" SLEU, HYPERLINK \l "Ccc" SGTU HYPERLINK \l "Ccc" SGEU, HYPERLINK \l "Ccc" SEQ, and HYPERLINK \l "Ccc" SNE).
Logical Operations
The processor supports a standard set of logical operations including and (HYPERLINK \l "AND"AND), or (inclusive)(HYPERLINK \l "OR"OR), and exclusive or (HYPERLINK \l "XOR"XOR). An additional derived operation is HYPERLINK \l "NOT"NOT which is an alternate form of the XOR instruction. The primary logical operations support both register and immediate forms. There are three more additional secondary logical operations (HYPERLINK \l "NAND"NAND, HYPERLINK \l "NOR"NOR, and HYPERLINK \l "XNOR"XNOR) which have only register formats.
Shifts
The ISA supports a full complement of shift instructions. Left shifts are supported via the HYPERLINK \l "SHL"SHL instruction. Right shifts are supported with arithmetic (HYPERLINK \l "ASR"ASR) and logical (HYPERLINK \l "SHR"SHR) shifts. Rotates are supported via the rotate left HYPERLINK \l "ROL"ROL and rotate right HYPERLINK \l "ROR"ROR instructions.
BitField Operations
The processor has support for bitfield operations via the HYPERLINK \l "BFINS"BFINS (bitfield insert) and HYPERLINK \l "BFEXT"BFEXT (bitfield extract) instructions. An additional bitfield operation is the HYPERLINK \l "BFCLR"BFCLR (bitfield clear) instruction which is an extended mnemonic for the BFINS instruction.
Floating Point Operations
Addition / Subtraction / Multiply / Divide
Basic addition (HYPERLINK \l "ADD"FADD), subtraction (HYPERLINK \l "SUB"FSUB), multiplication ( HYPERLINK \l "FMUL" FMUL) and division ( HYPERLINK \l "FDIV" FDIV) operations are supported.
Absolute Value / Negation / Sign Determination / Fractional Extraction
Absolute value (FABS), negation (FNEG), sign determination (FSGN), fractional extraction (FMAN) are supported.
Numeric Conversions
Conversions between integer and floating point values are handled with the float-to-int (F2INT) and int-to-float instructions (INT2F).
Comparisons
There are five floating point comparison instructions; four are relational comparisons, the fifth tests for ordering of operands. (FCLT, FCLE, FCEQ, FCNE, FCOR). The floating point comparisons compare the values in two registers and set the target register to true if the comparison is true. Other comparisons may be synthesized from existing instructions; for example, by switching the operands around.
Other Instructions
A random floating point value may be obtained using the GRAF (Get RAndom Float) instruction.
Memory Operations
Endian
The Raptor is a little endian processor. The least significant byte is at the lowest address.
Operations
The Raptor is a load / store architecture; the only operations accessing memory are load and store operations. The processor supports byte (8 bit), character (16 bit), half-word (32 bit), and word (64 bit) loads and stores of data to memory.
The ISA supports address update forms of the load / store instructions, where the addressing register is updated with the calculated effective address after the load / store operation is complete. Indexed address mode is also supported. There are instructions which automatically unpack and pack floating point values for transfer to or from memory.
There are numerous load and store instructions (not all are shown) which support the following operations:
operationsuffix characterSample Mnemonicsdefault / sign extension (loads)noneHYPERLINK \l "LB"LB HYPERLINK \l "LH"LH HYPERLINK \l "LW"LW HYPERLINK \l "SB"SB HYPERLINK \l "SH"SH HYPERLINK \l "SW"SWzero extension (loads)ZHYPERLINK \l "LBZ"LBZ HYPERLINK \l "LHZ"LHZindexed operationLB LH LW SB SH SW FLS FSS
LBZ LHZ floating point conversionLF SF
Data Alignment 32-bit
Memory is byte addressable; character, half-word and word accesses must be aligned on their respective address boundaries.
Bytes may be loaded from any memory address.
3210
Characters may be loaded from any memory address, except an address where the least significant two bits are 11.
201
CLB
If the address ends in 11, then the byte is loaded into register bits 9 to 15; otherwise the instruction is treated as NOP.
0
6420531
01234
23
Data Alignment
Memory is byte addressable; character, half-word and word accesses must be aligned on their respective address boundaries.
Bytes may be loaded from any memory address.
76543210
Characters may be loaded from any memory address, except an address where the least significant three bits are 111.
When a character is loaded from an address ending in 111, the load is treated as if it were a byte load instruction. The lowest byte of the target register is loaded.
CLC
If the address ends in 11, then a byte is loaded into register bits 8 to 15; otherwise the instruction is treated as NOP.
6420531
CLH
If the address ends in 101, then a byte is loaded into register bits 24 to 31;
If the address ends in 110, then a character is loaded into register bits 16 to 31;
If the address ends in 111, then a character is loaded into register bits 8 to 31;
otherwise the instruction is treated as NOP.
01234
23
LCA
LCZA
If the address ends in 111, then 8 bits are loaded into register bits 8 to 15; otherwise the instruction is treated as NOP.
LHA
LHZA
If the address ends in 101, then a byte is loaded into register bits 24 to 31;
If the address ends in 110, then a character is loaded into register bits 16 to 31;
If the address ends in 111, then a character is loaded into register bits 8 to 31;
otherwise the instruction is treated as NOP.
LWA
If the address ends in 001, then 56 bits are loaded into register bits 8 to 63;
If the address ends in 010, then 48 bits are loaded into register bits 16 to 63;
If the address ends in 011, then 40 bits are loaded into register bits 24 to 63;
If the address ends in 100, then 32 bits are loaded into register bits 32 to 63;
If the address ends in 101, then 24 bits are loaded into register bits 40 to 63;
If the address ends in 110, then 16 bits are loaded into register bits 48 to 63;
If the address ends in 111, then 8 bits is loaded into register bits 56 to 63;
otherwise the instruction is treated as NOP.
Memory Map
The processor supports a 64 bit (or 2^64 Bytes) address space.
FFFx_xxxx_xxxx_xxxxUnmapped FFEx_xxxx_xxxx_xxxxUnmappedFFDx_xxxx_xxxx_xxxxUnmappedFFCF_FFFF_FFFF_FFFFmapped0000_0000_0000_0000
TLB
The processor uses a 16 entry TLB (translation lookaside buffer) in order to support virtual memory. The TLB supports variable page sizes from 8kB to 4GB.
TLB Entries:
G = Global
ASID = address space identifier
C = cachability bits
D = dirty bit
V = valid bit
If the G bit is set in the TLB entry, then the ASID field is ignored during the address comparison. Opcode Formats
Ideally from a compiler's perspective the ISA should be able to support three operand instructions (one destination, two sources) including cases where all three operands are registers in order to allow a compiler to allocate registers more efficiently. This is commensurate with current compiler technology. This ISA supports the ideal condition.
Instruction Layout
Opcodes are forty-two bits in size. Instructions are placed three per instruction packet which must be aligned on 16-byte (128 bit) addresses.
127 126125 8483 4241 00--Opcode Slot 2Opcode Slot 1Opcode Slot 01--Opcode Slot 2Opcode Slot 1Opcode Slot 02--Opcode Slot 2Opcode Slot 1Opcode Slot 0--30--Opcode Slot 2Opcode Slot 1Opcode Slot 031--Opcode Slot 2Opcode Slot 1Opcode Slot 0
Opcode Formats
There are several different opcode formats, see the subsequent tables for specific formats. The major opcode formats are shown below. All instructions begin with a seven bit field in the most significant bits which determines the major opcode grouping or instruction.
IMM-Type
Usage: IMM
Set register,
41 3938 0Opcode3immediate39
I-Type
Usage: Register-immediate instructions,
loads and stores with displacements,
jump and link
41 3534 3029 2524 0Opcode7RegA5RegT5immediate25
R-Type
Usage: Register-Register instructions and loads and stores using indexed addressing
41 3534 3029 2524 2019 76 0Opcode7RegA5RegB5RegT5----13Func7
B-Type
Usage: Branches
41 3534 3029 1817 0Opcode7RegA5target12Immediate18
BF Type
Usage: Bitfield operations
41 3534 2928 2322 1716 1211 65 0Opcode7RegA5RegT5RegC5Opcode8Width6Start6
Detailed Opcode Formats
Op4Imm10Rt6Imm23SETOp6Typ2Ra6Rt6Imm22ImmOp6Typ2Ra6Rt6Rc6Op10Rb6RegOp6Typ2Ra6Rt6Rc6Op4Wd6St6BFCOp6Typ2Ra6Rt6Rc6Op4Wd6Rb6BFROp6Typ2Ra6target12Imm16BranchOp6Typ2Ra6326Rc6Imm16BranchOp6Typ2Ra6target12Op8Rb6BranchOp6Typ2Ra6326Rc6Op8Rb6Branch
BFC Type
Bitfield, constant field index
41 3635 3231 2625 2019 1413 1211 65 0Opcode6Opcode 4RegA6RegT6RegC6Opcode2Width6Start6
BFR Type
Bitfield, register field index
41 3635 3231 2625 2019 1413 1211 65 0Opcode6Opcode 4RegA6RegT6RegC6Opcode2Width6RegB6
Op7Ra5Rt5Imm250MiscMiscellaneous0---280BRK02IRETReturn from interrupt03ERETReturn from exception040WAIT049TLBPProbe TLB entries050TLBRRead TLB entry051TLBWIWrite TLB entry using index052TLBWRWrite random TLB entry064CLIClear interrupt mask065SEISet interrupt mask01Ra5Rt5Rc5Op13Opcd7{reg}register operate1Ra5Rt54COMcompliment1Ra5Rt55NOTLogical not1Ra5Rt56NEGNegative -a1Ra5Rt57ABSAbsolute value (a)1Ra5Rt516CTLZCount leading zeros1Ra5Rt517CTLOCount leading ones1Ra5Rt518CTPOPCount population1Ra5Rt519SEXT8Sign extend 8 to 64 bits1Ra5Rt520SEXT16Sign extend 16 to 64 bits1Ra5Rt521SEXT32Sign extend 32 to 64 bits1Ra5Rt524SQRTSquare root1Rt5SPR640MFSPRMove from special register1Ra5SPR641MTSPRMove to special register2Ra5Rb5Rt5Op1327ADDa + b, error on overflow 2Ra5Rb5Rt5Op1337ADDUa + b, no errors2Ra5Rb5Rt5Op1347SUBa - b, error on overflow 2Ra5Rb5Rt5Op1357SUBUa - b, no errors2Ra5Rb5Rt5Op1367CMPcompare2Ra5Rb5Rt5Op1377CMPU2Ra5Rb5Rt5Op1387AND2Ra5Rb5Rt5Op1397OR2Ra5Rb5Rt5Op13107XORExclusive or2Ra5Rb5Rt5Op13117ANDC2Ra5Rb5Rt5Op13127NAND2Ra5Rb5Rt5Op13137NOR2Ra5Rb5Rt5Op13147XNOR2Ra5Rb5Rt5Op1315ORCOr with complement2Ra5Rb5Rt5Op1320MINMinimum of a or b2Ra5Rb5Rt5Op1321MAXMaximum of a or b2Ra5Rb5Rt5Op1324MULUUnsigned multiply2Ra5Rb5Rt5Op1325MULSSigned multiply2Ra5Rb5Rt5Op1326DIVUUnsigned divide2Ra5Rb5Rt5Op1327DIVSSigned divide2Ra5Rb5Rt5Op1330MOVZConditional move if zero2Ra5Rb5Rt5Op1331MOVNZConditional move if not zero2Ra5Rb5Rt5Op1340SHLShift left2Ra5Rb5Rt5Op1341SHRUUnsigned Shift right 2Ra5Rb5Rt5Op1342ROLRotate left2Ra5Rb5Rt5Op1343RORRotate right2Ra5Rb5Rt5Op1344SHRSigned shift right2Ra5Rb5Rt5Op1345ROLAMRotate left and mask32Ra5Rb5Rt5Op1396SLT2Ra5Rb5Rt5Op1396SGE2Ra5Rb5Rt5Op1398SLE2Ra5Rb5Rt5Op1399SGT2Ra5Rb5Rt5Op13100SLTU2Ra5Rb5Rt5Op13101SGEU2Ra5Rb5Rt5Op13102SLEU2Ra5Rb5Rt5Op13102SGTU2Ra5Rb5Rt5Op13104SEQ2Ra5Rb5Rt5Op13105SNE3Basic Arithmetic4Ra5Rt5Imm25ADDIAdd immediate5Ra5Rt5Imm25ADDUIAdd immediate6Ra5Rt5Imm25SUBISubtract immediate7Ra5Rt5Imm25CMPICompare immediate8Ra5Rt5Imm25CMPUIUnsigned compare immediate9Ra5Rt5Imm25ANDIAnd10Ra5Rt5Imm25ORIOr11Ra5Rt5Imm25XORIExclusive or12Ra5Rt5Imm25MULUIUnsigned multiply13Ra5Rt5Imm25MULSISigned multiply14Ra5Rt5Imm25DIVUIUnsigned divide15Ra5Rt5Imm25DIVSISigned divide1617Ra5Rb5Cond7TRAPccTrap on condition18Ra5Cond5Imm25TRAPcciTrap on condition1920Rt5Imm32SETLOSet low order bits21222324Address35CALLcall subroutine25Address35JMPjump26Ra5Rt5Address25JALjump and link27Ra5Rb5Rt5Imm20RETreturn and add28Rt5Imm32SETHISet high order bits293031
Memory Operations32Ra5Rt5disp25LBload byte, sign extend33Ra5Rt5disp25LCload character, sign extend34Ra5Rt5disp25LHload half-word, sign extend35Ra5Rt5disp25LWload word36Ra5Rt5disp25LPload pair37Ra5Rt5disp25LBUload byte, zero extend38Ra5Rt5disp25LCUload character, zero extend39Ra5Rt5disp25LHUload half-word, zero extend40Ra5Sprt5disp25LSHload special half-word41Ra5Sprt5disp25LSWload special word42Ra5Rt5disp25LFload float43Ra5Rt5disp25LFDload float double44Ra5Rt5disp25LFPload float pair45Ra5Rt5disp25LFDPload float double pair46Ra5Rt5disp25LWRload word, reserve address4748Ra5Rt5disp25SBstore byte (zero)49Ra5Rt5disp25SCstore character50Ra5Rt5disp25SHstore half-word51Ra5Rt5disp25SWstore word52Ra5Rt5disp25SPstore pair53Ra5Rb5Rt5disp13Op7Indexed memory operations54reserved55reserved56Ra5Sprs5disp25SSHstore special half-word57Ra5Sprs5disp25SSWstore special word58Ra5Rb5disp25SFstore float59Ra5Rbt5disp25SFDstore float double60Ra5Rb5disp25SFPstore float pair61Ra5Rb5disp25SFDPstore float double pair62Ra5Rb5disp25SWCRstore word, clear address reservation63IO Operations64Ra5Rt5I/O Address25INBinput byte, sign extend65Ra5Rt5I/O Address25INCHinput character, sign extend66Ra5Rt5I/O Address25INHinput half-word, sign extend67Ra5Rt5I/O Address25INWinput word68Ra5Rt5I/O Address25INBUinput byte, zero extend69Ra5Rt5I/O Address25INCUinput character, zero extend70Ra5Rt5I/O Address25INHUinput half-word, zero extend7172Ra5Rt5I/O Address25OUTBoutput byte73Ra5Rt5I/O Address25OUTCoutput character74Ra5Rt5I/O Address25OUTHoutput half-word75Ra5Rt5I/O Address25OUTWoutput word76777879
Flow Control80Ra5Target12Imm18BLTIbranch if less than81Ra5Target12Imm18BGEIbranch if greater or equal82Ra5Target12Imm18BLEIbranch if less or equal83Ra5Target12Imm18BGTIbranch if greater than84Ra5Target12Imm18BLTUIbranch if lower85Ra5Target12Imm18BGEUIbranch if higher or same86Ra5Target12Imm18BLEUIbranch if lower or same87Ra5Target12Imm18BGTUIbranch if higher88Ra5Target12Imm18BEQIbranch if equal89Ra5Target12Imm18BNEIbranch if not equal90Ra5Target12Imm18LEQIloop if equal91Ra5Target12Imm18LNEIloop if not equal929394Ra5Rb5Op5Imm20Branch to register94Ra5Rb50Imm20BLTRIbranch if less than94Ra5Rb51Imm20BGERIbranch if greater or equal94Ra5Rb52Imm20BLERIbranch if less or equal94Ra5Rb53Imm20BGTRIbranch if greater than94Ra5Rb54Imm20BLTURIbranch if lower94Ra5Rb55Imm20BGEURIbranch if higher or same94Ra5Rb56Imm20BLEURIbranch if lower or same94Ra5Rb57Imm20BGTURIbranch if higher94Ra5Rb58Imm20BEQRIbranch if equal94Ra5Rb59Imm20BNERIbranch if not equal95Branch to register95Ra5Rb5Target200BLTa < b95Ra5Rb5Target201BGEa >= b95Ra5Rb5Target202BLEa<=b95Ra5Rb5Target203BGTa >b95Ra5Rb5Target204BLTUa < b95Ra5Rb5Target205BGEUa >=b95Ra5Rb5Target206BLEUa <=b95Ra5Rb5Target207BGTUa > b95Ra5Rb5Target208BEQa == b95Ra5Rb5Target209BEQa == b95Ra5Rb5Target2010BRA195Ra5Rb5Target2011BRN095Ra5Rb5Target2012BANDa && b95Ra5Rb5Target2013BORa || b95Ra5Rb5Rc516BLTRbranch if less than95Ra5Rb5Rc517BGERbranch if greater or equal95Ra5Rb5Rc518BLERbranch if less or equal95Ra5Rb5Rc519BGTRbranch if greater than95Ra5Rb5Rc520BLTURbranch if lower95Ra5Rb5Rc521BGEURbranch if higher or same95Ra5Rb5Rc522BLEURbranch if lower or same95Ra5Rb5Rc523BGTURbranch if higher95Ra5Rb5Rc524BEQRbranch if equal95Ra5Rb5Rc525BNERbranch if not equal
Relational Compares96Ra5Rt5Imm25SLTIa < b97Ra5Rt5Imm25SGEIa >= b98Ra5Rt5Imm25SLEIa <= b99Ra5Rt5Imm25SGTIa > b100Ra5Rt5Imm25SLTUIa < b101Ra5Rt5Imm25SGEUIa >= b102Ra5Rt5Imm25SLEUIa <= b103Ra5Rt5Imm25SGTUIa > b104Ra5Rt5Imm25SEQIa == b105Ra5Rt5Imm25SNEIa != b106107
108109Ra5Rt5Funct7FPLOOFloating point109Ra5Rt513I2FInteger to float109Ra5Rt514F2IFloat to integer110Ra5Rt5Funct7FPZLFloating point110Ra5Rt50FABSFloating point absolute value110Ra5Rt51FNABSFloating point neg. absolute110Ra5Rt52FNEGFloating point negate110Ra5Rt53FMOVFloating point move110Ra5Rt54FSIGNFloating point get sign110Ra5Rt55FMANFloating point get mantissa110Ra5Rt56110Ra5Rt57110Ra5Rb5Rt58FCLTa < b110Ra5Rb5Rt59FCGEa >= b110Ra5Rb5Rt510FCLEa <= b110Ra5Rb5Rt511FCGTa > b110Ra5Rb5Rt512FCEQa == b110Ra5Rb5Rt513FCNEa <> b110Ra5Rb5Rt514FCUNFloating point unordered110Ra5Rb5Rt515FCORFloating point ordered
111NOP73Imm39IMMImmediate prefix
Opcode Maps
Major Instruction Group
Bits 41-35
Opcode7Opcode35
MSB is down, LSB is across
01234567001234567{misc}{reg}{float} HYPERLINK \l "ADD" ADDM # HYPERLINK \l "SUB" SUBM # HYPERLINK \l "ADD" ADDH # HYPERLINK \l "SUB" SUBH #189101112131415 HYPERLINK \l "ADD" ADD # HYPERLINK \l "SUB" SUB # HYPERLINK \l "MUL" MUL # HYPERLINK \l "DIV" DIV # HYPERLINK \l "MULH" MULH # HYPERLINK \l "MOD" MOD #21617181920212223 HYPERLINK \l "XOR" XOR # HYPERLINK \l "AND" AND # HYPERLINK \l "OR" OR # HYPERLINK \l "MLO" MLO HYPERLINK \l "XOR" XORM # HYPERLINK \l "AND" ANDM # HYPERLINK \l "OR" ORM #32425262728293031 HYPERLINK \l "XOR" XORH # HYPERLINK \l "AND" ANDH # HYPERLINK \l "OR" ORH #{ HYPERLINK \l "BFINS" bitfield}43233343536373839LBLCLHLWLPLBZLCZLHZ54041424344454647LSHLSWLFLFDLFPLFDP HYPERLINK \l "DCACHE" {cache} HYPERLINK \l "DCACHE" {cacheu}64849505152535455SBSCSHSWSPSBZSCZSHZ75657585960616263SSHSSWSFSFDSFPSFDP86465666768697071INBINCINHINWINBZINCZINHZ97273747576777879OUTBOUTCOUTHOUTW108081828384858687 HYPERLINK \l "Bcc" BLT # HYPERLINK \l "Bcc" BLE # HYPERLINK \l "Bcc" BGT # HYPERLINK \l "Bcc" BGE # HYPERLINK \l "Bcc" BLTU # HYPERLINK \l "Bcc" BLEU # HYPERLINK \l "Bcc" BGTU # HYPERLINK \l "Bcc" BGEU #118889909192939495 HYPERLINK \l "Bcc" BEQ # HYPERLINK \l "Bcc" BNE # HYPERLINK \l "Bcc" BAND # HYPERLINK \l "Bcc" BNAND # HYPERLINK \l "Bcc" BOR # HYPERLINK \l "Bcc" BNOR #1296979899100101102103 HYPERLINK \l "JAL" JALRET HYPERLINK \l "JMP" JMP HYPERLINK \l "CALL" CALL HYPERLINK \l "NOP" NOP13104105106107108109110111 HYPERLINK \l "CLT" CLT # HYPERLINK \l "CGE" CLE # HYPERLINK \l "CLE" CGT # HYPERLINK \l "CGT" CGE # HYPERLINK \l "CLT" CLTU # HYPERLINK \l "CGE" CLEU # HYPERLINK \l "CLE" CGTU # HYPERLINK \l "CGT" CGEU #14112113114115116117118119 HYPERLINK \l "CEQ" CEQ # HYPERLINK \l "CNE" CNE # HYPERLINK \l "CLE" CMP # HYPERLINK \l "CGT" CMPU #15120121122123124125126127SETLOSETMIDSETHI
Register Instruction Group
Bits 12-6, Bits 41-35 = 4
17Ra6Rt6Rc6Opcode11Rb6
01234567001234567{misc}{ HYPERLINK \l "BFINS" bitfield}189101112131415 HYPERLINK \l "ADD" ADD HYPERLINK \l "SUB" SUB HYPERLINK \l "MUL" MUL HYPERLINK \l "DIV" DIV HYPERLINK \l "MULH" MULH HYPERLINK \l "MOD" MOD21617181920212223 HYPERLINK \l "XOR" XOR HYPERLINK \l "AND" AND HYPERLINK \l "OR" OR3242526272829303143233343536373839LBLCLHLWLPLBZLCZLHZ54041424344454647LSHLSWLFLFDLFPLFDP HYPERLINK \l "DCACHE" {cache} HYPERLINK \l "DCACHE" {cacheu}64849505152535455SBSCSHSWSP75657585960616263SSHSSWSFSFDSFPSFDP86465666768697071INBINCINHINWINBZINCZINHZ97273747576777879OUTBOUTCOUTHOUTW108081828384858687 HYPERLINK \l "Bcc" BLT HYPERLINK \l "Bcc" BLE HYPERLINK \l "Bcc" BGT HYPERLINK \l "Bcc" BGE HYPERLINK \l "Bcc" BLTU HYPERLINK \l "Bcc" BLEU HYPERLINK \l "Bcc" BGTU HYPERLINK \l "Bcc" BGEU118889909192939495 HYPERLINK \l "Bcc" BEQ HYPERLINK \l "Bcc" BNE HYPERLINK \l "Bcc" BAND HYPERLINK \l "Bcc" BNAND HYPERLINK \l "Bcc" BOR HYPERLINK \l "Bcc" BNOR1296979899100101102103 HYPERLINK \l "JAL" JALRET HYPERLINK \l "NOP" NOP13104105106107108109110111 HYPERLINK \l "CLT" CLT HYPERLINK \l "CGE" CLE HYPERLINK \l "CLE" CGT HYPERLINK \l "CGT" CGE HYPERLINK \l "CLT" CLTU HYPERLINK \l "CGE" CLEU HYPERLINK \l "CLE" CGTU HYPERLINK \l "CGT" CGEU14112113114115116117118119 HYPERLINK \l "CEQ" CEQ HYPERLINK \l "CNE" CNE HYPERLINK \l "CLE" CMP HYPERLINK \l "CGT" CMPU15120121122123124125126127SETLOSETMIDSETHI
01234567161281291301311321331341351713613713813914014114214318144145146147148149150151 HYPERLINK \l "XOR" XNOR HYPERLINK \l "AND" NAND HYPERLINK \l "OR" NOR191521531541551561571581592016016116216316416516616721168169170171172173174175221761771781791801811821832318418518618718818919019124192193194195196197198199 HYPERLINK \l "SHL" SHL # HYPERLINK \l "ROL" ROL # HYPERLINK \l "SHR" SHR # HYPERLINK \l "ASR" ASR # HYPERLINK \l "ASR" ROR #25200201202203204205206207 HYPERLINK \l "SHL" SHL HYPERLINK \l "ROL" ROL HYPERLINK \l "SHR" SHR HYPERLINK \l "ASR" ASR HYPERLINK \l "ROL" ROR26208209210211212213214215SRANDGRSGRINTGRAF27216217218219220221222223CPOPCLZCLO28224225226227228229230231292322332342352362372382393024024124224324424524624731248249250251252253254255
Miscellaneous Control
Bits 12-6, Bits 31-25 = 1
Bits 41-35
Opcode7Opcode35
Bits 12-6, Bits 41-35 = 4
07Ra6Rt6Rc6Opcode11Rb6
01234567001234567HYPERLINK \l "DI"DI HYPERLINK \l "EI" EI HYPERLINK \l "RI" RIFLUSH189101112131415 HYPERLINK \l "STOP" STOP HYPERLINK \l "END" END HYPERLINK \l "WAI" WAI21617181920212223 HYPERLINK \l "END" ENDsim1sim2sim3sim4sim5sim6sim732425262728293031swe0swe1swe2swe3swe4swe5swe6swe743233343536373839540414243444546476484950515253545575657585960616263 HYPERLINK \l "TRS" TRS HYPERLINK \l "TSR" TSR89101112131415
Floating Point Operations
Bits 12-6, Bits 41-35 = 4
27Ra6Rt6Rc6Opcode11Rb6
01234567001234567 HYPERLINK \l "FADD" FADD HYPERLINK \l "FSUB" FSUB HYPERLINK \l "FMUL" FMUL HYPERLINK \l "FDIV" FDIV189101112131415HYPERLINK \l "FABS"FABSHYPERLINK \l "FNABS"FNABS HYPERLINK \l "FNEG" FNEGFSIGNFMOVFMANFNOP21617181920212223 HYPERLINK \l "F2INT" F2INTINT2F32425262728293031 HYPERLINK \l "FCccS" FCLTFCGE HYPERLINK \l "FCccS" FCLEFCGT HYPERLINK \l "FCccS" FCEQ HYPERLINK \l "FCccS" FCNE HYPERLINK \l "FCccS" FCORFCNO43233343536373839540414243444546476484950515253545575657585960616263FSTATFRMFTXFCXFEXFDX86465666768697071 HYPERLINK \l "FADD" FADDD HYPERLINK \l "FSUB" FSUBD HYPERLINK \l "FMUL" FMULD HYPERLINK \l "FDIV" FDIVD97273747576777879HYPERLINK \l "FABS"FABSDHYPERLINK \l "FNABS"FNABSD HYPERLINK \l "FNEG" FNEGDFSIGNDFMOVDFMANDFNOPD108081828384858687 HYPERLINK \l "F2INT" F2INTDINT2FD118889909192939495 HYPERLINK \l "FCccS" FCLTDFCGED HYPERLINK \l "FCccS" FCLEDFCGTD HYPERLINK \l "FCccS" FCEQD HYPERLINK \l "FCccS" FCNED HYPERLINK \l "FCccS" FCORDFCNOD1296979899100101102103131041051061071081091101111411211311411511611711811915120121122123124125126127
Instruction Set Description
HYPERLINK \l "ADD" ADD HYPERLINK \l "AND" AND HYPERLINK \l "ASR" ASR HYPERLINK \l "Bcc" BAND HYPERLINK \l "Bcc" BEQ HYPERLINK \l "BFCHG" BFCHG HYPERLINK \l "BFCLR" BFCLR HYPERLINK \l "BFEXT" BFEXT HYPERLINK \l "BFINS" BFINS HYPERLINK \l "Bcc" BGE HYPERLINK \l "Bcc" BGT HYPERLINK \l "Bcc" BLE HYPERLINK \l "Bcc" BLT HYPERLINK \l "Bcc" BNAND HYPERLINK \l "Bcc" BNE HYPERLINK \l "Bcc" BNOR HYPERLINK \l "Bcc" BOR HYPERLINK \l "BRK" BRK HYPERLINK \l "Bcc" BXNOR HYPERLINK \l "Bcc" BXOR HYPERLINK \l "CALL" CALL HYPERLINK \l "Ccc" CEQ HYPERLINK \l "Ccc" CGE HYPERLINK \l "Ccc" CGT HYPERLINK \l "Ccc" CLE HYPERLINK \l "Ccc" CLT HYPERLINK \l "Ccc" CNE HYPERLINK \l "DI" DI HYPERLINK \l "DIV" DIV HYPERLINK \l "EI" EI HYPERLINK \l "END" END HYPERLINK \l "F2INT" F2INT HYPERLINK \l "FABS" FABS HYPERLINK \l "FADD" FADD HYPERLINK \l "FCccS" FCEQ HYPERLINK \l "FCccS" FCGE HYPERLINK \l "LB" LB HYPERLINK \l "LBU" LBULCLCU HYPERLINK \l "LH" LH HYPERLINK \l "LHU" LHULWLWCLWU HYPERLINK \l "MLO" MLO HYPERLINK \l "ROL" ROL HYPERLINK \l "ROR" ROR HYPERLINK \l "SB" SB HYPERLINK \l "SBU" SBUSCSCU HYPERLINK \l "SGN" SGN HYPERLINK \l "SH" SH HYPERLINK \l "SHL" SHL HYPERLINK \l "SHR" SHR HYPERLINK \l "SHU" SHU HYPERLINK \l "SUB" SUBSWSWU HYPERLINK \l "TRS" TRS HYPERLINK \l "TSR" TSR HYPERLINK \l "XNOR" XNOR HYPERLINK \l "XOR" XOR ADD Rt,Ra,Rb
ADDI Rt,Ra,#n
Immediate Format:
41 3534 3029 2524 047Ra5Rt5immediate25
Register Format:
41 3534 3029 2524 2019 76 027Ra6Rb6Rb6~1327
Synopsis
'Add' register with register or immediate. If the result overflows an overflow exception is triggered.
Detail
Rt = Ra + Rb
Rt = Ra + #imm
ADDU Rt,Ra,Rb
ADDUI Rt,Ra,#n
Immediate Format:
41 3534 3029 2524 057Ra5Rt5immediate25
Register Format:
41 3534 3029 2524 2019 76 027Ra6Rb6Rb6~1337
Synopsis
'Add' register with register or immediate. No exceptions will occur.
Detail
Rt = Ra + Rb
Rt = Ra + #imm
AND Rt,Ra,Rb
ANDI Rt,Ra,#n
Synopsis
Logically 'and' register with register or immediate.
Detail
Detail
Rt = Ra & Rb
Rt = Ra & #imm
ASR Rt,Ra,#cnt
ASR Rt,Ra,Rb
Synopsis
Arithmetically shift register right.
Detail
Rd = Rd ^>> Rb
The sign bit of the register is preserved during the shift.
Rt = Ra ^>> #cnt
BccI Ra,#,label
Bcc Ra,Rb,label
Synopsis
Branch to label if condition is true
Detail
if register register compare
if Ra cond Rb is true then
if register form
pc = Rt
else
pc = pc + displacement
else
if Ra cond #n is true then
if register form
pc = Rt
else
pc = pc + displacement
Branch Conditions
MnemonicDescriptionConditional TestHYPERLINK \l "Bcc"BLTBranch if Less Thana < bHYPERLINK \l "Bcc"BGEBranch if Greater than or Equala >= bHYPERLINK \l "Bcc"BLEBranch if Less than or Equala <= bHYPERLINK \l "Bcc"BGTBranch if Greater Thana > bHYPERLINK \l "Bcc"BEQ / BXNORBranch if Equala == bHYPERLINK \l "Bcc"BNE / BXORBranch if Not Equala <> bHYPERLINK \l "Bcc"BANDBranch if both truea and bHYPERLINK \l "Bcc"BORBranch if either truea or b
BFCHG Rt,Ra,#bfb,#bfe
Synopsis
Insert into bitfield..
Detail
Rt[bfb:fbe] = Ra
Flip the bits between BFB (bit field begin) and BFE (bit field end) of Ra and transfer the result to Rt. (Ra is not altered).
BFCLR Rt,#bfb,#bfe
Synopsis
Clear bitfield..
Detail
Rt[bfb:fbe] = 0
Clear the bits between BFB (bit field begin) and BFE (bit field end) inclusive of Rt.
This is an extended mnemonic for the HYPERLINK "C:\\Users\\Robert\\AppData\\Roaming\\Microsoft\\raptor32.html" \l "BFINS#BFINS"BFINS instruction.
BFEXT Rt,Ra,#bfb,#bfe
Synopsis
Extract bitfield..
Detail
Rt = Ra[bfb:fbe]
Extract the bits between BFB (bit field begin) and BFE (bit field end) inclusive and transfer to the low order bits of Rt. The result in Rt is zero extended.
BFINS Rt,Ra,#bfb,#bfe
Synopsis
Insert into bitfield..
Detail
Rt[bfb:fbe] = Ra
Insert the low order bits from Ra into the bits between BFB (bit field begin) and BFE (bit field end) inclusive of Rt.
BRK
Synopsis
Call break exception handler.
Detail
XRA = pc; pc = mem[FFFF_F000]; status.backup = status; status.im = 1
This instruction causes the processor to perform a software initiated 'break' interrupt routine. It is purposely defined as a zero word so the processor will execute the break routine in the event that code flows into a region of memory that has been nulled out. This helps promote reliable system operation.
BSR label
Synopsis
Branch to subroutine.
Detail
R31 = pc;
pc[31:8] = pc[31:8] + {target[25:6]};
pc[7:0] = {target[5:0],00}
Call subroutine using program counter page relative offset address form. The twenty-six bit displacement is shifted left twice and sign extended to 32 bits before being used. Note the branch is made in a similar fashion to conditional branches. The low order six bits of the target are copied directly to the pc, while the upper twenty bits represent a page relative address.
CALL d[Ra]
CALL label
Synopsis
Call subroutine
Detail
R47 = pc; pc = disp + Ra;
Call subroutine using register indirect with displacement mode. This is an alternate form of the HYPERLINK "C:\\Users\\Robert\\AppData\\Roaming\\Microsoft\\raptor32.html" \l "JAL#JAL"JAL instruction.
R47 = pc; pc = pc + displacement;
Call subroutine quick form. The twenty-five bit address field is shifted left twice and added to the program counter to form the target address. This allows an relative address call to a method within the same 64MB region of memory.
S Rt,Ra,Rb
S Rt,Ra,#n
Synopsis
Compare register with register or immediate.
Detail
Rt = Ra cond Rb
Rt = Ra cond #imm
This instruction performs a comparison of two values and stores the result (1 if condition is true, 0 otherwise) in the target register.
Compare Conditions
CMP Rt,Ra,Rb
CMPI Rt,Ra,#n
CMPU Rt,Ra,Rb
CMPUI Rt,Ra,#n
Synopsis
CMP: 'Compare' register with register or immediate.
CMPU: Unsigned compare of register with register or immediate
Detail
Rt = Ra cond Rb
Rt = Ra cond #imm
This instruction performs a comparison of two values and stores the result in the target register. If the first value is less than the second one, -1 is written to the target register. If the two values are equal, zero is written to the target register. If the first value is greater than the second one +1 is written to the target register. This instruction may also be used to obtain the sign of a value by comparing the value to zero.
CP1 #imm
CP2 #imm
Synopsis
Constant prefix
The upper bits of the immediate constant are set for the next instruction, overriding sign extension of the immediate.
The constant prefix instruction (CP1) indicates the presence of an additional twenty-eight constant bits in the instruction stream intended to represent significant bits 9 to 36 for the immediate constant of next instruction. These bits will take precedence over sign extension of the constant for the next instruction. CP1 sign extends from bit 37 to 64 bits.
The constant prefix instruction (CP2) adds twenty-seven more bits to the immediate constant of the following instruction, overriding any sign extension and substituting for bits 57 to 63.
Constant prefix instructions do not require the presence of other constant prefix instructions. For example CP2 may be used without CP1. CP1 may be used without CP2.
When multiple prefix are present the constant prefix instructions should be issued in the order CP1 then CP2 to ensure a properly built constant.
Interrupts are prevented from occurring between this instruction and the next instruction. Normally this instruction is automatically inserted by the assembler wherever an extended constant value is required.
DI
Synopsis
Disable interrupts.
Detail
status.im = 1
This instruction disables maskable hardware interrupts by setting the interrupt mask in the processor control register. It also disables the HYPERLINK "C:\\Users\\Robert\\AppData\\Roaming\\Microsoft\\raptor32.html" \l "NMI#NMI"IRQ instruction.
DIV Rt,Ra,Rb
DIVI Rt,Ra,#n
Synopsis
Divide register by register or immediate.
Detail
Rt = Ra / Rb
Rt = Ra / #imm
This is a signed division operation. Division by zero will cause an exception.
EI
Synopsis
Enable interrupts.
Detail
status.im = 0
This instruction enables maskable hardware interrupts by clearing the interrupt mask in the status register. Enabling interrupts occurs after a minimum of one clock cycle delay.
END
Synopsis
No operation.
Detail
This instruction is provided for use in a software emulator of the processor. It indicates the end of a sequence of instructions to emulate. The processor will treat this instruction as a NOP instruction. This instruction is not meant to be used by actual hardware.
F2INT Rt,Ra
Synopsis
Floating point convert single precision to integer. Register to register.
Detail
Rt = int(Ra)
FABS Rt,Ra
Synopsis
Take floating point absolute value of register.
Detail
Rt = Ra;
Rt.sign = 0;
This instruction simply clears the sign bit of register.
FADD Rt,Ra,Rb
Synopsis
Floating point addition. Add register with register.
Detail
Rt = Ra + Rb
FCLT Rt,Ra,Rb
FCLE Rt,Ra,Rb
FCGT Rt,Ra,Rb
FCGE Rt,Ra,Rb
FCEQ Rt,Ra,Rb
FCNE Rt,Ra,Rb
FCOR Rt,Ra,Rb
Synopsis
Floating point single precision comparison, register with register.
Detail
Rt = Ra cond Rb
This instruction performs a comparison of two values and stores a one (true) or zero (false) to the target register depending on the whether the tested condition is true or false.
Compare Conditions
FDIV Rt,Ra,Rb
Synopsis
Floating point division. Divide register by register.
Detail
Rt = Ra / Rb
This instruction may cause a division by zero exception.
FIP
Synopsis
Flush instruction pipeline.
Detail
flags.im = 0
This instruction flushes the processors instruction pipeline of all instructions following the FIP instruction.
Flags Affected
I0-------
FMUL Rt,Ra,Rb
Synopsis
Floating point multiplication. Multiply register by register.
Detail
Rt = Ra * Rb
FNABS Rt,Ra
Synopsis
Take floating point negative absolute value of register.
Detail
Rt = Ra
Rt[31] = 1
This instruction simply sets the sign bit of register.
FNEG Rt,Ra
Synopsis
Negate floating point value in register.
Detail
Rt = Ra
Rt[31] = ~Ra[31]
This instruction simply complements the sign bit of register.
FSUB Rt,Ra,Rb
Synopsis
Floating point subtraction. Subtract register from register.
Detail
Rt = Ra - Rb
IRQ
Synopsis
Run irq routine.
Detail
R30 = pc; pc = FFFF_FFF4; flags.backup = flags; flags.im = 1
This instruction causes the processor to perform a software initiated maskable interrupt routine. It has the same effect as an external hardware maskable interrupt. If the interrupt mask in the status register is set, then this instruction will be ignored. This is an alternate form of the HYPERLINK "C:\\Users\\Robert\\AppData\\Roaming\\Microsoft\\raptor32.html" \l "JAL#JAL"JAL instruction.
Flags Affected
I1-------
JAL Rt,d[Ra]
Synopsis
Jump and link to subroutine
Detail
Rt = inc(pc); pc = disp + Ra;
Jump to subroutine using register indirect with displacement mode. The current value of the program counter is stored in the destination register. Normally this instruction will be used with a constant prefix.
JMP d[Ra]
JMP address
Synopsis
Jump to address
Detail
pc = disp + Ra;
Jump using register indirect with displacement mode. This is an alternate form of the HYPERLINK "C:\\Users\\Robert\\AppData\\Roaming\\Microsoft\\raptor32.html" \l "JAL#JAL"JAL instruction.
pc = {pc[63:37],address,00};
Jump to address quick form. The thirty-five bit address field is shifted left twice and concatenated to the upper 27 bits of the program counter to form the target address.
LB Rt,d[Ra]
LBRt,[Ra + Rb]
Synopsis
Load register byte from memory
Detail
Rt = Memory8 [Ra + disp]
Rt = Memory8 [Ra + Rb]
The byte loaded from memory is sign extended to the register width.
LBU Rt,d[Ra]
LBU Rt,[Ra+Rb]
Synopsis
Load register byte from memory
Detail
Rt = Memory8 [Ra + disp]
Rt = Memory8 [Ra + Rb]
The byte loaded from memory is zero extended to the register width.
LEA Rt,d[Ra]
LEA Rt,d[Ra+Rb]
Synopsis
Load effective address.
Detail
Rt = Ra + Rb
Rt = Ra + #imm
The effective address is loaded into the target register. This instruction is an alternate form of the HYPERLINK "C:\\Users\\Robert\\AppData\\Roaming\\Microsoft\\raptor32.html" \l "SBC#SBC"ADD instruction.
LF Rt,d[Ra]
LF Rt,d[Ra+Rb]
Synopsis
Load floating point register word from memory
Detail
Rt = funpack(memory32[Ra + disp])
Rt = funpack(memory32 [Ra + Rb])
Load floating point value from memory and unpack the value into register Rt.
LH Rt,d[Ra]
LH Rt,d[Ra+Rb]
Synopsis
Load register half-word from memory
Detail
Rt = Memory16 [Ra + disp]
Note the format of the displacement field. D0 is forced to zero because half-word accesses must be half-word aligned.
Rt = Memory16 [Ra + Rb]
The half-word loaded from memory is sign extended to the register width.
LHU Rt,d[Ra]
LHU Rt,d[Ra+Rb]
Synopsis
Load register half-word from memory
Detail
Rt = Memory16 [Ra + disp]
Note the format of the displacement field. D0 is forced to zero because half-word accesses must be half-word aligned.
Rt = Memory16 [Ra + Rb]
The half-word loaded from memory is zero extended to the register width.
LW Rt,d25[Ra]
LW Rt,d13[Ra+Rb]
Synopsis
Load register word from memory
Detail
Rt = Memory32 [Ra + disp]
Note the format of the displacement field. D2..0 is forced to zero because word accesses must be word aligned.
Rt = Memory32 [Ra + Rb]
MLO Rt,Ra,Rb,Rc
Synopsis
Mystery logical operation register with register.
Detail
Rt = Ra Rb
Perform a logical operation between Ra and Rb and place result in target register Rt. The operation to be performed is determined by the low order three bits of register Rc. This instruction is used to avoid switch case statements (branches) where the logical operation to be performed may be determined at run time. There is no immediate form for this instruction.
Opcode:
register valueoperation0exclusive or1and2inclusive or3{reserved}4exclusive nor5nand6nor7{reserved}
MOD Rt,Ra,Rb
MOD Rt,Ra,#n
Synopsis
Get remainder from divide of register by register or immediate.
Detail
Rt = Ra % Rb
Rt = Ra % #imm
This is a signed division operation. The remainder of the division is placed in the target register Rt. MUL Rt,Ra,Rb
MUL Rt,Ra,#n
Synopsis
Multiply register with register or immediate.
Detail
Rt = Ra * Rb
Rt = Ra * #imm
This is a signed multiply operation. The low order 32 bits of the result are placed in the target register.
MULH Rt,Ra,Rb
MULH Rt,Ra,#n
Synopsis
Multiply register with register or immediate; return high order bits.
Detail
Rt = Ra * Rb
Rt = Ra * #imm
This is a signed multiply operation. The high order 32 bits of the result are placed in the target register.
NAND Rt,Ra,Rb
Synopsis
Logically ''nand' register with register.
Detail
Rt = ~(Ra & Rb)
There is no immediate form for this instruction.
NMI
Synopsis
Run nmi routine.
Detail
R30 = pc; pc = FFFF_FFF8; flags.backup = flags; flags.im = 1
This instruction causes the processor to perform a software initiated non-maskable interrupt routine. It has the same effect as an external hardware non-maskable interrupt.
Flags Affected
I1-------
NOP
Synopsis
No operation
Detail
This instruction acts merely as a placeholder. It performs no operation and has no effect on the processor. Many processors lack an explicit NOP operation resulting in different instructions being used for this purpose within the same processor. By providing an explicit NOP instruction some consistency in programs can be achieved. Without a NOP instruction many processors typically use instructions which have side effects in the form of affecting the processor status flags; this is not the case here.
NOR Rt,Ra,Rb
Synopsis
Logically inclusively 'nor' register with register.
Detail
Rt = ~(Ra | Rb)
There is no immediate form for this instruction.
NOT Rt,Ra
Synopsis
Take ones complement of register.
Detail
Rt = ~Ra
There is no immediate form for this instruction.
OR Rt,Ra,Rb
ORI Rt,Ra,#n
Synopsis
Logically inclusively 'or' register with register or immediate.
Detail
Rt = Ra | Rb
Rt = Ra | #imm
RESET
Synopsis
Run reset routine.
Detail
EPC = pc; pc = FFFF_FFFC; flags.backup = flags; flags.im = 1
This instruction causes the processor to perform a software initiated reset routine.
Flags Affected
I1-------
RET
Synopsis
Return from subroutine.
Detail
pc = Rb
Rt = Ra + imm
27Ra5Rb5Rt5Imm20RETreturn and addThis instruction returns to the calling routine by loading the program counter with the contents of the register Rb. Normally Rb will be R31 which is automatically updated by the call instruction.
This instruction also performs and addition, allowing a stack frame to be updated.
RI
Synopsis
Restore interrupt flag from backup copy.
Detail
flags.im = flags.backup im
This instruction restores the previous interrupt flag state from the backup copy of the processor control register. This allows restoring the interrupt state that was present when the backup of the status register was made. This is useful in operating system code where interrupts must be disabled to perform certain system functions (like updating system lists) and then restored to a previous state after performing the operation.
Flags Affected
IX-------
ROLI Rt,Ra,#cnt
ROL Rt,Ra,Rb
Synopsis
Rotate register left.
Detail
Rd = Rd !<< Rb
The most significant bit is shifted into the least significant bit.
Rt = Ra !<< #cnt
RORI Rt,Ra,#cnt
ROR Rt,Ra,Rb
Synopsis
Rotate register right.
Detail
Rd = Rd !>> Rb
The most significant bit is shifted into the least significant bit.
Rt = Ra !>> #cnt
ERET
Synopsis
Return from exception subroutine.
Detail
pc = R30
This instruction returns from an exception processing routine by restoring the flag register and jumping back to the code that was interrupted (who's address is stored in EPC).
SB Rs,d[Ra]
SBRs,d[Ra + Rb]
Synopsis
Store byte from register to memory.
Detail
Memory8 [Ra + disp] = Rs
Memory8 [Ra + Rb + disp] = Rs
SETHI
S-Type
Usage: setting register to constant value
41 3835 2525 2019 0154immediate12RegT6immediate20
The SETHI instruction sets the high order 32 bits of the target register to the immediate value specified in the opcode. The low order 32 bits of the register are unaffected. This instruction is typically used after the SETLO instruction in order to form a 64 bit constant.
SETLO
S-Type SETHI, SETLO
Usage: setting register to constant value
41 3736 2524 2019 0145immediate12RegT5immediate20
The SETLO instruction sets the target register to the immediate value specified in the opcode. The low order 32 bits of the register are set as specified in the opcode, the high order 32 bits of the register are set to the sign extension of the low order bits. SF Rt,d[Ra]
SF Rt,[Ra+Rb]
Synopsis
Store floating point register word to memory
Detail
memory32[Ra + disp] = fpack(Rs)
desc:opRaRsdisp.size:65516bits:31 2625 2120 1615 0bit pattern:28R4..0R4..0d15..0
memory32[Ra + Rb] = fpack(Rs)
desc:opRaRsRbXopsize:655556bits:31 2627 2423 2015 1110 65 0bit pattern:60R4..0R4..0R4..0~28Store packed floating point single value from register Rs to memory.
SGN Rt,Ra
Synopsis
Obtain sign of number.
Detail
Rt = Ra cond 0
This instruction performs a comparison of a register to zero and stores the result in the target register. If the value is less than zero, -1 is written to the target register. If the value is equal to zero, zero is written to the target register. If the value is greater than zero, +1 is written to the target register. This instruction is an alternate form of the HYPERLINK \l "CMP" CMP instruction, where the register is compared to the value zero..
SH Rt,d[Ra]
SH Rt,[Ra+Rb]
Synopsis
Store half-word from register to memory
Detail
Memory16 [Ra + disp] = Rs[15:0]
desc:opRaRsdispsize:65516bits:31 2625 2120 1615 0bit pattern:54R4..0R4..0d15..0Memory16 [Ra + Rb] = Rs[15:0]
desc:OpRaRs~OpRbsize:655565bits:31 2625 2120 1615 1110 54 0bit pattern:2R4..0R4..0~54R4..0Note the format of the displacement field. D0 is forced to zero because half-word accesses must be half-word aligned.
SHL Rt,Ra,#cnt
SHL Rt,Ra,Rb
Synopsis
(Logically) shift register left.
Detail
Rd = Rd << Rb
Zeroes are shifted into the least significant bits.
desc:opRaRtXopRbsize:655565bits:31 2625 2120 1615 1110 54 0bit pattern:12R4..0R4..0~8R4..0Rt = Ra << #cnt
desc:opRaRtXopcntsize:655565bits:31 2625 2120 1615 1110 54 0bit pattern:12R4..0R4..0~0N4..0
SHR Rt,Ra,#cnt
SHR Rt,Ra,Rb
Synopsis
(Logically) shift register right.
Detail
Rd = Rd >> Rb
A zero is shifted into the most significant bit.
desc:opRaRtXopRbsize:655565bits:31 2625 2120 1615 1110 54 0bit pattern:12R4..0R4..0~11R4..0Rt = Ra >> #cnt
desc:opRaRtXopcntsize:655565bits:31 2625 2120 1615 1110 54 0bit pattern:12R4..0R4..0~3N4..0
STOP
Synopsis
Stop the processor from executing instructions and wait for the external hardware 'go' signal or a non-maskable interrupt.
Detail
desc:opsize:32bits:31 0bit pattern:0000_0008This instruction can be used to synchronize the processor to an external event.
SUB Rt,Ra,Rb
SUB Rt,Ra,#n
Synopsis
'Subtract' register with register or immediate.
Detail
Rt = Ra - Rb
desc:opRaRt~opRbsize:655565bits:31 2625 2120 1615 1110 54 0bit pattern:2R4..0R4..0~5R4..0Rt = Ra - #imm
desc:opRaRtimmsize:65516bits:31 2625 2120 1615 0bit pattern:5R4..0R4..0n15..0 SWRs,d[Ra]
SWRs,[Ra + Rb]
Synopsis
Store word from register to memory
Detail
Memory32 [Ra + disp] = Rs
desc:opRaRsdispsize:65516bits:31 2625 2120 1615 0bit pattern:55R4..0R4..0d15..0Note the format of the displacement field. D1..0 is forced to zero because word accesses must be word aligned.
Memory32 [Ra + Rb] = Rs
desc:opRaRs~opRbsize:655565bits:31 2625 2120 1615 1110 54 0bit pattern:2R4..0R4..0~55R4..0
SYS
Synopsis
Perform system call.
Detail
R62 = pc; pc = +nnn; pcr.backup = pcr; pcr.im = 1
This instruction causes the processor to perform a system call. It is meant for operating system support. It is a specialized form of the HYPERLINK \l "JAL" JAL instruction.
Effects:
The processor control register is copied to its backup version. Then the interrupt mask is set, disabling further interrupts.
The program counter is stored in register 62.
The program counter is loaded with the sum of the exception table address register and the call number shifted left twice.
I - Type
Register-Immediate Datapath,
Jump and Link
31 2524 1918 1312 10 9 027Ra6620Call No10 TRSRa,Spr
Synopsis
Transfer register to special purpose register.
Detail
Special Register = Ra
Special Registers
Currently there are only five special registers defined, the remaining codes are reserved for future use.
CodeRegister NameDescription0PCRProcessor Control Register1{this register is reserved}2{this register is reserved}3VERProcessor Version - major, minor, revision4RNDrandom number register
TSRRt,Spr
Synopsis
Transfer special purpose register to register.
Detail
Rt = Special Register
Special Registers
Currently there are only five special registers defined, the remaining codes are reserved for future use.
CodeRegister NameDescription0PCRProcessor Control Register1{this register is reserved}2{this register is reserved}3VERProcessor Version - major, minor, revision4RNDrandom number register5TCTick Count
WAI
Synopsis
Wait for interrupt.
Detail
If the processor is in the interrupt context, this instruction will cause the processor to exit the interrupt context; otherwise this instruction will be treated as a nop. When an interrupt occurs, the processor will begin execution immediately after the wai instruction, if the wai instruction was used to exit the interrupt context.
Normally this instruction would be used in an interrupt service routine at the point at which it is desired to begin interrupt processing.
XNOR Rt,Ra,Rb
Synopsis
Logically exclusively 'nor' register with register.
Detail
Rt = ~(Ra ^ Rb)
There is no immediate form for this instruction.
XOR Rt,Ra,Rb
XOR Rt,Ra,#n
Synopsis
Logically exclusively 'or' register with register or immediate.
Detail
Rt = Ra ^ Rb
Rt = Ra ^ #imm
PAGE 38
C2..0
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Virtual Address63...13
Physical Address63...13
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k q X Z Z Z Z Z Z p Z 2 mv H\ " j\ " mv mv Z 2 2 (Y (Y o M M M mv V 2 (Y 2 (Y X M mv X M M F h : (Y @xgnk# Ð D 0 | : " \ 2 p *t t r M the result is positive (and not zero)17SEzero =the result is zero (negative or positive)16SIinf ?the result is infinite or quiet NaNException Occurrence15X6swt{reserved} - set this bit using software to trigger an invalid operation14X5inerx- inexact result exception occurred (sticky)13X4dbzx- divide by zero exception occurred12X3underx- underflow exception occurred11X2overx- overflow exception occurred10X1giopx- global invalid operation exception set if any invalid operation exception has occurred9GXgx- global exception indicator set if any enabled exception has happened8SXsumx- summary exception set if any exception could occur if it was enabled
- can only be cleared by softwareException Type Resolution7X1Tcvt- attempt to convert NaN or too large to integer6X1Tsqrtx- square root of non-zero negative 5X1TNaNCmp- comparison of NaN not using unordered comparison instructions4X1Tinfzero- multiply infinity by zero3X1Tzerozero- division of zero by zero2X1Tinfdiv- division of infinities1X1Tsubinfx- subtraction of infinities 0X1Tsnanx- signaling NaN
RMRounding Mode0round towards nearest even1round towards zero (truncate)2round towards positive infinity3round towards negative infinity* add floating point invalid operation exception instruction
Hyper-Threading
The Raptor supports hyper-threading via the use of multiple contexts. The processor can switch in a controlled fashion between contexts on a cycle-by-cycle basis. Which context is active during any clock cycle depends on the list configured in the execution pattern registers (EPx). The core cycles through the entries in the execution registers using the context number (0-15) stored in the list register to determine the next context to use during execution. Execution context zero is reserved for processing hardware exceptions. When a hardware exception occurs, the processor automatically forces execution context zero to become active, overriding the contents of the execution pattern list.
Interrupts
Interrupts cause an automatic transfer of processor execution to context zero.
This processor supports interrupts and exceptions in the form of a system call instruction. When a hardware interrupt or program exception occurs the appropriate system call instruction is forced into the processor's internal instruction pipeline (this is accomplished by hardware internal to the processor). There are several pre-defined exception numbers for specific vectors in order to support hardware interrupts as listed in the table below. An exception vectors to the handler whose address is located by combining the exception number (a field in the system call instruction) with the base address stored in the vector base address register (VBA). The REX1 (return from exception) instruction is used to return from an exception routine.
Occurrence of an exception results in the status register being copied to the back up version, the maskable interrupt mask being set to disable further interrupts, and the exception return address being copied to XRA, so that these may be restored by the exception return operation. The processor is also switched to system mode, which enables registers and instructions available only to system mode.
Interrupt Vector Table
The interrupt vector table is a table of 512 entries containing the addresses of routines that may be called using the system call instruction (SYS). They may also be called during hardware interrupt processing. The location of the table in memory is controlled by the vector base address register (VBA) which on reset is set to $0000_0000_0000_0000, effectively placing the vector table in the first 4KiB of memory.
The reset vector and non-maskable interrupt vectors are not governed by the VBA and have fixed addresses in memory of $FFFF_FFFF_FFFF_FFF8 and $FFFFFFFF_FFFF_FFF0 respectively.
The last 64 entries in the table are reserved for interrupts that the processor might generate. The remaining entries are free for use as needed by the operating system.
Entry #DescriptionOperating System ( reserved)0BIOS (32 reserved)416RTC417KeyboardNetworkMass Storage447Processor Hardware Exceptions (64 reserved)448spurious interrupt449hardware interrupt level 1450hardware interrupt level 2......479hardware interrupt level 31480-487{reserved}488division by zero489-493{reserved}494illegal instruction address495unimplemented instruction496-509{reserved}510reserved - Non-maskable interrupt vector511reserved - Reset Vector Program Flow Control
There are four basic flow control instructions (JAL, Bcc, RET, and SYS).
JAL is an unconditional program flow transfer instruction.
The Bcc instructions are conditional transfers.
The RET instruction is a return instruction that also performs an add operation,
and the SYS instruction is used to invoke exception handlers.
Compare Operation
Conditional program flow instructions are guided by comparisons. The comparisons may be performed directly by the branch instruction, or via one of the datapath comparison instructions such as a floating point comparison. The compare instruction compares either two registers or a register and an immediate value and writes the result of the comparison to the target register. The target register will be written with a one to represent a true value or a zero for false. There are six basic relational comparison operations than can be performed (equal, not equal, less than, less than or equal, greater than or greater than or equal).
There are six integer comparison instructions which cover the standard relational comparisons for signed values.( HYPERLINK \l "CLT" SLT, HYPERLINK \l "CGE" SGE, HYPERLINK \l "CLE" SLE, HYPERLINK \l "CGT" SGT, HYPERLINK \l "CEQ" SEQ, HYPERLINK \l "CNE" SNE).
There are two additional comparison operations ( HYPERLINK \l "CMP" CMP, HYPERLINK \l "CMP" CMPU) which perform a relational comparison between a register and either another register or immediate value; and place the result of the comparison to the target register. For these two instructions the target register is written with -1 to indicate the first operand is less than the second, 0 to indicate that both operands are the same, and +1 to indicate that the first operand is greater than the second. CMP performs a signed comparison, CMPU performs an unsigned comparison.
Branches
Overview
Branches are the most frequent form of program flow control operation and are usually performed in a conditional manner.Branches are integrated with compare operations allowing a comparison and a branch to be processed as one unit for improved code density and performance.
Targets
Branch target addresses are determined in one of two fashions; the branch target may be an absolute address stored in a register, or it may be a relative address specified by a field in the branch instruction itself. The processor allows a twelve bit target address field which covers virtually 100% of branch cases.
If the top four bits of target field have the value 8 then the lower six bits of the target field specify a register that contains the target address, otherwise the target address is determined as described below.
Packet-Relative Addresses
When the branch target is not coming from a register, the branch target field contains a packet relative address and an absolute instruction slot number. This mechanism allows for easy relocation of code on packet boundaries. The twelve bit target field is split into two subfields a relative packet displacement and the instruction slot number. The relative packet displacement is used to determine which instruction packet is the target relative to the packet of the branch instruction. The slot number indicates which slot within the target packet is the target for the branch. The slot number must have a value of 0, 1, or 2.
Packet displacements may vary from -448 to +511 packets. (The symmetry in the range is due to the allowance for register targets.
Target Field Specifier (non-register targets)
11 21 0Packet DisplacementSlotTarget Field Specifier (register targets)
11 87 65 084~2Reg6
Branch Conditions
A standard set of branch conditions is provided, outlined in the table below. The branch conditional is determined by comparing the two registers or a register and a small immediate value specified by the branch instruction. The branch architecture is such that it is possible to branch based directly on a value in a register. The ISA features logical tests in addition to the regular relational tests.
Branch Conditions
MnemonicDescriptionConditional TestHYPERLINK \l "Bcc"BLTBranch if Less Thana < bHYPERLINK \l "Bcc"BGEBranch if Greater than or Equala >= bHYPERLINK \l "Bcc"BLEBranch if Less than or Equala <= bHYPERLINK \l "Bcc"BGTBranch if Greater Thana > bHYPERLINK \l "Bcc"BEQ / BXNORBranch if Equala == bHYPERLINK \l "Bcc"BLTUBranch if Less Thana < bHYPERLINK \l "Bcc"BGEUBranch if Greater than or Equala >= bHYPERLINK \l "Bcc"BLEUBranch if Less than or Equala <= bHYPERLINK \l "Bcc"BGTUBranch if Greater Thana > bHYPERLINK \l "Bcc"BNE / BXORBranch if Not Equala <> bHYPERLINK \l "Bcc"BANDBranch if both truea and bHYPERLINK \l "Bcc"BORBranch if either truea or b
Method Invocation (Jumps and Calls)
Methods may be invoked by the HYPERLINK \l "CALL"JAL. instruction. JAL automatically stores the method return address in the return address link register (R47). A method return instruction (HYPERLINK \l "RET"RET) is used to return from a method by restoring the program counter from the return address register.
The HYPERLINK \l "JAL"JAL instruction is a simple powerful instruction common in many newer architectures that provides for most common program flow transfer operations that are not covered by branches. The JAL instruction is a generic unconditional program flow control instruction. This single instruction can perform regular jump, method call and return operations, interrupt call and return operations, using absolute or register indirect addresses. The default form of the JAL instruction where the return address is stored in the return address register (R47) may referred to as a CALL in assembly language. When a jump (HYPERLINK \l "JMP"JMP) is required, the register to store the return address in may be specified as R0 (R0 will not be updated). When R63 is used to store the return address, the JAL instruction is assumed to be an interrupt or system call. When R63 is used to indirectly specify the target address, the JAL instruction is assumed to be an interrupt or system call return. As an interrupt or system call or return, the control bits are exchanged with the backup versions in the processor control register.
The JAL instruction may be used to perform program counter relative calls with the use of the program counter alias register, or program offset based calls by loading a register with the address of the program. JAL may target absolute addresses in memory by setting the target register field to R0.
JAL forms a target address by adding a register and immediate value, or two registers. The address generated is treated as an instruction address (Its not a byte address).
System Calls and Interrupts
Calls to the operating system or interrupt routines may be made using the system call (HYPERLINK \l "SYS"SYS) instruction. Returns from system routines may be made using the HYPERLINK \l "RTX"RTX instruction. Note that the system call (SYS) and exceptions return (RTX) instructions are really specialized forms of the JAL instruction mentioned above. System, interrupt calls and returns cause transfers between processor control bits and their alternates. The system call instruction automatically places the processor in system mode.
Datapath Operations
Immediate Constants
Large immediate values used in integer arithmetic operations may be loaded into registers with the SETLO and SETHI instructions. SETLO loads the register with a thirty-two bit value thats sign extended to the width of the register. The SETHI instruction loads the upper half of a register with the specified thirty-two bit value. The low order half of the register is unaffected.
Integer Operations
Integers are represented using twos complement notation.
Addition / Subtraction / Multiply / Divide
Basic addition (HYPERLINK \l "ADD"ADD) and subtraction (HYPERLINK \l "SUB"SUB) operations are supported. Addition and subtraction work with both signed and unsigned values.
Multiplication and division of signed numbers are supported by the ISA with the HYPERLINK \l "MUL"MUL, HYPERLINK \l "MULH"MULH and HYPERLINK \l "DIV"DIV instructions A remainder function (HYPERLINK \l "MOD"MOD) is also available. The MULH instruction returns the high order thirty-two bits of a signed multiply operation.
Comparisons
There are ten comparison instructions performing signed and unsigned comparisons between two registers or a register and an immediate value ( HYPERLINK \l "Ccc" SLT, HYPERLINK \l "Ccc" SLE, HYPERLINK \l "Ccc" SGT HYPERLINK \l "Ccc" SGE, HYPERLINK \l "Ccc" SLTU, HYPERLINK \l "Ccc" SLEU, HYPERLINK \l "Ccc" SGTU HYPERLINK \l "Ccc" SGEU, HYPERLINK \l "Ccc" SEQ, and HYPERLINK \l "Ccc" SNE).
Logical Operations
The processor supports a standard set of logical operations including and (HYPERLINK \l "AND"AND), or (inclusive)(HYPERLINK \l "OR"OR), and exclusive or (HYPERLINK \l "XOR"XOR). An additional derived operation is HYPERLINK \l "NOT"NOT which is an alternate form of the XOR instruction. The primary logical operations support both register and immediate forms. There are three more additional secondary logical operations (HYPERLINK \l "NAND"NAND, HYPERLINK \l "NOR"NOR, and HYPERLINK \l "XNOR"XNOR) which have only register formats.
Shifts
The ISA supports a full complement of shift instructions. Left shifts are supported via the HYPERLINK \l "SHL"SHL instruction. Right shifts are supported with arithmetic (HYPERLINK \l "ASR"ASR) and logical (HYPERLINK \l "SHR"SHR) shifts. Rotates are supported via the rotate left HYPERLINK \l "ROL"ROL and rotate right HYPERLINK \l "ROR"ROR instructions.
BitField Operations
The processor has support for bitfield operations via the HYPERLINK \l "BFINS"BFINS (bitfield insert) and HYPERLINK \l "BFEXT"BFEXT (bitfield extract) instructions. An additional bitfield operation is the HYPERLINK \l "BFCLR"BFCLR (bitfield clear) instruction which is an extended mnemonic for the BFINS instruction.
Floating Point Operations
Addition / Subtraction / Multiply / Divide
Basic addition (HYPERLINK \l "ADD"FADD), subtraction (HYPERLINK \l "SUB"FSUB), multiplication ( HYPERLINK \l "FMUL" FMUL) and division ( HYPERLINK \l "FDIV" FDIV) operations are supported.
Absolute Value / Negation / Sign Determination / Fractional Extraction
Absolute value (FABS), negation (FNEG), sign determination (FSGN), fractional extraction (FMAN) are supported.
Numeric Conversions
Conversions between integer and floating point values are handled with the float-to-int (F2INT) and int-to-float instructions (INT2F).
Comparisons
There are five floating point comparison instructions; four are relational comparisons, the fifth tests for ordering of operands. (FCLT, FCLE, FCEQ, FCNE, FCOR). The floating point comparisons compare the values in two registers and set the target register to true if the comparison is true. Other comparisons may be synthesized from existing instructions; for example, by switching the operands around.
Other Instructions
A random floating point value may be obtained using the GRAF (Get RAndom Float) instruction.
Memory Operations
Endian
The Raptor is a little endian processor. The least significant byte is at the lowest address.
Operations
The Raptor is a load / store architecture; the only operations accessing memory are load and store operations. The processor supports byte (8 bit), character (16 bit), half-word (32 bit), and word (64 bit) loads and stores of data to memory.
The ISA supports address update forms of the load / store instructions, where the addressing register is updated with the calculated effective address after the load / store operation is complete. Indexed address mode is also supported. There are instructions which automatically unpack and pack floating point values for transfer to or from memory.
There are numerous load and store instructions (not all are shown) which support the following operations:
operationsuffix characterSample Mnemonicsdefault / sign extension (loads)noneHYPERLINK \l "LB"LB HYPERLINK \l "LH"LH HYPERLINK \l "LW"LW HYPERLINK \l "SB"SB HYPERLINK \l "SH"SH HYPERLINK \l "SW"SWzero extension (loads)ZHYPERLINK \l "LBZ"LBZ HYPERLINK \l "LHZ"LHZindexed operationLB LH LW SB SH SW FLS FSS
LBZ LHZ floating point conversionLF SF
Data Alignment 32-bit
Memory is byte addressable; character, half-word and word accesses must be aligned on their respective address boundaries.
Bytes may be loaded from any memory address.
3210
Characters may be loaded from any memory address, except an address where the least significant two bits are 11.
201
CLB
If the address ends in 11, then the byte is loaded into register bits 9 to 15; otherwise the instruction is treated as NOP.
0
6420531
01234
23
Data Alignment
Memory is byte addressable; character, half-word and word accesses must be aligned on their respective address boundaries.
Bytes may be loaded from any memory address.
76543210
Characters may be loaded from any memory address, except an address where the least significant three bits are 111.
When a character is loaded from an address ending in 111, the load is treated as if it were a byte load instruction. The lowest byte of the target register is loaded.
CLC
If the address ends in 11, then a byte is loaded into register bits 8 to 15; otherwise the instruction is treated as NOP.
6420531
CLH
If the address ends in 101, then a byte is loaded into register bits 24 to 31;
If the address ends in 110, then a character is loaded into register bits 16 to 31;
If the address ends in 111, then a character is loaded into register bits 8 to 31;
otherwise the instruction is treated as NOP.
01234
23
LCA
LCZA
If the address ends in 111, then 8 bits are loaded into register bits 8 to 15; otherwise the instruction is treated as NOP.
LHA
LHZA
If the address ends in 101, then a byte is loaded into register bits 24 to 31;
If the address ends in 110, then a character is loaded into register bits 16 to 31;
If the address ends in 111, then a character is loaded into register bits 8 to 31;
otherwise the instruction is treated as NOP.
LWA
If the address ends in 001, then 56 bits are loaded into register bits 8 to 63;
If the address ends in 010, then 48 bits are loaded into register bits 16 to 63;
If the address ends in 011, then 40 bits are loaded into register bits 24 to 63;
If the address ends in 100, then 32 bits are loaded into register bits 32 to 63;
If the address ends in 101, then 24 bits are loaded into register bits 40 to 63;
If the address ends in 110, then 16 bits are loaded into register bits 48 to 63;
If the address ends in 111, then 8 bits is loaded into register bits 56 to 63;
otherwise the instruction is treated as NOP.
Memory Map
The processor supports a 64 bit (or 2^64 Bytes) address space.
Opcode Formats
Ideally from a compiler's perspective the ISA should be able to support three operand instructions (one destination, two sources) including cases where all three operands are registers in order to allow a compiler to allocate registers more efficiently. This is commensurate with current compiler technology. This ISA supports the ideal condition.
Instruction Layout
Opcodes are forty-two bits in size. Instructions are placed three per instruction packet which must be aligned on 16-byte (128 bit) addresses.
127 126125 8483 4241 00--Opcode Slot 2Opcode Slot 1Opcode Slot 01--Opcode Slot 2Opcode Slot 1Opcode Slot 02--Opcode Slot 2Opcode Slot 1Opcode Slot 0--30--Opcode Slot 2Opcode Slot 1Opcode Slot 031--Opcode Slot 2Opcode Slot 1Opcode Slot 0
Opcode Formats
There are several different opcode formats, see the subsequent tables for specific formats. The major opcode formats are shown below. All instructions begin with a seven bit field in the most significant bits which determines the major opcode grouping or instruction.
S-Type
Usage: SETHI, SETLO
Set register,
41 3837 3231 0Opcode4RegT6immediate32
I-Type
Usage: Register-immediate instructions,
loads and stores with displacements,
jump and link
41 3534 2928 2322 0Opcode7RegA6RegT6immediate23
R-Type
Usage: Register-Register instructions and loads and stores using indexed addressing
41 3534 2928 2322 1716 65 0Opcode7RegA6RegT6RegC6Opcode11RegB6
B-Type
Usage: Branches
41 3534 2928 1716 0Opcode7RegA6target12Immediate17
BF Type
Usage: Bitfield operations
41 3534 2928 2322 1716 1211 65 0Opcode7RegA6RegT6RegC6Opcode5Width6Start6
Detailed Opcode Formats
Op4Imm10Rt6Imm23SETOp6Typ2Ra6Rt6Imm22ImmOp6Typ2Ra6Rt6Rc6Op10Rb6RegOp6Typ2Ra6Rt6Rc6Op4Wd6St6BFCOp6Typ2Ra6Rt6Rc6Op4Wd6Rb6BFROp6Typ2Ra6target12Imm16BranchOp6Typ2Ra6326Rc6Imm16BranchOp6Typ2Ra6target12Op8Rb6BranchOp6Typ2Ra6326Rc6Op8Rb6Branch
BR-Type Branches
Usage: Register-Register comparison branches
41 3635 3231 2625 14 13 65 0Opcode6Typ4RegA6target12~8RegB6
41 3635 3231 2625 2019 1413 65 0Opcode6Typ4RegA61000006RegC6~8RegB6
BI-Type
Usage: Register-Immediate comparison branches
41 3635 3231 2625 1413 0Opcode6Typ4RegA6target12Immediate14
41 3635 3231 2625 2019 1413 0Opcode6Typ4RegA61000006RegC6Immediate14
BFC Type
Bitfield, constant field index
41 3635 3231 2625 2019 1413 1211 65 0Opcode6Opcode 4RegA6RegT6RegC6Opcode2Width6Start6
BFR Type
Bitfield, register field index
41 3635 3231 2625 2019 1413 1211 65 0Opcode6Opcode 4RegA6RegT6RegC6Opcode2Width6RegB6
Op7Ra5Rt5Imm250MiscMiscellaneous1Ra5Rt5Rc6Op11Rb6{reg}register operate2Ra5Rb5Rt5Op1347ADD2Ra5Rb5Rt5Op1357{reg}2Ra5Rb5Rt5Op1367CMP2Ra5Rb5Rt5Op1377CMPU2Ra5Rb5Rt5Op1387AND2Ra5Rb5Rt5Op1397OR2Ra5Rb5Rt5Op13107XOR2Ra5Rb5Rt5Op13117ANDC2Ra5Rb5Rt5Op13127NAND2Ra5Rb5Rt5Op13137NOR2Ra5Rb5Rt5Op13147XNOR2Ra5Rb5Target1880BLTa < b2Ra5Rb5Target1881BGEa >= b2Ra5Rb5Target1882BLEa<=b2Ra5Rb5Target1883BGTa >b2Ra5Rb5Target1884BLTUa < b2Ra5Rb5Target1885BGEUa >=b2Ra5Rb5Target1886BLEUa <=b2Ra5Rb5Target1887BGTUa > b2Ra5Rb5Target1888BEQa == b2Ra5Rb5Target1888BEQa == b2Ra5Rb5Target1890BRA12Ra5Rb5Target1891BRN02Ra5Rb5Target1892BANDa && b2Ra5Rb5Target1893BORa || b32Ra5Rb5Rt5Op1396SLT2Ra5Rb5Rt5Op1396SLT2Ra5Rb5Rt5Op1398SGT2Ra5Rb5Rt5Op1399SGE2Ra5Rb5Rt5Op13100SLTU2Ra5Rb5Rt5Op13101SLTU2Ra5Rb5Rt5Op13102SGTU2Ra5Rb5Rt5Op13102SGTU2Ra5Rb5Rt5Op13104SEQ2Ra5Rb5Rt5Op13105SNE3Basic Arithmetic4Ra5Rt5Imm25ADDIAdd immediate5Ra5Rt5Imm256Ra5Rt5Imm25CMPICompare immediate7Ra5Rt5Imm25CMPUIUnsigned compare immediate8Ra5Rt5Imm25ANDIAnd9Ra5Rt5Imm25ORIOr10Ra5Rt5Imm25XORIExclusive or11Ra5Rt5Imm25DIVdivide12Ra5Rt5Imm25MULHmultiply13Ra5Rt5Imm25MODmodulus141516Rt6Ra6Imm23EORbits 0-2217Rt6Ra6Imm23ANDbits 0-2218Rt6Ra6Imm23ORbits 0-2231{bitfield}24Address35CALLcall subroutine25Address35JMPjump26Ra5Rt5Address25JALjump and link27Ra5Rt5Imm25RETreturn and add
Memory Operations32Ra5Rt5disp25LBload byte, sign extend33Ra5Rt5disp25LCload character, sign extend34Ra5Rt5disp25LHload half-word, sign extend35Ra5Rt5disp25LWload word36Ra5Rt5disp25LPload pair37Ra5Rt5disp25LBUload byte, zero extend38Ra5Rt5disp25LCUload character, zero extend39Ra5Rt5disp25LHUload half-word, zero extend40Ra5Sprt5disp25LSHload special half-word41Ra5Sprt5disp25LSWload special word42Ra5Rt5disp25LFload float43Ra5Rt5disp25LFDload float double44Ra5Rt5disp25LFPload float pair45Ra5Rt5disp25LFDPload float double pair46Ra5Rt5disp25LWRload word, reserve address4748Ra5Rt5disp25SBstore byte (zero)49Ra5Rt5disp25SCstore character50Ra5Rt5disp25SHstore half-word51Ra5Rt5disp25SWstore word52Ra5Rt5disp25SPstore pair53reserved54reserved55reserved56Ra5Sprs5disp25SSHstore special half-word57Ra5Sprs5disp25SSWstore special word58Ra5Rb5disp25SFstore float59Ra5Rbt5disp25SFDstore float double60Ra5Rb5disp25SFPstore float pair61Ra5Rb5disp25SFDPstore float double pair62Ra5Rb5disp25SWCRstore word, clear address reservation63IO Operations64Ra5Rt5I/O Address25INBinput byte, sign extend65Ra5Rt5I/O Address25INCinput character, sign extend66Ra5Rt5I/O Address25INHinput half-word, sign extend67Ra5Rt5I/O Address25INWinput word68Ra5Rt5I/O Address25INBUinput byte, zero extend69Ra5Rt5I/O Address25INCUinput character, zero extend70Ra5Rt5I/O Address25INHUinput half-word, zero extend7172Ra5Rt5I/O Address25OUTBoutput byte73Ra5Rt5I/O Address25OUTCoutput character74Ra5Rt5I/O Address25OUTHoutput half-word75Ra5Rt5I/O Address25OUTWoutput word76777879
Flow Control80Ra5Target12Imm18BLTIbranch if less than81Ra5Target12Imm18BGEIbranch if greater or equal82Ra5Target12Imm18BLEIbranch if less or equal83Ra5Target12Imm18BGTIbranch if greater than84Ra5Target12Imm18BLOIbranch if lower85Ra5Target12Imm18BHSIbranch if higher or same86Ra5Target12Imm18BLSIbranch if lower or same87Ra5Target12Imm18BHIIbranch if higher88Ra5Target12Imm18BEQIbranch if equal89Ra5Target12Imm18BNEIbranch if not equal90Ra5Target12Imm18LEQIloop if equal91Ra5Target12Imm18LNEIloop if not equalRelational Compares96Ra5Rt5Imm25SLTIa < b97Ra5Rt5Imm25SGEIa >= b98Ra5Rt5Imm25SLEIa <= b99Ra5Rt5Imm25SGTIa > b100Ra5Rt5Imm25SLTUIa < b101Ra5Rt5Imm25SGEUIa >= b102Ra5Rt5Imm25SLEUIa <= b103Ra5Rt5Imm25SGTUIa > b104Ra5Rt5Imm25SEQIa == b105Ra5Rt5Imm25SNEIa != b106107108109Ra5Rt5Funct7FPLOOFloating point109Ra5Rt513I2FInteger to float109Ra5Rt514F2IFloat to integer110Ra5Rt5Funct7FPZLFloating point110Ra5Rt50FABSFloating point absolute value110Ra5Rt51FNABSFloating point neg. absolute110Ra5Rt52FNEGFloating point negate110Ra5Rt53FMOVFloating point move110Ra5Rt54FSIGNFloating point get sign110Ra5Rt55FMANFloating point get mantissa110Ra5Rt56110Ra5Rt57110Ra5Rb5Rt58FCLTa < b110Ra5Rb5Rt59FCGEa >= b110Ra5Rb5Rt510FCLEa <= b110Ra5Rb5Rt511FCGTa > b110Ra5Rb5Rt512FCEQa == b110Ra5Rb5Rt513FCNEa <> b110Ra5Rb5Rt514FCUNFloating point unordered110Ra5Rb5Rt515FCORFloating point ordered111NOP73Imm39IMMImmediate prefix
Opcode Maps
Major Instruction Group
Bits 41-35
Opcode7Opcode35
MSB is down, LSB is across
01234567001234567{misc}{reg}{float} HYPERLINK \l "ADD" ADDM # HYPERLINK \l "SUB" SUBM # HYPERLINK \l "ADD" ADDH # HYPERLINK \l "SUB" SUBH #189101112131415 HYPERLINK \l "ADD" ADD # HYPERLINK \l "SUB" SUB # HYPERLINK \l "MUL" MUL # HYPERLINK \l "DIV" DIV # HYPERLINK \l "MULH" MULH # HYPERLINK \l "MOD" MOD #21617181920212223 HYPERLINK \l "XOR" XOR # HYPERLINK \l "AND" AND # HYPERLINK \l "OR" OR # HYPERLINK \l "MLO" MLO HYPERLINK \l "XOR" XORM # HYPERLINK \l "AND" ANDM # HYPERLINK \l "OR" ORM #32425262728293031 HYPERLINK \l "XOR" XORH # HYPERLINK \l "AND" ANDH # HYPERLINK \l "OR" ORH #{ HYPERLINK \l "BFINS" bitfield}43233343536373839LBLCLHLWLPLBZLCZLHZ54041424344454647LSHLSWLFLFDLFPLFDP HYPERLINK \l "DCACHE" {cache} HYPERLINK \l "DCACHE" {cacheu}64849505152535455SBSCSHSWSPSBZSCZSHZ75657585960616263SSHSSWSFSFDSFPSFDP86465666768697071INBINCINHINWINBZINCZINHZ97273747576777879OUTBOUTCOUTHOUTW108081828384858687 HYPERLINK \l "Bcc" BLT # HYPERLINK \l "Bcc" BLE # HYPERLINK \l "Bcc" BGT # HYPERLINK \l "Bcc" BGE # HYPERLINK \l "Bcc" BLTU # HYPERLINK \l "Bcc" BLEU # HYPERLINK \l "Bcc" BGTU # HYPERLINK \l "Bcc" BGEU #118889909192939495 HYPERLINK \l "Bcc" BEQ # HYPERLINK \l "Bcc" BNE # HYPERLINK \l "Bcc" BAND # HYPERLINK \l "Bcc" BNAND # HYPERLINK \l "Bcc" BOR # HYPERLINK \l "Bcc" BNOR #1296979899100101102103 HYPERLINK \l "JAL" JALRET HYPERLINK \l "JMP" JMP HYPERLINK \l "CALL" CALL HYPERLINK \l "NOP" NOP13104105106107108109110111 HYPERLINK \l "CLT" CLT # HYPERLINK \l "CGE" CLE # HYPERLINK \l "CLE" CGT # HYPERLINK \l "CGT" CGE # HYPERLINK \l "CLT" CLTU # HYPERLINK \l "CGE" CLEU # HYPERLINK \l "CLE" CGTU # HYPERLINK \l "CGT" CGEU #14112113114115116117118119 HYPERLINK \l "CEQ" CEQ # HYPERLINK \l "CNE" CNE # HYPERLINK \l "CLE" CMP # HYPERLINK \l "CGT" CMPU #15120121122123124125126127SETLOSETMIDSETHI
Register Instruction Group
Bits 12-6, Bits 41-35 = 4
17Ra6Rt6Rc6Opcode11Rb6
01234567001234567{misc}{ HYPERLINK \l "BFINS" bitfield}189101112131415 HYPERLINK \l "ADD" ADD HYPERLINK \l "SUB" SUB HYPERLINK \l "MUL" MUL HYPERLINK \l "DIV" DIV HYPERLINK \l "MULH" MULH HYPERLINK \l "MOD" MOD21617181920212223 HYPERLINK \l "XOR" XOR HYPERLINK \l "AND" AND HYPERLINK \l "OR" OR3242526272829303143233343536373839LBLCLHLWLPLBZLCZLHZ54041424344454647LSHLSWLFLFDLFPLFDP HYPERLINK \l "DCACHE" {cache} HYPERLINK \l "DCACHE" {cacheu}64849505152535455SBSCSHSWSP75657585960616263SSHSSWSFSFDSFPSFDP86465666768697071INBINCINHINWINBZINCZINHZ97273747576777879OUTBOUTCOUTHOUTW108081828384858687 HYPERLINK \l "Bcc" BLT HYPERLINK \l "Bcc" BLE HYPERLINK \l "Bcc" BGT HYPERLINK \l "Bcc" BGE HYPERLINK \l "Bcc" BLTU HYPERLINK \l "Bcc" BLEU HYPERLINK \l "Bcc" BGTU HYPERLINK \l "Bcc" BGEU118889909192939495 HYPERLINK \l "Bcc" BEQ HYPERLINK \l "Bcc" BNE HYPERLINK \l "Bcc" BAND HYPERLINK \l "Bcc" BNAND HYPERLINK \l "Bcc" BOR HYPERLINK \l "Bcc" BNOR1296979899100101102103 HYPERLINK \l "JAL" JALRET HYPERLINK \l "NOP" NOP13104105106107108109110111 HYPERLINK \l "CLT" CLT HYPERLINK \l "CGE" CLE HYPERLINK \l "CLE" CGT HYPERLINK \l "CGT" CGE HYPERLINK \l "CLT" CLTU HYPERLINK \l "CGE" CLEU HYPERLINK \l "CLE" CGTU HYPERLINK \l "CGT" CGEU14112113114115116117118119 HYPERLINK \l "CEQ" CEQ HYPERLINK \l "CNE" CNE HYPERLINK \l "CLE" CMP HYPERLINK \l "CGT" CMPU15120121122123124125126127SETLOSETMIDSETHI
01234567161281291301311321331341351713613713813914014114214318144145146147148149150151 HYPERLINK \l "XOR" XNOR HYPERLINK \l "AND" NAND HYPERLINK \l "OR" NOR191521531541551561571581592016016116216316416516616721168169170171172173174175221761771781791801811821832318418518618718818919019124192193194195196197198199 HYPERLINK \l "SHL" SHL # HYPERLINK \l "ROL" ROL # HYPERLINK \l "SHR" SHR # HYPERLINK \l "ASR" ASR # HYPERLINK \l "ASR" ROR #25200201202203204205206207 HYPERLINK \l "SHL" SHL HYPERLINK \l "ROL" ROL HYPERLINK \l "SHR" SHR HYPERLINK \l "ASR" ASR HYPERLINK \l "ROL" ROR26208209210211212213214215SRANDGRSGRINTGRAF27216217218219220221222223CPOPCLZCLO28224225226227228229230231292322332342352362372382393024024124224324424524624731248249250251252253254255
Miscellaneous Control
Bits 12-6, Bits 31-25 = 1
Bits 41-35
Opcode7Opcode35
Bits 12-6, Bits 41-35 = 4
07Ra6Rt6Rc6Opcode11Rb6
01234567001234567HYPERLINK \l "DI"DI HYPERLINK \l "EI" EI HYPERLINK \l "RI" RIFLUSH189101112131415 HYPERLINK \l "STOP" STOP HYPERLINK \l "END" END HYPERLINK \l "WAI" WAI21617181920212223 HYPERLINK \l "END" ENDsim1sim2sim3sim4sim5sim6sim732425262728293031swe0swe1swe2swe3swe4swe5swe6swe743233343536373839540414243444546476484950515253545575657585960616263 HYPERLINK \l "TRS" TRS HYPERLINK \l "TSR" TSR89101112131415
Floating Point Operations
Bits 12-6, Bits 41-35 = 4
27Ra6Rt6Rc6Opcode11Rb6
01234567001234567 HYPERLINK \l "FADD" FADD HYPERLINK \l "FSUB" FSUB HYPERLINK \l "FMUL" FMUL HYPERLINK \l "FDIV" FDIV189101112131415HYPERLINK \l "FABS"FABSHYPERLINK \l "FNABS"FNABS HYPERLINK \l "FNEG" FNEGFSIGNFMOVFMANFNOP21617181920212223 HYPERLINK \l "F2INT" F2INTINT2F32425262728293031 HYPERLINK \l "FCccS" FCLTFCGE HYPERLINK \l "FCccS" FCLEFCGT HYPERLINK \l "FCccS" FCEQ HYPERLINK \l "FCccS" FCNE HYPERLINK \l "FCccS" FCORFCNO43233343536373839540414243444546476484950515253545575657585960616263FSTATFRMFTXFCXFEXFDX86465666768697071 HYPERLINK \l "FADD" FADDD HYPERLINK \l "FSUB" FSUBD HYPERLINK \l "FMUL" FMULD HYPERLINK \l "FDIV" FDIVD97273747576777879HYPERLINK \l "FABS"FABSDHYPERLINK \l "FNABS"FNABSD HYPERLINK \l "FNEG" FNEGDFSIGNDFMOVDFMANDFNOPD108081828384858687 HYPERLINK \l "F2INT" F2INTDINT2FD118889909192939495 HYPERLINK \l "FCccS" FCLTDFCGED HYPERLINK \l "FCccS" FCLEDFCGTD HYPERLINK \l "FCccS" FCEQD HYPERLINK \l "FCccS" FCNED HYPERLINK \l "FCccS" FCORDFCNOD1296979899100101102103131041051061071081091101111411211311411511611711811915120121122123124125126127
Instruction Set Description
HYPERLINK \l "ADD" ADD HYPERLINK \l "AND" AND HYPERLINK \l "ASR" ASR HYPERLINK \l "Bcc" BAND HYPERLINK \l "Bcc" BEQ HYPERLINK \l "BFCHG" BFCHG HYPERLINK \l "BFCLR" BFCLR HYPERLINK \l "BFEXT" BFEXT HYPERLINK \l "BFINS" BFINS HYPERLINK \l "Bcc" BGE HYPERLINK \l "Bcc" BGT HYPERLINK \l "Bcc" BLE HYPERLINK \l "Bcc" BLT HYPERLINK \l "Bcc" BNAND HYPERLINK \l "Bcc" BNE HYPERLINK \l "Bcc" BNOR HYPERLINK \l "Bcc" BOR HYPERLINK \l "BRK" BRK HYPERLINK \l "Bcc" BXNOR HYPERLINK \l "Bcc" BXOR HYPERLINK \l "CALL" CALL HYPERLINK \l "Ccc" CEQ HYPERLINK \l "Ccc" CGE HYPERLINK \l "Ccc" CGT HYPERLINK \l "Ccc" CLE HYPERLINK \l "Ccc" CLT HYPERLINK \l "Ccc" CNE HYPERLINK \l "DI" DI HYPERLINK \l "DIV" DIV HYPERLINK \l "EI" EI HYPERLINK \l "END" END HYPERLINK \l "F2INT" F2INT HYPERLINK \l "FABS" FABS HYPERLINK \l "FADD" FADD HYPERLINK \l "FCccS" FCEQ HYPERLINK \l "FCccS" FCGE HYPERLINK \l "LB" LB HYPERLINK \l "LBU" LBULCLCU HYPERLINK \l "LH" LH HYPERLINK \l "LHU" LHULWLWCLWU HYPERLINK \l "MLO" MLO HYPERLINK \l "ROL" ROL HYPERLINK \l "ROR" ROR HYPERLINK \l "SB" SB HYPERLINK \l "SBU" SBUSCSCU HYPERLINK \l "SGN" SGN HYPERLINK \l "SH" SH HYPERLINK \l "SHL" SHL HYPERLINK \l "SHR" SHR HYPERLINK \l "SHU" SHU HYPERLINK \l "SUB" SUBSWSWU HYPERLINK \l "TRS" TRS HYPERLINK \l "TSR" TSR HYPERLINK \l "XNOR" XNOR HYPERLINK \l "XOR" XOR ADD Rt,Ra,Rb
ADD Rt,Ra,#n
Immediate Format:
41 3534 2928 2322 087Ra6Rt6immediate23
Register Format:
41 3534 2928 2322 1716 65 017Ra6Rt6~6811Rb6
Synopsis
'Add' register with register or immediate.
Detail
Rt = Ra + Rb
Rt = Ra + #imm
AND Rt,Ra,Rb
AND Rt,Ra,#n
Synopsis
Logically 'and' register with register or immediate.
Detail
Detail
Rt = Ra & Rb
Rt = Ra & #imm
ASR Rt,Ra,#cnt
ASR Rt,Ra,Rb
Synopsis
Arithmetically shift register right.
Detail
Rd = Rd ^>> Rb
The sign bit of the register is preserved during the shift.
Rt = Ra ^>> #cnt
Bcc Ra,#,label
Bcc Ra,Rb,label
Synopsis
Branch to label if condition is true
Detail
if register register compare
if Ra cond Rb is true then
if register form
pc = Rt
else
pc = pc + displacement
else
if Ra cond #n is true then
if register form
pc = Rt
else
pc = pc + displacement
Branch Conditions
MnemonicDescriptionConditional TestHYPERLINK \l "Bcc"BLTBranch if Less Thana < bHYPERLINK \l "Bcc"BGEBranch if Greater than or Equala >= bHYPERLINK \l "Bcc"BLEBranch if Less than or Equala <= bHYPERLINK \l "Bcc"BGTBranch if Greater Thana > bHYPERLINK \l "Bcc"BEQ / BXNORBranch if Equala == bHYPERLINK \l "Bcc"BNE / BXORBranch if Not Equala <> bHYPERLINK \l "Bcc"BANDBranch if both truea and bHYPERLINK \l "Bcc"BORBranch if either truea or b
Instruction Format:
BR-Type Branches
Usage: Register-Register comparison branches
41 3635 3231 2625 14 13 65 0Opcode6Typ4RegA6target12~8RegB6
41 3635 3231 2625 2019 1413 65 0Opcode6Typ4RegA61000xx6RegC6~8RegB6
BI-Type
Usage: Register-Immediate comparison branches
41 3635 3231 2625 1413 0Opcode6Typ4RegA6target12Immediate14
41 3635 3231 2625 2019 1413 0Opcode6Typ4RegA61000xx6RegC6Immediate14
BFCHG Rt,Ra,#bfb,#bfe
Synopsis
Insert into bitfield..
Detail
Rt[bfb:fbe] = Ra
Flip the bits between BFB (bit field begin) and BFE (bit field end) of Ra and transfer the result to Rt. (Ra is not altered).
BFCLR Rt,#bfb,#bfe
Synopsis
Clear bitfield..
Detail
Rt[bfb:fbe] = 0
Clear the bits between BFB (bit field begin) and BFE (bit field end) inclusive of Rt.
This is an extended mnemonic for the HYPERLINK "file:///O:\\IPCores\\raptor\\Documents\\raptor32.html" \l "BFINS#BFINS" BFINS instruction.
BFEXT Rt,Ra,#bfb,#bfe
Synopsis
Extract bitfield..
Detail
Rt = Ra[bfb:fbe]
Extract the bits between BFB (bit field begin) and BFE (bit field end) inclusive and transfer to the low order bits of Rt. The result in Rt is zero extended.
BFINS Rt,Ra,#bfb,#bfe
Synopsis
Insert into bitfield..
Detail
Rt[bfb:fbe] = Ra
Insert the low order bits from Ra into the bits between BFB (bit field begin) and BFE (bit field end) inclusive of Rt.
BRK
Synopsis
Call break exception handler.
Detail
XRA = pc; pc = mem[FFFF_F000]; status.backup = status; status.im = 1
This instruction causes the processor to perform a software initiated 'break' interrupt routine. It is purposely defined as a zero word so the processor will execute the break routine in the event that code flows into a region of memory that has been nulled out. This helps promote reliable system operation.
BSR label
Synopsis
Branch to subroutine.
Detail
R31 = pc;
pc[31:8] = pc[31:8] + {target[25:6]};
pc[7:0] = {target[5:0],00}
Call subroutine using program counter page relative offset address form. The twenty-six bit displacement is shifted left twice and sign extended to 32 bits before being used. Note the branch is made in a similar fashion to conditional branches. The low order six bits of the target are copied directly to the pc, while the upper twenty bits represent a page relative address.
desc:optargetsize:626bits:31 2625 0bit pattern:45d25..0 CALL d[Ra]
CALL label
Synopsis
Call subroutine
Detail
R47 = pc; pc = disp + Ra;
Call subroutine using register indirect with displacement mode. This is an alternate form of the HYPERLINK "file:///O:\\IPCores\\raptor\\Documents\\raptor32.html" \l "JAL#JAL" JAL instruction.
R47 = pc; pc = pc + displacement;
Call subroutine quick form. The twenty-five bit address field is shifted left twice and added to the program counter to form the target address. This allows an relative address call to a method within the same 64MB region of memory.
C Rt,Ra,Rb
C Rt,Ra,#n
Synopsis
'Compare' register with register or immediate.
Detail
Rt = Ra cond Rb
Rt = Ra cond #imm
This instruction performs a comparison of two values and stores the result (1 if condition is true, 0 otherwise) in the target register.
Compare Conditions
CMP Rt,Ra,Rb
CMP Rt,Ra,#n
CMPU Rt,Ra,Rb
CMPU Rt,Ra,#n
Synopsis
CMP: 'Compare' register with register or immediate.
CMPU: Unsigned compare of register with register or immediate
Detail
Rt = Ra cond Rb
Rt = Ra cond #imm
This instruction performs a comparison of two values and stores the result in the target register. If the first value is less than the second one, -1 is written to the target register. If the two values are equal, zero is written to the target register. If the first value is greater than the second one +1 is written to the target register. This instruction may also be used to obtain the sign of a value by comparing the value to zero.
CP1 #imm
CP2 #imm
Synopsis
Constant prefix
The upper bits of the immediate constant are set for the next instruction, overriding sign extension of the immediate.
The constant prefix instruction (CP1) indicates the presence of an additional twenty-eight constant bits in the instruction stream intended to represent significant bits 9 to 36 for the immediate constant of next instruction. These bits will take precedence over sign extension of the constant for the next instruction. CP1 sign extends from bit 37 to 64 bits.
The constant prefix instruction (CP2) adds twenty-seven more bits to the immediate constant of the following instruction, overriding any sign extension and substituting for bits 57 to 63.
Constant prefix instructions do not require the presence of other constant prefix instructions. For example CP2 may be used without CP1. CP1 may be used without CP2.
When multiple prefix are present the constant prefix instructions should be issued in the order CP1 then CP2 to ensure a properly built constant.
Interrupts are prevented from occurring between this instruction and the next instruction. Normally this instruction is automatically inserted by the assembler wherever an extended constant value is required.
DI
Synopsis
Disable interrupts.
Detail
status.im = 1
This instruction disables maskable hardware interrupts by setting the interrupt mask in the processor control register. It also disables the HYPERLINK "file:///O:\\IPCores\\raptor\\Documents\\raptor32.html" \l "NMI#NMI" IRQ instruction.
DIV Rt,Ra,Rb
DIV Rt,Ra,#n
Synopsis
Divide register by register or immediate.
Detail
Rt = Ra / Rb
Rt = Ra / #imm
This is a signed division operation. Division by zero will cause an exception.
EI
Synopsis
Enable interrupts.
Detail
status.im = 0
This instruction enables maskable hardware interrupts by clearing the interrupt mask in the status register. Enabling interrupts occurs after a minimum of one clock cycle delay.
END
Synopsis
No operation.
Detail
This instruction is provided for use in a software emulator of the processor. It indicates the end of a sequence of instructions to emulate. The processor will treat this instruction as a NOP instruction. This instruction is not meant to be used by actual hardware.
F2INT Rt,Ra
Synopsis
Floating point convert single precision to integer. Register to register.
Detail
Rt = int(Ra)
FABS Rt,Ra
Synopsis
Take floating point absolute value of register.
Detail
Rt = Ra;
Rt.sign = 0;
This instruction simply clears the sign bit of register.
FADD Rt,Ra,Rb
Synopsis
Floating point addition. Add register with register.
Detail
Rt = Ra + Rb
FCLT Rt,Ra,Rb
FCLE Rt,Ra,Rb
FCGT Rt,Ra,Rb
FCGE Rt,Ra,Rb
FCEQ Rt,Ra,Rb
FCNE Rt,Ra,Rb
FCOR Rt,Ra,Rb
Synopsis
Floating point single precision comparison, register with register.
Detail
Rt = Ra cond Rb
This instruction performs a comparison of two values and stores a one (true) or zero (false) to the target register depending on the whether the tested condition is true or false.
Compare Conditions
FDIV Rt,Ra,Rb
Synopsis
Floating point division. Divide register by register.
Detail
Rt = Ra / Rb
desc:opRaRtXopRbsize:655565bits:31 2625 2120 1615 1110 65 0bit pattern:3R4..0R4..0~3R4..0This instruction may cause a division by zero exception.
FIP
Synopsis
Flush instruction pipeline.
Detail
flags.im = 0
desc:opcode~opcode~size:61565bits:31 2625 1110 54 0bit pattern:0~6~This instruction flushes the processors instruction pipeline of all instructions following the FIP instruction.
Flags Affected
I0-------
FMUL Rt,Ra,Rb
Synopsis
Floating point multiplication. Multiply register by register.
Detail
Rt = Ra * Rb
desc:opRaRtXopRbsize:655565bits:31 2625 2120 1615 1110 54 0bit pattern:3R4..0R4..0~2R4..0
FNABS Rt,Ra
Synopsis
Take floating point negative absolute value of register.
Detail
Rt = Ra
Rt[31] = 1
desc:opRaRt~op~size:655565bits:31 2625 2120 1615 1110 54 0bit pattern:3R4..0R4..0~9~This instruction simply sets the sign bit of register.
FNEG Rt,Ra
Synopsis
Negate floating point value in register.
Detail
Rt = Ra
Rt[31] = ~Ra[31]
desc:opRaRt~op~size:655565bits:31 2625 2120 1615 1110 54 0bit pattern:3R4..0R4..0~10~This instruction simply complements the sign bit of register.
FSUB Rt,Ra,Rb
Synopsis
Floating point subtraction. Subtract register from register.
Detail
Rt = Ra - Rb
desc:opRaRtXopRbsize:655565bits:31 2625 2021 1615 1110 54 0bit pattern:3R4..0R4..0~1R4..0
IRQ
Synopsis
Run irq routine.
Detail
R30 = pc; pc = FFFF_FFF4; flags.backup = flags; flags.im = 1
desc:opRaRtdisp.size:65516bits:31 2625 2120 1615 0bit pattern:44030$FFFD15..0This instruction causes the processor to perform a software initiated maskable interrupt routine. It has the same effect as an external hardware maskable interrupt. If the interrupt mask in the status register is set, then this instruction will be ignored. This is an alternate form of the HYPERLINK "file:///O:\\IPCores\\raptor\\Documents\\raptor32.html" \l "JAL#JAL" JAL instruction.
Flags Affected
I1-------
JAL Rt,d[Ra]
Synopsis
Jump and link to subroutine
Detail
Rt = pc + 4; pc = disp + Ra;
Jump to subroutine using register indirect with displacement mode. The current value of the program counter is stored in the destination register. Normally this instruction will be used with a constant prefix.
desc:opRaRtdispsize:65516bits:31 2625 2120 1615 0bit pattern:44R4..0R4..0n15..0
JMP d[Ra]
JMP address
Synopsis
Jump to address
Detail
pc = disp + Ra;
Jump using register indirect with displacement mode. This is an alternate form of the HYPERLINK "file:///O:\\IPCores\\raptor\\Documents\\raptor32.html" \l "JAL#JAL" JAL instruction.
desc:opRtRadisp.size:65516bits:31 2625 2120 1615 0bit pattern:440R4..0d15..0pc = {pc[31:28],address,00};
Jump to address quick form. The twenty-six bit address field is shifted left twice and concatenated to the upper 4 bits of the program counter to form the target address. This allows an absolute address jump to a target within the same 256MB region of memory.
desc:opaddresssize:626bits:31 2625 0bit pattern:47address27..2
LB Rt,d[Ra]
LBRt,[Ra + Rb]
Synopsis
Load register byte from memory
Detail
Rt = Memory8 [Ra + disp]
desc:OpRaRtdispsize:76623bits:41 3534 2928 2322 0bit pattern:48R5..0R5..0d22..0Rt = Memory8 [Ra + Rb]
desc:OpRaRt~opRbsize:655565bits:31 2625 2120 1615 1110 54 0bit pattern:2R4..0R4..0~48R4..0The byte loaded from memory is sign extended to the register width.
LBZ Rt,d[Ra]
LBZ Rt,[Ra+Rb]
Synopsis
Load register byte from memory
Detail
Rt = Memory8 [Ra + disp]
desc:OpRaRtdispsize:65516bits:31 2625 2120 1615 0bit pattern:49R4..0R4..0d15..0Rt = Memory8 [Ra + Rb]
desc:OpRaRt~opRbsize:655565bits:31 2625 2120 1615 1110 54 0bit pattern:2R4..0R4..0~49R4..0The byte loaded from memory is zero extended to the register width.
LEA Rt,d[Ra]
LEA Rt,[Ra+Rb]
Synopsis
Load effective address.
Detail
Rt = Ra + Rb
desc:opRaRt~opRbsize:655565bits:31 26252120 1610 610 54 0bit pattern:2R4..0R4..0~4R4..0Rt = Ra + #imm
desc:opRaRtimmsize:65516bits:31 2625 2120 1615 0bit pattern:4R4..0R4..0n15..0The effective address is loaded into the target register. This instruction is an alternate form of the HYPERLINK "file:///O:\\IPCores\\raptor\\Documents\\raptor32.html" \l "SBC#SBC" ADD instruction.
LF Rt,d[Ra]
LF Rt,[Ra+Rb]
Synopsis
Load floating point register word from memory
Detail
Rt = funpack(memory32[Ra + disp])
desc:opRaRtdisp.size:65516bits:31 2625 2120 1615 0bit pattern:56R4..0R4..0d15..0
Rt = funpack(memory32 [Ra + Rb])
desc:OpRaRs~opRbsize:655565bits:31 2625 2120 1615 1110 54 0bit pattern:2R4..0R4..0~56R4..0Load floating point value from memory and unpack the value into register Rt.
LH Rt,d[Ra]
LH Rt,[Ra+Rb]
Synopsis
Load register half-word from memory
Detail
Rt = Memory16 [Ra + disp]
desc:OpRaRtdispsize:65516bits:31 2625 2120 1615 0bit pattern:50R4..0R4..0d15..0Note the format of the displacement field. D0 is forced to zero because half-word accesses must be half-word aligned.
Rt = Memory16 [Ra + Rb]
desc:opRaRt~opRbsize:655565bits:31 2625 2120 1615 1110 54 0bit pattern:2R4..0R4..0~50R4..0The half-word loaded from memory is sign extended to the register width.
LHZ Rt,d[Ra]
LHZ Rt,[Ra+Rb]
Synopsis
Load register half-word from memory
Detail
Rt = Memory16 [Ra + disp]
desc:OpRaRtdispsize:65516bits:31 2625 2120 1615 0bit pattern:51R4..0R4..0d15..0Note the format of the displacement field. D0 is forced to zero because half-word accesses must be half-word aligned.
Rt = Memory16 [Ra + Rb]
desc:opRaRt~opRbsize:655565bits:31 2625 2120 1615 1110 54 0bit pattern:2R4..0R4..0~51R4..0The half-word loaded from memory is zero extended to the register width.
LW Rt,d[Ra]
LW Rt,[Ra+Rb]
Synopsis
Load register word from memory
Detail
Rt = Memory32 [Ra + disp]
desc:OpRaRtdispsize:65516bits:31 2625 2120 1615 0bit pattern:52R4..0R4..0d15..0Note the format of the displacement field. D1..0 is forced to zero because word accesses must be word aligned.
Rt = Memory32 [Ra + Rb]
desc:opRaRt~opRbsize:655565bits:31 2625 2120 1615 1110 54 0bit pattern:2R4..0R4..0~52R4..0
MLO Rt,Ra,Rb,Rc
Synopsis
Mystery logical operation register with register.
Detail
Rt = Ra Rb
Perform a logical operation between Ra and Rb and place result in target register Rt. The operation to be performed is determined by the low order three bits of register Rc. This instruction is used to avoid switch case statements (branches) where the logical operation to be performed may be determined at run time. There is no immediate form for this instruction.
Opcode:
R Type
Register-Register Datapath
31 2524 1918 1312 11 65 0Opcode7Ra6Rt6-1Rc6Rb6
register valueoperation0exclusive or1and2inclusive or3{reserved}4exclusive nor5nand6nor7{reserved}
MOD Rt,Ra,Rb
MOD Rt,Ra,#n
Synopsis
Get remainder from divide of register by register or immediate.
Detail
Rt = Ra % Rb
desc:opRaRt~opRbsize:655565bits:31 2625 2120 1615 1110 54 0bit pattern:2R4..0R4..0~15R4..0Rt = Ra % #imm
desc:opRaRtimmsize:65516bits:31 2625 2120 1615 0bit pattern:15R4..0R4..0n15..0This is a signed division operation. The remainder of the division is placed in the target register Rt. MUL Rt,Ra,Rb
MUL Rt,Ra,#n
Synopsis
Multiply register with register or immediate.
Detail
Rt = Ra * Rb
desc:opRaRt~opRbsize:655565bits:31 2625 2120 1615 1110 54 0bit pattern:2R4..0R4..0~6R4..0Rt = Ra * #imm
desc:opRaRtimmsize:65516bits:31 2625 2120 1615 0bit pattern:6R4..0R4..0n15..0This is a signed multiply operation. The low order 32 bits of the result are placed in the target register.
MULH Rt,Ra,Rb
MULH Rt,Ra,#n
Synopsis
Multiply register with register or immediate; return high order bits.
Detail
Rt = Ra * Rb
desc:opRaRt~opRbsize:655565bits:31 2625 2120 1615 1110 54 0bit pattern:2R4..0R4..0~14R4..0Rt = Ra * #imm
desc:opRaRtimmsize:65516bits:31 2625 2120 1615 0bit pattern:14R4..0R4..0n15..0This is a signed multiply operation. The high order 32 bits of the result are placed in the target register.
NAND Rt,Ra,Rb
Synopsis
Logically ''nand' register with register.
Detail
Rt = ~(Ra & Rb)
desc:opRaRt~opRbsize:655565bits:31 2625 2120 1615 1110 54 0bit pattern:2R4..0R4..0~17R4..0There is no immediate form for this instruction.
NMI
Synopsis
Run nmi routine.
Detail
R30 = pc; pc = FFFF_FFF8; flags.backup = flags; flags.im = 1
desc:opRaRtdisp.size:65516bits:31 2625 2120 1615 0bit pattern:44030$FFFE15..0This instruction causes the processor to perform a software initiated non-maskable interrupt routine. It has the same effect as an external hardware non-maskable interrupt. This is an alternate form of the HYPERLINK \l "JAL"JAL instruction.
Flags Affected
I1-------
NOP
Synopsis
No operation
Detail
desc:opsize:32bit pattern:0000_0009This instruction acts merely as a placeholder. It performs no operation and has no effect on the processor. Many processors lack an explicit NOP operation resulting in different instructions being used for this purpose within the same processor. By providing an explicit NOP instruction some consistency in programs can be achieved. Without a NOP instruction many processors typically use instructions which have side effects in the form of affecting the processor status flags; this is not the case here.
NOR Rt,Ra,Rb
Synopsis
Logically inclusively 'nor' register with register.
Detail
Rt = ~(Ra | Rb)
desc:opRaRt~opRbsize:655565bits:31 2625 2120 1615 1110 54 0bit pattern:2R4..0R4..0~18R4..0There is no immediate form for this instruction.
NOT Rt,Ra
Synopsis
Take ones complement of register.
Detail
Rt = ~Ra
desc:opRaRtimmsize:65516bits:31 2625 2120 1615 0bit pattern:8R4..0R4..0-115..0This is really an alternate form of the HYPERLINK "file:///O:\\IPCores\\raptor\\Documents\\raptor32.html" \l "XOR#XOR" XOR instruction.
OR Rt,Ra,Rb
OR Rt,Ra,#n
Synopsis
Logically inclusively 'or' register with register or immediate.
Detail
Rt = Ra | Rb
desc:opRaRt~opRbsize:655565bits:31 2625 2120 1615 1110 54 0bit pattern:2R4..0R4..0~10R4..0Rt = Ra | #imm
desc:opRaRtimmsize:65516bits:31 2625 2120 1615 0bit pattern:10R4..0R4..0n15..0
RESET
Synopsis
Run reset routine.
Detail
R30 = pc; pc = FFFF_FFFC; flags.backup = flags; flags.im = 1
desc:opRaRtdisp.size:65516bits:31 2625 2120 1615 0bit pattern:44030$FFFF15..0This instruction causes the processor to perform a software initiated reset routine. This is an alternate form of the HYPERLINK \l "JAL" JAL instruction.
Flags Affected
I1-------
RET
Synopsis
Return from subroutine.
Detail
pc = R31
desc:opRaRtdisp.size:65516bits:31 2625 2120 1615 0bit pattern:443100This instruction returns to the calling routine by loading the program counter with the contents of the return address. This is an alternate form of the jump-and-link ( HYPERLINK "file:///O:\\IPCores\\raptor\\Documents\\raptor32.html" \l "JAL#JAL" JAL) instruction.It is possible to return to a point in the program after the subroutine call by specifying a positive displacement instead of zero. This allows constant parameters to a subroutine call to be placed directly in code immediately after the calling instruction.
RI
Synopsis
Restore interrupt flag from backup copy.
Detail
flags.im = flags.backup im
desc:opsize:32bit pattern:0000_0004This instruction restores the previous interrupt flag state from the backup copy of the processor control register. This allows restoring the interrupt state that was present when the backup of the status register was made. This is useful in operating system code where interrupts must be disabled to perform certain system functions (like updating system lists) and then restored to a previous state after performing the operation.
Flags Affected
IX-------
ROL Rt,Ra,#cnt
ROL Rt,Ra,Rb
Synopsis
Rotate register left.
Detail
Rd = Rd !<< Rb
The most significant bit is shifted into the least significant bit.
desc:opRaRtXopRbsize:655565bits:31 2625 2120 1615 1110 54 0bit pattern:12R4..0R4..0~9R4..0Rt = Ra !<< #cnt
desc:opRaRtXopcntsize:655565bits:31 2625 2120 1615 1110 54 0bit pattern:12R4..0R4..0~1N4..0
ROR Rt,Ra,#cnt
ROR Rt,Ra,Rb
Synopsis
Rotate register right.
Detail
Rd = Rd !>> Rb
The most significant bit is shifted into the least significant bit.
desc:opRaRtXopRbsize:655565bits:31 2625 2120 1615 1110 54 0bit pattern:12R4..0R4..0~13R4..0Rt = Ra !>> #cnt
desc:opRaRtXopcntsize:655565bits:31 2625 2120 1615 1110 54 0bit pattern:12R4..0R4..0~5N4..0
RTX
Synopsis
Return from subroutine.
Detail
pc = R30
desc:opRaRtdisp.size:65516bits:31 2625 2120 1615 0bit pattern:443000This instruction returns from an exception processing routine by restoring the flag register and jumping back to the code that was interrupted (who's address is stored in R30). This is an alternate form of the jump-and-link ( HYPERLINK "file:///O:\\IPCores\\raptor\\Documents\\raptor32.html" \l "JAL#JAL" JAL) instruction.
SB Rs,d[Ra]
SBRs,[Ra + Rb]
Synopsis
Store byte from register to memory.
Detail
Memory8 [Ra + disp] = Rs
desc:opRaRsdispsize:65516bits:31 2625 2120 1615 0bit pattern:53R4..0R4..0d15..0Memory8 [Ra + Rb] = Rs
desc:OpRaRs~OpRbsize:655565bits:31 2625 2120 1615 1110 54 0bit pattern:2R4..0R4..0~53R4..0
SETHI
S-Type
Usage: setting register to constant value
41 3835 2525 2019 0154immediate12RegT6immediate20
The SETHI instruction sets the high order 32 bits of the target register to the immediate value specified in the opcode. The low order 32 bits of the register are unaffected. This instruction is typically used after the SETLO instruction in order to form a 64 bit constant.
SETLO
S-Type SETHI, SETLO
Usage: setting register to constant value
41 3835 2525 2019 0144immediate12RegT6immediate20
The SETLO instruction sets the target register to the immediate value specified in the opcode. The low order 32 bits of the register are set as specified in the opcode, the high order 32 bits of the register are set to the sign extension of the low order bits. SF Rt,d[Ra]
SF Rt,[Ra+Rb]
Synopsis
Store floating point register word to memory
Detail
memory32[Ra + disp] = fpack(Rs)
desc:opRaRsdisp.size:65516bits:31 2625 2120 1615 0bit pattern:28R4..0R4..0d15..0
memory32[Ra + Rb] = fpack(Rs)
desc:opRaRsRbXopsize:655556bits:31 2627 2423 2015 1110 65 0bit pattern:60R4..0R4..0R4..0~28Store packed floating point single value from register Rs to memory.
SGN Rt,Ra
Synopsis
Obtain sign of number.
Detail
Rt = Ra cond 0
This instruction performs a comparison of a register to zero and stores the result in the target register. If the value is less than zero, -1 is written to the target register. If the value is equal to zero, zero is written to the target register. If the value is greater than zero, +1 is written to the target register. This instruction is an alternate form of the HYPERLINK \l "CMP" CMP instruction, where the register is compared to the value zero..
SH Rt,d[Ra]
SH Rt,[Ra+Rb]
Synopsis
Store half-word from register to memory
Detail
Memory16 [Ra + disp] = Rs[15:0]
desc:opRaRsdispsize:65516bits:31 2625 2120 1615 0bit pattern:54R4..0R4..0d15..0Memory16 [Ra + Rb] = Rs[15:0]
desc:OpRaRs~OpRbsize:655565bits:31 2625 2120 1615 1110 54 0bit pattern:2R4..0R4..0~54R4..0Note the format of the displacement field. D0 is forced to zero because half-word accesses must be half-word aligned.
SHL Rt,Ra,#cnt
SHL Rt,Ra,Rb
Synopsis
(Logically) shift register left.
Detail
Rd = Rd << Rb
Zeroes are shifted into the least significant bits.
desc:opRaRtXopRbsize:655565bits:31 2625 2120 1615 1110 54 0bit pattern:12R4..0R4..0~8R4..0Rt = Ra << #cnt
desc:opRaRtXopcntsize:655565bits:31 2625 2120 1615 1110 54 0bit pattern:12R4..0R4..0~0N4..0
SHR Rt,Ra,#cnt
SHR Rt,Ra,Rb
Synopsis
(Logically) shift register right.
Detail
Rd = Rd >> Rb
A zero is shifted into the most significant bit.
desc:opRaRtXopRbsize:655565bits:31 2625 2120 1615 1110 54 0bit pattern:12R4..0R4..0~11R4..0Rt = Ra >> #cnt
desc:opRaRtXopcntsize:655565bits:31 2625 2120 1615 1110 54 0bit pattern:12R4..0R4..0~3N4..0
STOP
Synopsis
Stop the processor from executing instructions and wait for the external hardware 'go' signal or a non-maskable interrupt.
Detail
desc:opsize:32bits:31 0bit pattern:0000_0008This instruction can be used to synchronize the processor to an external event.
SUB Rt,Ra,Rb
SUB Rt,Ra,#n
Synopsis
'Subtract' register with register or immediate.
Detail
Rt = Ra - Rb
desc:opRaRt~opRbsize:655565bits:31 2625 2120 1615 1110 54 0bit pattern:2R4..0R4..0~5R4..0Rt = Ra - #imm
desc:opRaRtimmsize:65516bits:31 2625 2120 1615 0bit pattern:5R4..0R4..0n15..0 SWRs,d[Ra]
SWRs,[Ra + Rb]
Synopsis
Store word from register to memory
Detail
Memory32 [Ra + disp] = Rs
desc:opRaRsdispsize:65516bits:31 2625 2120 1615 0bit pattern:55R4..0R4..0d15..0Note the format of the displacement field. D1..0 is forced to zero because word accesses must be word aligned.
Memory32 [Ra + Rb] = Rs
desc:opRaRs~opRbsize:655565bits:31 2625 2120 1615 1110 54 0bit pattern:2R4..0R4..0~55R4..0
SYS
Synopsis
Perform system call.
Detail
R62 = pc; pc = +nnn; pcr.backup = pcr; pcr.im = 1
This instruction causes the processor to perform a system call. It is meant for operating system support. It is a specialized form of the HYPERLINK \l "JAL" JAL instruction.
Effects:
The processor control register is copied to its backup version. Then the interrupt mask is set, disabling further interrupts.
The program counter is stored in register 62.
The program counter is loaded with the sum of the exception table address register and the call number shifted left twice.
I - Type
Register-Immediate Datapath,
Jump and Link
31 2524 1918 1312 10 9 027Ra6620Call No10 TRSRa,Spr
Synopsis
Transfer register to special purpose register.
Detail
Special Register = Ra
Special Registers
Currently there are only five special registers defined, the remaining codes are reserved for future use.
CodeRegister NameDescription0PCRProcessor Control Register1{this register is reserved}2{this register is reserved}3VERProcessor Version - major, minor, revision4RNDrandom number register
TSRRt,Spr
Synopsis
Transfer special purpose register to register.
Detail
Rt = Special Register
Special Registers
Currently there are only five special registers defined, the remaining codes are reserved for future use.
CodeRegister NameDescription0PCRProcessor Control Register1{this register is reserved}2{this register is reserved}3VERProcessor Version - major, minor, revision4RNDrandom number register5TCTick Count
WAI
Synopsis
Wait for interrupt.
Detail
If the processor is in the interrupt context, this instruction will cause the processor to exit the interrupt context; otherwise this instruction will be treated as a nop. When an interrupt occurs, the processor will begin execution immediately after the wai instruction, if the wai instruction was used to exit the interrupt context.
Normally this instruction would be used in an interrupt service routine at the point at which it is desired to begin interrupt processing.
XNOR Rt,Ra,Rb
Synopsis
Logically exclusively 'nor' register with register.
Detail
Rt = ~(Ra ^ Rb)
There is no immediate form for this instruction.
XOR Rt,Ra,Rb
XOR Rt,Ra,#n
Synopsis
Logically exclusively 'or' register with register or immediate.
Detail
Rt = Ra ^ Rb
Rt = Ra ^ #imm
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< a bp2 H H H H H H H H H H H H H H H H H H H H H H H H H I Ff& Ff7
$$If a$ $If [$ \$ I I I I I I %I +I -I 0I 1I vI I I I I I I K K K K K K [$ \$ gdN [$ \$ gdN Ff $If Ff $$If a$ wI zI I I I I I I I I &K 'K K AK BK K K K K K K K K K K K K ſŌ|rh^Xh^XTJT hr CJ ^J aJ hr
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hr ^J FI I I I I I J J J J J J J J 2J 8J ;J >J AJ CJ FJ JJ KJ QJ SJ UJ WJ FfrE FfA $If Ff= $$If a$ 0J 2J 7J 8J :J ;J =J >J @J AJ BJ CJ EJ FJ IJ JJ KJ PJ QJ RJ SJ TJ UJ VJ WJ XJ YJ ZJ [J \J ]J ^J cJ dJ mJ nJ vJ wJ J J J J J J J J J J J J J J J J J J J J J J J J J J J ƾƾƾ hr CJ aJ mH sH hr CJ H*^J aJ mH sH hr CJ aJ hr hr CJ ^J aJ hr mH sH hr CJ ^J aJ mH sH hr CJ ^J aJ mH sH hr mH sH @WJ YJ [J ]J ^J dJ nJ wJ J J J J J J J J J J J J J J J J J J J FfP FfM $If FfEI $$If a$ J J J J J J J J J J J K K K K K K K
|
hr ^J hr ^J mH sH hr CJ ^J aJ hN CJ ^J aJ hN hN 0J >* CJ ^J aJ 'jh hN hF CJ U^J aJ !j hN hN CJ U^J aJ hN CJ ^J aJ hN
|
K K K K K K K K K K K K K K !K &K 'K .K /K 7K 8K @K AK OK PK QK ]K ^K `K aK cK dK eK fK gK hK iK L L JL KL L ҾҶҶҶҨҶ֚֨ j hr CJ U^J aJ hr CJ ^J aJ mH sH hr CJ aJ hr CJ ^J aJ mH sH
|
hN ^J hN hN CJ ^J aJ h
hN mH sH h
hN ^J mH sH hN ^J mH sH hN CJ ^J mH sH K K K K K K K K K L L L L L
|
hr ^J hr hr CJ ^J aJ hr ^J mH sH hr CJ ^J aJ mH sH hr mH sH ;J K K K
|
L L L L L L L L L L L L L L !L )L *L 1L 2L 9L :L >L ML OL PL QL ]L ^L `L aL bL fL gL hL lL mL nL sL tL uL L L L L L L L L L L L L L L L L L L hr CJ H*^J aJ hr CJ ^J aJ mH sH hr CJ aJ hr mH sH hr CJ ^J aJ mH sH hr CJ ^J aJ hr
|
K K K K K K K K !K 'K /K 8K AK PK QK ^K aK dK fK hK iK L Ff%^ FfZ FfW FfT $$If a$ $If L L L L L L L L L L L L L L L L M M M M M !M #M $M &M 'M )M *M .M /M 0M 5M 6M 7M 8M 9M :M ;M M ?M @M EM FM NM OM VM WM ^M ·{{ hr CJ aJ hr mH sH hr CJ ^J aJ mH sH
|
hr ^J GK K K K L L
|
hr ^J hr ^J mH sH hr CJ ^J aJ mH sH h
hr mH sH hr hr CJ ^J aJ hr 0J >* CJ ^J aJ j hr CJ U^J aJ 'j` h hIk CJ U^J aJ 0L L L L L L M M !M $M 'M *M /M $$If a$ $If [$ \$ /M 0M kd` $$If < r B
|
L $$If a$ $If
|
8
|
L L kd $$If < r B
|
2 0 $6 4 4
|
8
|
< a bp2 0M 6M 8M :M
|
2 0 $6 4 4
|
8
|
< a bp2 L L L L L L $$If a$ $If L L kd $$If < r B
|
2 0 $6 4 4
|
8
|
< a bp2 @M FM OM WM _M uM $$If a$ $If ^M _M cM rM tM uM vM M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M N N N N N N N #N $N %N &N 'N ûûûû hr mH sH hr CJ ^J aJ mH sH hr CJ H*^J aJ hr CJ aJ hr CJ ^J aJ mH sH hr CJ ^J aJ hr HuM vM kdXc $$If < r B
|
2 0 $6 4 4
|
8
|
< a bp2 L !L *L 2L :L PL $$If a$ $If PL QL kdW $$If < r B
|
2 0 $6 4 4
|
8
|
< a bp2 vM M M M M M $$If a$ $If M M kdd $$If < r B
|
2 0 $6 4 4
|
8
|
< a bp2 QL ^L aL gL mL tL $$If a$ $If tL uL kd $$If < r B
|
2 0 $6 4 4
|
8
|
< a bp2 M M M M M M M M M M M M M M M M M M M M M M N N N N $N Ffo Ff*k FfMg $$If a$ $If $N &N ,N 2N 4N 7N =N >N ?N FN GN NN xN N N N N $$If a$gd9 gd5b Ffr $$If a$ 'N +N ,N -N 1N 2N 3N 4N 6N 7N 8N N @N CN EN FN GN xN N N N N N N O O O O O O O O )P 迳ririZ h
h5b CJ aJ mH sH h5b CJ H*aJ h5b CJ H*aJ mH sH h CJ aJ mH sH h5b CJ aJ mH sH h5b CJ aJ mH sH h5b CJ aJ h5b mH sH h5b CJ aJ mH sH h5b h5b CJ aJ mH sH hr CJ aJ mH sH hr CJ ^J aJ mH sH hr mH sH hr CJ H*^J aJ mH sH "N N N O O O [ O O O O $$If a$gd9 kdRu $$If l \ 4 t" 4 t
|
2 0 $6 4 4
|
t 0 t"6 4 4
|
< a bp2 uL L L L L L L L L L L L L L L L L L L L L L L L L L M Ff* Ff)& FfL" $$If a$ $If L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L M M M M M
M M M M M M M M M M M M M LM MM M M M M M M M h
hr ^J mH sH h
hr CJ ^J aJ mH sH h
hr mH sH hr CJ H*^J aJ mH sH hr CJ ^J aJ mH sH hr CJ H*^J aJ hr CJ aJ hr CJ ^J aJ hr 8M M M M M M M M M M M M M M M M (N .N 1N 4N 7N 9N N ?N @N EN FN GN HN IN JN KN LN MN NN ON PN QN RN SN XN YN bN cN kN lN tN uN }N ~N N N N N N N N N N N N N ºººڲڲڲº£ hr CJ H*^J aJ mH sH hr CJ aJ hr mH sH hr CJ ^J aJ mH sH hr CJ ^J aJ hr
|
l al yt5b O O O O (P )P 0P 1P [ R I I I D D gd5b [$ \$ ^gd5b kd v $$If l \ 4 t" 4 t
|
hr ^J h
hr ^J mH sH h
hr CJ ^J mH sH @FN HN JN LN NN PN RN SN YN cN lN uN ~N N N N N N N N N N N N N N N Ff9= Fff9 $If Ff5 $$If a$ N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N O O
O O O O O O )O *O 1O 2O 3O ?O @O BO CO DO hr CJ aJ hr hr CJ ^J aJ hr mH sH hr CJ ^J aJ mH sH hr CJ aJ mH sH hr mH sH hr CJ H*^J aJ mH sH hr CJ ^J aJ mH sH ?N N N N N N N N N N N N N N N N O O O O *O 2O 3O @O CO IO OO FfH FfD $If Ff A $$If a$ DO HO IO JO NO OO PO QO RO SO TO XO YO ZO ]O `O lO oO O O O O O O O O O O O O O O O O O O O O O O P P P P P P
|
t 0 t"6 4 4
|
P P P
P P P P P P ʨʺʨʨʚʨʨʨʊʨʨʨʨʨ hr CJ aJ hr mH sH hr CJ ^J aJ mH sH hr CJ ^J aJ hr CJ ^J
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l al yt5b )P 0P 1P pP P P P P P P P P P P Q
|
hr ^J hr CJ ^J aJ hr hr CJ aJ mH sH hr CJ ^J aJ mH sH hr mH sH hr CJ H*^J aJ mH sH 6OO QO SO YO ZO \O lO yO O O O O O O O O O O O P P P
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Q
Q Q R R R R "R -R 5R 6R bR cR iR jR R R ƺޤƭޤޜ|o|oie[eie[e hr CJ ^J aJ hr
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P P P P FfXP $If [$ \$ FfL $$If a$ P P P P P %P .P 7P @P JP RP SP `P cP iP oP qP tP zP {P P P P P P P P Ff[ FfW $If Ff+T $$If a$ P P P P P P $P %P -P .P 6P 7P ?P @P IP JP QP RP SP _P `P bP cP dP hP iP jP nP oP pP qP sP tP uP yP zP {P P P P P P P P P P P P P P P P P P P P P P P P P P P P P Թԫ hr mH sH hr CJ ^J aJ mH sH hr CJ aJ mH sH hr CJ H*^J aJ mH sH hr mH sH hr CJ ^J aJ mH sH hr CJ aJ hr hr CJ ^J aJ @P P P P P P P P P P P P P P P P P P P Q Q Q Q Q Q Q FfJg Ffwc $If Ff_ $$If a$ P P P P P P P P P P P P P P P P P P P P Q Q Q Q Q Q Q
Q Q Q Q Q Q Q Q Q Q Q Q !Q $Q %Q -Q .Q HQ IQ nQ Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Թԯ
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hr ^J h
hr ^J mH sH h
hr CJ ^J aJ mH sH h
h5b CJ aJ mH sH h5b mH sH h5b CJ H*aJ h5b CJ H*aJ mH sH hpO CJ aJ mH sH h5b CJ aJ mH sH h5b CJ aJ mH sH h5b CJ aJ h
h5b mH sH h
h5b CJ aJ mH sH 1P FP pP P P P P P P J kdv $$If l \ 4 t" 4 t
|
hr ^J hr CJ ^J aJ mH sH hr CJ ^J aJ hr CJ aJ mH sH hr CJ H*^J aJ mH sH hr mH sH hr CJ ^J aJ mH sH hr CJ aJ hr CJ ^J aJ hr = Q Q Q %Q .Q Q Q Q Q Q T kdm $$If < 0 0 6 4 4
|
t 0 t"6 4 4
|
< a bp $$If a$ $If Ff k Q Q Q Q Q Q ] kdXn $$If < 0 0 6 4 4
|
l al yt9 $$If a$gd9 gd5b P P P Q Q
Q Q O F : [$ \$ gd5b ^gd5b kdiw $$If l \ 4 t" 4 t
|
< a bp $$If a$ $If Q Q Q Q Q Q Q Q Q Q Q Q ?R BR CR FR PR SR eR fR R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R S S S S !S "S #S $S %S ƾ hr CJ ^J aJ mH sH
|
t 0 t"6 4 4
|
hr ^J hr mH sH hr ^J mH sH hr CJ \^J aJ mH sH h
hr mH sH hr hr CJ ^J aJ hr CJ aJ AQ Q Q Q l f ] $$If a$ $If kd/o $$If < 0 0 6 4 4
|
l al yt9 $$If a$gd9 Q R -R 6R cR jR R R R R R R $$If a$ $If [$ \$ [$ \$ gd5b R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R S S S S S S
S S ,S /S 4S 5S 7S 8S :S ;S =S >S @S AS BS CS ES FS GS LS MS NS OS PS QS RS SS TS US VS WS XS YS hr CJ H*^J aJ hr CJ aJ hr hr CJ ^J aJ hr mH sH hr CJ ^J aJ mH sH OR R kdx $$If < r Ln B
|
< a bp Q Q @R BR PR ]R fR R R R R l j j h _ j j j j Y $If [$ \$ kdp $$If < 0 0 6 4 4
|
2 0 46 4 4
|
< a bp
|
< a bp2 R R R R R R $$If a$ $If R R kdUy $$If < r Ln B
|
R R R R R R R R R R R R R R R R R R R R S S S S "S $S *S FfZz Ffav $If Ffhr $$If a$ %S )S *S +S /S 0S 2S 5S 9S :S ;S IS JS OS PS RS SS US VS XS YS \S ]S ^S cS dS eS fS gS hS iS jS lS mS nS sS tS |S }S S S S S S S S S S S S S S S S S S S S S S S S S S hr CJ ^J aJ mH sH
|
2 0 46 4 4
|
hr ^J hr CJ ^J aJ hr mH sH hr CJ ^J aJ mH sH hr CJ aJ hr CJ ^J aJ hr hr CJ H*^J aJ ?*S 0S 2S 4S :S ;S JS PS SS VS YS ]S ^S dS fS hS jS mS nS tS }S S S S S S Fff Ff5 Ff $If FfS~ $$If a$ S S S S S S S S S T #T =T CT FT IT LT QT $If [$ \$ Ff $$If a$ S S S T T "T #T
|
< a bp2 R R R R R R $$If a$ $If R R kdz $$If < r Ln B
|
hr ^J hr hr CJ ^J aJ hr mH sH hr ^J mH sH =QT RT kd $$If < r B
|
2 0 46 4 4
|
8
|
< a bp2 R R R R S S $$If a$ $If S
S kd{ $$If < r Ln B
|
2 0 $6 4 4
|
2 0 46 4 4
|
< a bp2 RT XT ZT \T ^T aT $$If a$ $If aT bT kdȎ $$If < r B
|
< a bp2
S S -S /S 5S 8S ;S >S AS CS FS GS MS OS QS SS US WS YS ZS `S jS sS |S S S Ff Ff~ $$If a$ $If [$ \$ YS ZS _S `S iS jS rS sS {S |S S S S S S S S S S S S S S S S S S S S S S S S S S T T T
T T T .T 4T 5T CT DT U U U ɼ !j hN hN CJ U^J aJ hN CJ ^J aJ hN
|
8
|
hN ^J hN hN CJ ^J aJ h
hN mH sH h
hN ^J mH sH hN ^J mH sH hN CJ ^J mH sH hr CJ H*^J aJ hr hr CJ ^J aJ hr CJ aJ 0S S S S S S S S S S S T
T T T .T 5T DT V V *V 3V [V bV [$ \$ gdN [$ \$ gdN Ffv $If Ff $$If a$ U U U U U V V V V V V V V 2V 3V ZV [V aV bV V V V V V V V V V V V V V V V V V V V V V V V V |t|t|tll hr CJ aJ hr mH sH hr CJ ^J aJ mH sH hr CJ ^J aJ hr
|
2 0 $6 4 4
|
hr ^J hr ^J mH sH hr CJ ^J aJ hN CJ ^J aJ hN hN CJ ^J aJ hN hN 0J >* CJ ^J aJ !j hN hN CJ U^J aJ 'jڌ hN hF CJ U^J aJ *bV V V V V V V $$If a$ $If V V kdC $$If < r B
|
< a bp2 bT hT qT yT T T $$If a$ $If T T kd $$If < r B
|
8
|
8
|
2 0 $6 4 4
|
2 0 $6 4 4
|
< a bp2 V V V V V V $$If a$ $If V V kd $$If < r B
|
< a bp2 T T T T T T $$If a$ $If T T kdN $$If < r B
|
8
|
8
|
2 0 $6 4 4
|
2 0 $6 4 4
|
< a bp2 V V V V V V V V V V V V V V V V V V V V V V V V V V W W W W $W %W 'W (W *W +W -W .W /W 0W 2W 3W 5W 6W 7W W ?W @W AW BW CW DW EW FW GW HW IW JW OW PW YW ZW bW cW kW lW tW uW |W }W W W W ûûûhr mH sH hr CJ ^J aJ mH sH hr CJ H*^J aJ hr CJ aJ hr CJ ^J aJ mH sH hr hr CJ ^J aJ JV V V V V V $$If a$ $If V V kdɏ $$If < r B
|
< a bp2 U !U *U +U BU CU HU IU KU LU NU OU QU RU SU TU VU WU YU ZU [U `U aU bU cU dU eU fU gU hU iU jU kU lU mU nU sU tU }U ~U U U U U U U U U U U U U U U U U U U U U U U U U U U U U ַַַ hr CJ H*^J aJ mH sH hr CJ aJ hr mH sH hr CJ ^J aJ mH sH hr hr CJ ^J aJ mH sH hr CJ ^J aJ CT +U CU IU LU OU RU TU WU ZU [U aU cU eU gU iU kU mU nU tU ~U U U U U U U Ff Ffݗ Ff $$If a$ $If U U U U U U U U U U U U U U 2V V V nW W X X =X KX XX $$If a$gdr [$ \$ ^gdW gd$s Ff $$If a$ $If U U U U U U U U U U U U U
|
8
|
V V 1V 2V V V V V V V V V V V X X WX ;ziz\zX hW h$s 0J >* CJ ^J aJ !j h$s CJ U^J aJ j h$s CJ U^J aJ hW CJ ^J aJ hq CJ ^J aJ h$s CJ ^J aJ mH sH h$s CJ ^J aJ h$s
|
2 0 $6 4 4
|
h$s ^J hW h$s CJ aJ mH sH hW CJ ^J aJ mH sH hW h$s CJ ^J aJ mH sH hr mH sH hr CJ aJ mH sH WX XX X X X X X X X X X X X X X Y Y Y Y Y $Y %Y 6Y 7Y Y Y Y Y Y Y Y Y õñyobbbZ hr CJ aJ hr 5CJ \^J aJ hN CJ ^J aJ
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< a bp2 V V V V V W $$If a$ $If W W kd $$If < r B
|
hr ^J hr hr CJ ^J aJ hr mH sH hr ^J mH sH hr CJ ^J aJ mH sH h$s hW hW hW CJ H*^J aJ hW CJ ^J aJ hW CJ H*^J aJ mH sH hW mH sH hW CJ ^J aJ mH sH hW CJ ^J aJ mH sH XX dX nX X X X X X ? kdn $$If l r <(` dl 8 8
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8
|
t 0 06 4 4
|
2 0 $6 4 4
|
l a $$If a$gdr X X X X X X X ? = ; kd $$If l r <(` dl 8 8
|
< a bp2 W W %W (W +W .W 0W 3W 6W 7W =W ?W AW CW EW GW IW JW PW ZW cW lW uW }W W W W Ffx Ff Ff $$If a$ $If W W W W W W W W W W W W W W W W W W W W W X X !X #X $X 'X 3X 6X @X HX IX iX jX pX qX ~X X X X X X X X vnvn hr mH sH hr CJ ^J aJ mH sH
|
t 0 06 4 4
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hr ^J h
hr CJ ^J mH sH h
hr ^J mH sH h
hr CJ ^J aJ mH sH h
hr mH sH hr CJ H*^J aJ mH sH hr CJ ^J aJ mH sH hr CJ aJ hr CJ H*^J aJ hr hr CJ ^J aJ +W W W W W W W W "X #X 3X @X IX jX qX X X X X X X X X X X X Ff2 $If [$ \$ FfU $$If a$ X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Y Y Y
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l a $$If a$gdr X Y Y %Y 7Y Y Y Y Y $If $$If a$ Y Y Y Y Y G > 8 8 $If $$If a$ kd£ $$If < F L 0
6 4 4
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Y Y Y Y Y Y )Y *Y ,Y -Y .Y 2Y 3Y 4Y 8Y 9Y :Y ;Y Y BY CY DY SY UY ZY [Y ]Y ^Y `Y aY hr CJ aJ mH sH hr CJ H*^J aJ mH sH hr CJ aJ hr hr CJ ^J aJ hr mH sH hr CJ ^J aJ mH sH CX X X X X X X X X X X Y
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< a b p Y Y Y Y Y Y Y Y Y Y Z Z Z Z Z "Z #Z $Z %Z &Z )Z *Z TZ UZ VZ WZ XZ [Z \Z rZ sZ tZ wZ xZ {Z ~Z Z Z Z Z Z Z Z Z Z Z W[ X[ \[ ][ j[ k[ v[ w[ x[ y[ z[ }[ ~[ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ hr 5CJ \^J aJ
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Z Z ܯ hr CJ ^J
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hr ^J hr CJ ^J aJ hr CJ ^J aJ hr CJ aJ hr hr CJ ^J aJ mH sH KY Y Y Y Z m d ^ ^ $If $$If a$ kd $$If < F L 0
6 4 4
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hr ^J hr CJ ^J aJ hr CJ aJ mH sH hr CJ H*^J aJ mH sH hr CJ aJ hr hr CJ ^J aJ hr mH sH hr CJ ^J aJ mH sH ?Y Y Y Y Y Y Y Z Z 0Z 7Z EZ vZ |Z Z Z Z Z Z Z Z Z Z Z Z Z Ff $If [$ \$ Ff $$If a$ Z /Z 0Z 6Z 7Z DZ EZ uZ vZ {Z |Z ~Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z [ [ [ [ hr CJ H*^J aJ mH sH hr CJ aJ hr mH sH hr CJ ^J aJ mH sH
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< a b Z Z Z Z #Z m d ^ ^ $If $$If a$ kdm $$If < F L 0
6 4 4
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hr ^J hr hr CJ ^J aJ FZ Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z [ [ [ [ [ ![ $[ '[ )[ ,[ FfC Ffp $If Ff $$If a$ [ [ [ [ [ [ [ ![ #[ $[ &[ '[ ([ )[ +[ ,[ /[ 0[ 1[ 6[ 7[ 8[ 9[ :[ ;[ <[ =[ >[ ?[ @[ A[ B[ C[ D[ I[ J[ S[ T[ \[ ][ e[ f[ n[ o[ x[ y[ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ ȾУУУ hr CJ H*^J aJ mH sH hr CJ aJ hr hr CJ ^J aJ hr mH sH hr CJ ^J aJ mH sH hr mH sH hr CJ ^J aJ mH sH hr CJ aJ mH sH @,[ 0[ 1[ 7[ 9[ ;[ =[ ?[ A[ C[ D[ J[ T[ ][ f[ o[ y[ [ [ [ [ [ [ [ [ [ Ff Ff $If Ff $$If a$ [ [ [ [ [ [ [ [ [ [ [ [ \ 3\ 4\ 5\ ;\ <\ A\ B\ D\ E\ F\ K\ L\ N\ O\ P\ U\ V\ b\ c\ d\ p\ q\ z\ {\ |\ \ \ \ \ \ \ \ \ !] "] (] )] ʼʲʲʪʲʪʲʪʲʪʟ~ hr mH sH hr ^J mH sH hr CJ \^J aJ mH sH h
hr mH sH hr CJ aJ hr CJ ^J aJ hr CJ ^J aJ mH sH hr
|
< a b #Z $Z &Z *Z UZ m d ^ ^ $If $$If a$ kd $$If < F L 0
6 4 4
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hr ^J hr CJ ^J aJ mH sH hr CJ ^J aJ hr CJ aJ mH sH hr mH sH 1[ [ [ [ [ 5\ <\ B\ E\ F\ T kd $$If < 0 0 6 4 4
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< a b UZ VZ XZ \Z sZ m d ^ ^ $If $$If a$ kdͦ $$If < F L 0
6 4 4
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< a bp $$If a$ $If Ff F\ L\ O\ P\ V\ c\ ] kd $$If < 0 0 6 4 4
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< a b sZ tZ uZ vZ wZ m d ^ ^ $If $$If a$ kd} $$If < F L 0
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yt P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f yt?9 kd $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
l al p2 ֛ ytyX :$$If l !v h#v #v#vS#v9#v#v :V l
|
l al p< ̙ ̙ f f yt?9 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f yt?9 kd $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
2 ֛ 0 % 5 55S5955 4 al p2 ֛ ytPU kd $$If l ֞ T +d% S 9
|
l al p< ̙ ̙ f f yt?9 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f yt?9 kda $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
2 ֛ 0 % 4
|
l al p< ̙ ̙ f f yt?9 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f yt?9 kd $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
l al p2 ֛ ytPU $$If l !v h#v #v#v#vn#v9#v#v :V l
|
l al p< ̙ ̙ f f yt?9 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f yt?9 kd $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
0 % 5 555n5955 / 4 al p
|
l al p< ̙ ̙ f f yt?9 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f yt?9 kd~ $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
yt^0 kd $$If l ִ T +d% n 9
|
l al p< ̙ ̙ f f yt?9 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f yt?9 kd $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
0 % 4
|
l al p< ̙ ̙ f f yt?9 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f yt?9 kd< $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
l al p
|
l al p< ̙ ̙ f f yt?9 B$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 554 al p< ̙ ̙ f f yt?9 kd $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
yt^0 @$$If l !v h#v #v#v#vn#v9#v#v :V l ( 0 % 5 555n5955 / 4 al p( ytPU +kd $$If l ִ T +d% n 9 ( 0 % 4
|
l al p< ̙ ̙ f f yt?9 B$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 554 al p< ̙ ̙ f f yt?9 kd $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
l al p( ytPU @$$If l !v h#v #v#v#vn#v9#v#v :V l ( 0 % 5 555n5955 / 4 al p( ytPU +kd< $$If l ִ T +d% n 9 ( 0 % 4
|
l al p< ̙ ̙ f f yt?9 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f yt?9 kd= $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
l al p( ytPU @$$If l !v h#v #v#v#vn#v9#v#v :V l ( 0 % 5 555n5955 / 4 al p( ytPU +kd $$If l ִ T +d% n 9 ( 0 % 4
|
l al p< ̙ ̙ f f yt?9 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f yt?9 kd $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
l al p( ytPU @$$If l !v h#v #v#v#vn#v9#v#v :V l ( 0 % 5 555n5955 / 4 al p( ytPU +kd
$$If l ִ T +d% n 9 ( 0 % 4
|
l al p< ̙ ̙ f f yt?9 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f yt?9 kd $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
l al p( ytPU @$$If l !v h#v #v#v#vn#v9#v#v :V l ( 0 % 5 555n5955 / 4 al p( ytPU +kd $$If l ִ T +d% n 9 ( 0 % 4
|
l al p< ̙ ̙ f f yt?9 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f yt?9 kdZ $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
l al p( ytPU @$$If l !v h#v #v#v#vn#v9#v#v :V l ( 0 % 5 555n5955 / 4 al p( ytPU +kd $$If l ִ T +d% n 9 ( 0 % 4
|
l al p< ̙ ̙ f f yt?9 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f yt?9 kd $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
l al p( ytPU @$$If l !v h#v #v#v#vn#v9#v#v :V l ( 0 % 5 555n5955 / 4 al p( ytPU +kdg $$If l ִ T +d% n 9 ( 0 % 4
|
l al p< ̙ ̙ f f yt?9 l$$If l !v h#v #v#v@ #v#v:V l d d d d d< 0 % 5 55@ 55/ / / 4 al p< yt^0 kd $$If l ֈ T$ d% @ d d d d d< 0 % 4
|
l al p( ytPU @$$If l !v h#v #v#v#vn#v9#v#v :V l ( 0 % 5 555n5955 / 4 al p( ytPU +kd $$If l ִ T +d% n 9 ( 0 % 4
|
l al p< yt^0 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f yt?9 kd $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
l al p( ytPU @$$If l !v h#v #v#v#vn#v9#v#v :V l ( 0 % 5 555n5955 / 4 al p( ytPU +kdE $$If l ִ T +d% n 9 ( 0 % 4
|
l al p< ̙ ̙ f f yt?9 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f yt?9 kd $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
l al p( ytPU @$$If l !v h#v #v#v#vn#v9#v#v :V l ( 0 % 5 555n5955 / 4 al p( ytPU +kd! $$If l ִ T +d% n 9 ( 0 % 4
|
l al p< ̙ ̙ f f yt?9 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f yt?9 kdQ $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
l al p( ytPU @$$If l !v h#v #v#v#vn#v9#v#v :V l ( 0 % 5 555n5955 / 4 al p( ytPU +kd#% $$If l ִ T +d% n 9 ( 0 % 4
|
l al p< ̙ ̙ f f yt?9 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f yt?9 kd $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
l al p( ytPU l$$If l !v h#v #v#v#vn#v9#v#v :V l < 0 % 5 555n5955 / 4 al p< yt{ Wkd( $$If l ִ T +d% n 9 < 0 % 4
|
l al p< ̙ ̙ f f yt?9 ^$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ / 4 al p< ̙ ̙ f f yt`i kd $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
l al p< yt{ l$$If l !v h#v #v#v#vn#v9#v#v :V l < 0 % 5 555n5955 / 4 al p< yt^0 WkdY, $$If l ִ T +d% n 9 < 0 % 4
|
l al p< ̙ ̙ f f yt`i $$If l !v h#v #v#v #vn#v#v#v:V l P 0 % 5 55 5n555/ 4 al pP yt` kd| $$If l ִ T$ / d% n P 0 % 4
|
l al p< yt^0 l$$If l !v h#v #v#v#vn#v9#v#v :V l < 0 % 5 555n5955 / 4 al p< yt^0 Wkd 0 $$If l ִ T +d% n 9 < 0 % 4
|
l al pP yt` B$$If l !v h#v #v#v@ #v#v:V l d d d d d< 0 % 5 55@ 554 al p< yt` kd $$If l ֈ T$ d% @ d d d d d< 0 % 4
|
l al p< yt^0 l$$If l !v h#v #v#v#vn#v9#v#v :V l < 0 % 5 555n5955 / 4 al p< yt{ Wkd3 $$If l ִ T +d% n 9 < 0 % 4
|
l al p< yt` P$$If l !v h#v #v#v@ #v#v:V l d d d d d< 0 % 5 55@ 55/ 4 al p< yt` kd $$If l ֈ T$ d% @ d d d d d< 0 % 4
|
l al p< yt{ l$$If l !v h#v #v#v#vn#v9#v#v :V l < 0 % 5 555n5955 / 4 al p< yt^0 Wkd7 $$If l ִ T +d% n 9 < 0 % 4
|
l al p< yt` P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f ytU
kdK $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
l al p< yt^0 l$$If l !v h#v #v#v#vn#v9#v#v :V l < 0 % 5 555n5955 / 4 al p< yt^0 Wkdu; $$If l ִ T +d% n 9 < 0 % 4
|
l al p< ̙ ̙ f f ytU
P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f ytU
kd $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
l al p< yt^0 l$$If l !v h#v #v#v#vn#v9#v#v :V l < 0 % 5 555n5955 / 4 al p< yt^0 Wkd
|
l al p< ̙ ̙ f f ytU
P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f ytU
kd $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
l al p< yt^0 l$$If l !v h#v #v#v#vn#v9#v#v :V l < 0 % 5 555n5955 / 4 al p< yt^0 WkdC $$If l ִ T +d% n 9 < 0 % 4
|
l al p< ̙ ̙ f f ytU
P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f ytU
kdh $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
l al p< yt^0 l$$If l !v h#v #v#v#vn#v9#v#v :V l < 0 % 5 555n5955 / 4 al p< yt^0 WkdF $$If l ִ T +d% n 9 < 0 % 4
|
l al p< ̙ ̙ f f ytU
P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f ytU
kd $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
l al p< yt^0 l$$If l !v h#v #v#v#vn#v9#v#v :V l < 0 % 5 555n5955 / 4 al p< yt^0 WkdJ $$If l ִ T +d% n 9 < 0 % 4
|
l al p< ̙ ̙ f f ytU
P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f ytU
kd& $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
l al p< yt^0 $$If l !v h#v %:V l
|
l al p< ̙ ̙ f f ytU
P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f ytU
kd $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
0 % 5 %/ 4 al p
|
l al p< ̙ ̙ f f ytU
P$$If l !v h#v #v#v@ #v#v:V l d d d d d< 0 % 5 55@ 55/ 4 al p< yt^0 kd $$If l ֈ T$ d% @ d d d d d< 0 % 4
|
yte P$$If l !v h#v #v#v
|
l al p< yt^0 $$If l !v h#v %:V l 4
|
#vn#v :V l @ @ < 0 % 5 55
|
0 % 5 %/ 4 al f4p
|
5n5 / 4 al p< ytPU kdO $$If l ֈ T }%
|
yt$ P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ 0 % 5 55@ 55/ 4 al p< ̙ ̙ yt 7 kd $$If l ֈ T$ d% @ < ̙ ̙ 0 % 4
|
n @ @ < 0 % 4
|
l al p< ̙ ̙ yt 7 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ 0 % 5 55@ 55/ 4 al p< ̙ ̙ yt 7 kdT $$If l ֈ T$ d% @ < ̙ ̙ 0 % 4
|
l al p< ytPU ^$$If l !v h#v #v#v
|
l al p< ̙ ̙ yt 7 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ 0 % 5 55@ 55/ 4 al p< ̙ ̙ yt 7 kd $$If l ֈ T$ d% @ < ̙ ̙ 0 % 4
|
#vn#v :V l @ @ < 0 % 5 55
|
l al p< ̙ ̙ yt 7 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ 0 % 5 55@ 55/ 4 al p< ̙ ̙ yt 7 kd$ $$If l ֈ T$ d% @ < ̙ ̙ 0 % 4
|
5n5 / / 4 al p< ytPU kdcR $$If l ֈ T }%
|
l al p< ̙ ̙ yt 7 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ 0 % 5 55@ 55/ 4 al p< ̙ ̙ yt 7 kdq' $$If l ֈ T$ d% @ < ̙ ̙ 0 % 4
|
n @ @ < 0 % 4
|
l al p< ̙ ̙ yt 7 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ 0 % 5 55@ 55/ 4 al p< ̙ ̙ yt 7 kd* $$If l ֈ T$ d% @ < ̙ ̙ 0 % 4
|
l al p< ytPU P$$If l !v h#v #v#v
|
l al p< ̙ ̙ yt 7 ^$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ 0 % 5 55@ 55/ / 4 al p< ̙ ̙ yt 7 kd/. $$If l ֈ T$ d% @ < ̙ ̙ 0 % 4
|
#vn#v :V l @ @ < 0 % 5 55
|
l al p< ̙ ̙ yt 7 ^$$If l !v h#v #v#v@ #v#v:V l d d d d d< 0 % 5 55@ 55/ / 4 al p< yt 7 kd1 $$If l ֈ T$ d% @ d d d d d< 0 % 4
|
5n5 / 4 al p< ytPU kdU $$If l ֈ T }%
|
l al p< yt 7 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ 0 % 5 55@ 55/ 4 al p< ̙ ̙ yt 7 kd 5 $$If l ֈ T$ d% @ < ̙ ̙ 0 % 4
|
n @ @ < 0 % 4
|
l al p< ̙ ̙ yt 7 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ 0 % 5 55@ 55/ 4 al p< ̙ ̙ yt 7 kdh8 $$If l ֈ T$ d% @ < ̙ ̙ 0 % 4
|
l al p< ytPU P$$If l !v h#v #v#v
|
l al p< ̙ ̙ yt 7 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ 0 % 5 55@ 55/ 4 al p< ̙ ̙ yt 7 kd; $$If l ֈ T$ d% @ < ̙ ̙ 0 % 4
|
#vn#v :V l @ @ < 0 % 5 55
|
l al p< ̙ ̙ yt 7 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ 0 % 5 55@ 55/ 4 al p< ̙ ̙ yt 7 kd&? $$If l ֈ T$ d% @ < ̙ ̙ 0 % 4
|
5n5 / 4 al p< ytPU kd/Y $$If l ֈ T }%
|
l al p< ̙ ̙ yt 7 P$$If l !v h#v #v#v@ #v#v:V l d d d d d< 0 % 5 55@ 55/ 4 al p< yt kdB $$If l ֈ T$ d% @ d d d d d< 0 % 4
|
n @ @ < 0 % 4
|
l al p< yt P$$If l !v h#v #v#v@ #v#v:V l d d d d d< 0 % 5 55@ 55/ 4 al p< yt kdE $$If l ֈ T$ d% @ d d d d d< 0 % 4
|
l al p< ytPU P$$If l !v h#v #v#v
|
l al p< yt P$$If l !v h#v #v#v@ #v#v:V l d d d d d< 0 % 5 55@ 55/ 4 al p< yt kdCI $$If l ֈ T$ d% @ d d d d d< 0 % 4
|
#vn#v :V l @ @ < 0 % 5 55
|
l al p< yt P$$If l !v h#v #v#v@ #v#v:V l d d d d d< 0 % 5 55@ 55/ 4 al p< yt kdL $$If l ֈ T$ d% @ d d d d d< 0 % 4
|
5n5 / 4 al p< ytPU kd\ $$If l ֈ T }%
|
l al p< yt $$If l !v h#v %:V l 4
|
n @ @ < 0 % 4
|
0 % 5 %/ / 4 al f4p
|
l al p< ytPU B$$If l !v h#v #v#v
|
yt $$If l !v h#v R#v#vW#v#vl#v :V l 4 ` < ̙ Ob( 0 % 5 R55W55l5 / / / 4 al f4p< ̙ Ob( yt kdP $$If l 4 ֈ RP % R W l ` < ̙ Ob( 0 % 4
|
#vn#v :V l @ @ < 0 % 5 55
|
l al f4p< ̙ Ob( yt $$If l !v h#v R#v#vW#v#vl#v :V l 4 ` < ̙ Ob( 0 % 5 R55W55l5 / / / 4 al f4p< ̙ Ob( yt kdVT $$If l 4 ֈ RP % R W l ` < ̙ Ob( 0 % 4
|
5n5 4 al p< ytPU kd_ $$If l ֈ T }%
|
l al f4p< ̙ Ob( yt d$$If l !v h#v R#v#vW#v#vl#v :V l 4 ` < ̙ Ob( 0 % 5 R55W55l5 / 4 al f4p< ̙ Ob( yt kdW $$If l 4 ֈ RP % R W l ` < ̙ Ob( 0 % 4
|
n @ @ < 0 % 4
|
l al f4p< ̙ Ob( yt d$$If l !v h#v R#v#vW#v#vl#v :V l 4 ` < ̙ Ob( 0 % 5 R55W55l5 / 4 al f4p< ̙ Ob( yt kdd[ $$If l 4 ֈ RP % R W l ` < ̙ Ob( 0 % 4
|
l al p< ytPU P$$If l !v h#v #v#v
|
l al f4p< ̙ Ob( yt $$If l !v h#v R#v#vW#v#vl#v :V l 4 ` < ̙ Ob( 0 % 5 R55W55l5 / / / 4 al f4p< ̙ Ob( yt kd^ $$If l 4 ֈ RP % R W l ` < ̙ Ob( 0 % 4
|
#vn#v :V l @ @ < 0 % 5 55
|
l al f4p< ̙ Ob( yt $$If l !v h#v R#v#vW#v#vl#v :V l 4 ` < ̙ Ob( 0 % 5 R55W55l5 / / / 4 al f4p< ̙ Ob( yt kdrb $$If l 4 ֈ RP % R W l ` < ̙ Ob( 0 % 4
|
5n5 / 4 al p< ytPU kd>c $$If l ֈ T }%
|
l al f4p< ̙ Ob( yt $$If l !v h#v R#v#vW#v#vl#v :V l 4 ` < ̙ Ob( 0 % 5 R55W55l5 / / / 4 al f4p< ̙ Ob( yt kdf $$If l 4 ֈ RP % R W l ` < ̙ Ob( 0 % 4
|
n @ @ < 0 % 4
|
l al f4p< ̙ Ob( yt $$If l !v h#v R#v#vW#v#vl#v :V l 4 ` < ̙ Ob( 0 % 5 R55W55l5 / / / 4 al f4p< ̙ Ob( yt kdi $$If l 4 ֈ RP % R W l ` < ̙ Ob( 0 % 4
|
l al p< ytPU P$$If l !v h#v #v#v
|
l al f4p< ̙ Ob( yt $$If l !v h#v R#v#vW#v#vl#v :V l 4 ` < ̙ Ob( 0 % 5 R55W55l5 / / / 4 al f4p< ̙ Ob( yt kd1m $$If l 4 ֈ RP % R W l ` < ̙ Ob( 0 % 4
|
#vn#v :V l @ @ < 0 % 5 55
|
l al f4p< ̙ Ob( yt $$If l !v h#v R#v#vW#v#vl#v :V l 4 ` < ̙ Ob( 0 % 5 R55W55l5 / / / 4 al f4p< ̙ Ob( yt kdp $$If l 4 ֈ RP % R W l ` < ̙ Ob( 0 % 4
|
5n5 / 4 al p< ytyX kdf $$If l ֈ T }%
|
l al f4p< ̙ Ob( yt d$$If l !v h#v R#v#vW#v#vl#v :V l 4 ` < ̙ Ob( 0 % 5 R55W55l5 / 4 al f4p< ̙ Ob( yt kd[t $$If l 4 ֈ RP % R W l ` < ̙ Ob( 0 % 4
|
n @ @ < 0 % 4
|
l al f4p< ̙ Ob( yt d$$If l !v h#v R#v#vW#v#vl#v :V l 4 ` < ̙ Ob( 0 % 5 R55W55l5 / 4 al f4p< ̙ Ob( yt kdw $$If l 4 ֈ RP % R W l ` < ̙ Ob( 0 % 4
|
l al p< ytyX P$$If l !v h#v #v#v
|
l al f4p< ̙ Ob( yt $$If l !v h#v R#v#vW#v#vl#v :V l 4 d d d d d d< 0 % 5 R55W55l5 / / / 4 al f4p< yt kdM{ $$If l 4 ֈ RP % R W l d d d d d d< 0 % 4
|
#vn#v :V l @ @ < 0 % 5 55
|
l al f4p< yt $$If l !v h#v R#v#vW#v#vl#v :V l 4 d d d d d d< 0 % 5 R55W55l5 / / / / 4 al f4p< yt kd~ $$If l 4 ֈ RP % R W l d d d d d d< 0 % 4
|
5n5 / 4 al p< ytyX kdi $$If l ֈ T }%
|
l al f4p< yt $$If l !v h#v R#v#v#v7#v
|
n @ @ < 0 % 4
|
#v:V l 4 ` < ̙ 0 % 5 R55575
|
l al p< ytyX P$$If l !v h#v #v#v
|
5/ / / / / /
/ 4 al f4p< ̙ ytC'p kd $$If l 4 ֈ RP % R 7
|
#vn#v :V l @ @ < 0 % 5 55
|
` < ̙ 0 % 4
|
5n5 / 4 al p< ytyX kd[m $$If l ֈ T }%
|
l al f4p< ̙ ytC'p $$If l !v h#v R#v#v#v7#v
|
n @ @ < 0 % 4
|
#vl#v :V l 4 ` F ̙ 0 % 5 R55575
|
l al p< ytyX $$If l !v h#v #v#v
|
5l5 / / / / / / / / 4 al f4pF ̙ ytC'p MkdR $$If l 4 ֞ RP % R 7
|
#vn#v :V l
|
l ` F ̙ 0 % 4
|
0 % 5 55
|
l al f4pF ̙ ytC'p $$If l !v h#v R#v#v#v7#v
|
5n5 / 4 al p< ytyX $$If l !v h#v #v#v
|
#vl#v :V l 4 ` F ̙ 0 % 5 R55575
|
#vn#v :V l
|
5l5 / / / / / 4 al f4pF ̙ ytC'p Mkd $$If l 4 ֞ RP % R 7
|
0 % 5 55
|
l ` F ̙ 0 % 4
|
5n5 / 4 al p
|
l al f4pF ̙ ytC'p $$If l !v h#v R#v#v#v7#v
|
ytyX ^$$If l !v h#v #v#v#vY #vn#v :V l ` ` < ̙ ̙ 0 % 5 555Y 5n5 / 4 al p< ̙ ̙ ytyX kdr $$If l ֈ T$ }% Y n ` ` < ̙ ̙ 0 % 4
|
#vl#v :V l 4 ` F ̙ 0 % 5 R55575
|
l al p< ̙ ̙ ytyX P$$If l !v h#v #v#v#vY #vn#v :V l ` ` < ̙ ̙ 0 % 5 555Y 5n5 4 al p< ̙ ̙ ytyX kd!v $$If l ֈ T$ }% Y n ` ` < ̙ ̙ 0 % 4
|
5l5 / / / / / 4 al f4pF ̙ ytC'p Mkd $$If l 4 ֞ RP % R 7
|
l al p< ̙ ̙ ytyX ^$$If l !v h#v #v#v#vY #vn#v :V l ` ` < ̙ ̙ 0 % 5 555Y 5n5 / 4 al p< ̙ ̙ ytyX kdy $$If l ֈ T$ }% Y n ` ` < ̙ ̙ 0 % 4
|
l ` F ̙ 0 % 4
|
l al p< ̙ ̙ ytyX $$If l !v h#v #v#v#vY #vn#v :V l
|
l al f4pF ̙ ytC'p $$If l !v h#v R#v#v#v7#v
|
0 % 5 555Y 5n5 / 4 al p
|
#vl#v :V l 4 ` F ̙ 0 % 5 R55575
|
ytyX $$If l !v h#v #v#vn#v :V l ( p0 0 % 5 55n5 / 4 al p( p0 ytyX $$If l !v h#v #v#vn#v :V l ( p0 0 % 5 55n5 / 4 al p( p0 ytyX ^$$If l !v h#v #v#v#vY #vn#v :V l < 0 % 5 555Y 5n5 / 4 al p< ytyX kd $$If l ֈ T$ }% Y n < 0 % 4
|
5l5 / / / / / 4 al f4pF ̙ ytC'p Mkd $$If l 4 ֞ RP % R 7
|
l al p< ytyX ^$$If l !v h#v #v#v#vY #vn#v :V l < 0 % 5 555Y 5n5 / 4 al p< ytyX kd| $$If l ֈ T$ }% Y n < 0 % 4
|
l ` F ̙ 0 % 4
|
l al p< ytyX $$If l !v h#v %:V l 4
|
l al f4pF ̙ ytC'p $$If l !v h#v R#v#v#v7#v
|
0 % 5 %/ 4 al f4p
|
#vl#v :V l 4 ` F ̙ 0 % 5 R55575
|
yt P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f yt?9 kd $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
5l5 / / / / / 4 al f4pF ̙ ytC'p Mkd $$If l 4 ֞ RP % R 7
|
l al p< ̙ ̙ f f yt?9 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f yt?9 kd $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
l ` F ̙ 0 % 4
|
l al p< ̙ ̙ f f yt?9 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f yt?9 kdY $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
l al f4pF ̙ ytC'p $$If l !v h#v R#v#v#v7#v
|
l al p< ̙ ̙ f f yt?9 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f yt?9 kd $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
#vl#v :V l 4 ` F ̙ 0 % 5 R55575
|
l al p< ̙ ̙ f f yt?9 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f yt?9 kd $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
5l5 / / / / / 4 al f4pF ̙ ytC'p Mkdњ $$If l 4 ֞ RP % R 7
|
l al p< ̙ ̙ f f yt?9 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f yt?9 kdv $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
l ` F ̙ 0 % 4
|
l al p< ̙ ̙ f f yt?9 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f yt?9 kd՛ $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
l al f4pF ̙ ytC'p $$If l !v h#v R#v#v#v7#v
|
l al p< ̙ ̙ f f yt?9 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f yt?9 kd4 $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
#vl#v :V l 4 ` F ̙ 0 % 5 R55575
|
l al p< ̙ ̙ f f yt?9 B$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 554 al p< ̙ ̙ f f yt?9 kd $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
5l5 / / / / / 4 al f4pF ̙ ytC'p Mkd $$If l 4 ֞ RP % R 7
|
l al p< ̙ ̙ f f yt?9 B$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 554 al p< ̙ ̙ f f yt?9 kd $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
l ` F ̙ 0 % 4
|
l al p< ̙ ̙ f f yt?9 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f yt?9 kd5 $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
l al f4pF ̙ ytC'p $$If l !v h#v R#v#v#v7#v
|
l al p< ̙ ̙ f f yt?9 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f yt?9 kd $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
#vl#v :V l 4 ` F ̙ 0 % 5 R55575
|
l al p< ̙ ̙ f f yt?9 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f yt?9 kd $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
5l5 / / / / / 4 al f4pF ̙ ytC'p Mkd $$If l 4 ֞ RP % R 7
|
l al p< ̙ ̙ f f yt?9 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f yt?9 kdR $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
l ` F ̙ 0 % 4
|
l al p< ̙ ̙ f f yt?9 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f yt?9 kd $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
l al f4pF ̙ ytC'p $$If l !v h#v R#v#v#v7#v
|
l al p< ̙ ̙ f f yt?9 l$$If l !v h#v #v#v@ #v#v:V l d d d d d< 0 % 5 55@ 55/ / / 4 al p< yt^0 kd $$If l ֈ T$ d% @ d d d d d< 0 % 4
|
#vl#v :V l 4 ` F ̙ 0 % 5 R55575
|
l al p< yt^0 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f yt?9 kd $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
5l5 / / / / / 4 al f4pF ̙ ytC'p Mkd $$If l 4 ֞ RP % R 7
|
l al p< ̙ ̙ f f yt?9 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f yt?9 kd $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
l ` F ̙ 0 % 4
|
l al p< ̙ ̙ f f yt?9 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f yt?9 kdI $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
l al f4pF ̙ ytC'p $$If l !v h#v R#v#v#v7#v
|
l al p< ̙ ̙ f f yt?9 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f yt?9 kd $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
#vl#v :V l 4 ` F ̙ 0 % 5 R55575
|
l al p< ̙ ̙ f f yt?9 ^$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ / 4 al p< ̙ ̙ f f yt?9 kd $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
5l5 / / / / / / 4 al f4pF ̙ ytC'p Mkd $$If l 4 ֞ RP % R 7
|
l al p< ̙ ̙ f f yt?9 $$If l !v h#v #v#v@ #v#v:V l
|
l ` F ̙ 0 % 4
|
0 % 5 55@ 554 al p< yt^0 $$If l !v h#v #v#v@ #v#v:V l
|
l al f4pF ̙ ytC'p $$If l !v h#v R#v#v#v#v #v:V l 4 ` < ̙ 0 % 5 R5555 5/ / / / / 4 al f4p< ̙ ytC'p kd4 $$If l 4 ֈ RP % R ` < ̙ 0 % 4
|
0 % 5 55@ 554 al p< yt^0 $$If l !v h#v #v#v@ #v#v:V l
|
l al f4p< ̙ ytC'p $$If l !v h#v R#v#v#v#v#v9#vl#v :V l 4 d P ̙ 0 % 5 R5555595l5 / / / / / / / / 4 al f4pP ̙ ytC'p kd $$If l 4 ִ RP b% R 9 l d P ̙ 0 % 4
|
0 % 5 55@ 55/ 4 al p< yt^0 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f ytU
kd $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
l al f4pP ̙ ytC'p t$$If l !v h#v R#v#v#v
|
l al p< ̙ ̙ f f ytU
P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f ytU
kd $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
#v9#vl#v :V l F Ob( 0 % 5 R555
|
l al p< ̙ ̙ f f ytU
P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f ytU
kdX $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
595l5 4 al pF Ob( ytC'p Gkd $$If l ֞ RPb% R
|
l al p< ̙ ̙ f f ytU
P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f ytU
kd $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
9 l F Ob( 0 % 4
|
l al p< ̙ ̙ f f ytU
P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f ytU
kd $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
l al pF Ob( ytC'p t$$If l !v h#v R#v#v#v
|
l al p< ̙ ̙ f f ytU
P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f ytU
kdu $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
#v9#vl#v :V l F Ob( 0 % 5 R555
|
l al p< ̙ ̙ f f ytU
P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ f f 0 % 5 55@ 55/ 4 al p< ̙ ̙ f f ytU
kd $$If l ֈ T$ d% @ < ̙ ̙ f f 0 % 4
|
595l5 4 al pF Ob( ytC'p Gkd? $$If l ֞ RPb% R
|
l al p< ̙ ̙ f f ytU
P$$If l !v h#v #v#v@ #v#v:V l d d d d d< 0 % 5 55@ 55/ 4 al p< yt^0 kd3 $$If l ֈ T$ d% @ d d d d d< 0 % 4
|
9 l F Ob( 0 % 4
|
l al p< yt^0 $$If l !v h#v %:V l 4
|
l al pF Ob( ytC'p t$$If l !v h#v R#v#v#v
|
0 % 5 %/ 4 al f4p
|
#v9#vl#v :V l F Ob( 0 % 5 R555
|
yt$ P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ 0 % 5 55@ 55/ 4 al p< ̙ ̙ yt 7 kdD $$If l ֈ T$ d% @ < ̙ ̙ 0 % 4
|
595l5 4 al pF Ob( ytC'p Gkd $$If l ֞ RPb% R
|
l al p< ̙ ̙ yt 7 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ 0 % 5 55@ 55/ 4 al p< ̙ ̙ yt 7 kd $$If l ֈ T$ d% @ < ̙ ̙ 0 % 4
|
9 l F Ob( 0 % 4
|
l al p< ̙ ̙ yt 7 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ 0 % 5 55@ 55/ 4 al p< ̙ ̙ yt 7 kd $$If l ֈ T$ d% @ < ̙ ̙ 0 % 4
|
l al pF Ob( ytC'p t$$If l !v h#v R#v#v#v
|
l al p< ̙ ̙ yt 7 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ 0 % 5 55@ 55/ 4 al p< ̙ ̙ yt 7 kda $$If l ֈ T$ d% @ < ̙ ̙ 0 % 4
|
#v9#vl#v :V l F Ob( 0 % 5 R555
|
l al p< ̙ ̙ yt 7 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ 0 % 5 55@ 55/ 4 al p< ̙ ̙ yt 7 kd $$If l ֈ T$ d% @ < ̙ ̙ 0 % 4
|
595l5 4 al pF Ob( ytC'p Gkd $$If l ֞ RPb% R
|
l al p< ̙ ̙ yt 7 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ 0 % 5 55@ 55/ 4 al p< ̙ ̙ yt 7 kd $$If l ֈ T$ d% @ < ̙ ̙ 0 % 4
|
9 l F Ob( 0 % 4
|
l al p< ̙ ̙ yt 7 ^$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ 0 % 5 55@ 55/ / 4 al p< ̙ ̙ yt 7 kd~ $$If l ֈ T$ d% @ < ̙ ̙ 0 % 4
|
l al pF Ob( ytC'p t$$If l !v h#v R#v#v#v
|
l al p< ̙ ̙ yt 7 ^$$If l !v h#v #v#v@ #v#v:V l d d d d d< 0 % 5 55@ 55/ / 4 al p< yt 7 kd $$If l ֈ T$ d% @ d d d d d< 0 % 4
|
#v9#vl#v :V l F Ob( 0 % 5 R555
|
l al p< yt 7 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ 0 % 5 55@ 55/ 4 al p< ̙ ̙ yt 7 kdX $$If l ֈ T$ d% @ < ̙ ̙ 0 % 4
|
595l5 4 al pF Ob( ytC'p Gkd| $$If l ֞ RPb% R
|
l al p< ̙ ̙ yt 7 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ 0 % 5 55@ 55/ 4 al p< ̙ ̙ yt 7 kd $$If l ֈ T$ d% @ < ̙ ̙ 0 % 4
|
9 l F Ob( 0 % 4
|
l al p< ̙ ̙ yt 7 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ 0 % 5 55@ 55/ 4 al p< ̙ ̙ yt 7 kd $$If l ֈ T$ d% @ < ̙ ̙ 0 % 4
|
l al pF Ob( ytC'p t$$If l !v h#v R#v#v#v
|
l al p< ̙ ̙ yt 7 P$$If l !v h#v #v#v@ #v#v:V l < ̙ ̙ 0 % 5 55@ 55/ 4 al p< ̙ ̙ yt 7 kdu $$If l ֈ T$ d% @ < ̙ ̙ 0 % 4
|
#v9#vl#v :V l F Ob( 0 % 5 R555
|
l al p< ̙ ̙ yt 7 P$$If l !v h#v #v#v@ #v#v:V l d d d d d< 0 % 5 55@ 55/ 4 al p< yt kd $$If l ֈ T$ d% @ d d d d d< 0 % 4
|
595l5 4 al pF Ob( ytC'p Gkd; $$If l ֞ RPb% R
|
l al p< yt P$$If l !v h#v #v#v@ #v#v:V l d d d d d< 0 % 5 55@ 55/ 4 al p< yt kd3 $$If l ֈ T$ d% @ d d d d d< 0 % 4
|
9 l F Ob( 0 % 4
|
l al p< yt P$$If l !v h#v #v#v@ #v#v:V l d d d d d< 0 % 5 55@ 55/ 4 al p< yt kd $$If l ֈ T$ d% @ d d d d d< 0 % 4
|
l al pF Ob( ytC'p t$$If l !v h#v R#v#v#v
|
l al p< yt P$$If l !v h#v #v#v@ #v#v:V l d d d d d< 0 % 5 55@ 55/ 4 al p< yt kd $$If l ֈ T$ d% @ d d d d d< 0 % 4
|
#v9#vl#v :V l F Ob( 0 % 5 R555
|
l al p< yt $$If l !v h#v D%:V l 4
|
595l5 4 al pF Ob( ytC'p Gkd $$If l ֞ RPb% R
|
0 D% 5 D%/ / 4 al f4p
|
9 l F Ob( 0 % 4
|
yt i $$If l !v h#v #v#vT#v$ #v8#v@ :V l 4 ` < ̙ 0 D% 5 55T5$ 585@ / / / 4 al f4p< ̙ ytA kd$ $$If l 4 ֈ T D% T $ 8 @ ` < ̙ 0 D% 4
|
l al pF Ob( ytC'p t$$If l !v h#v R#v#v#v
|
l al f4p< ̙ ytA $$If l !v h#v #v#vT#v$ #v8#v@ :V l 4 ` < ̙ 0 D% 5 55T5$ 585@ / / / 4 al f4p< ̙ ytA kd' $$If l 4 ֈ T D% T $ 8 @ ` < ̙ 0 D% 4
|
#v9#vl#v :V l F Ob( 0 % 5 R555
|
l al f4p< ̙ ytA d$$If l !v h#v #v#vT#v$ #v8#v@ :V l 4 ` < ̙ 0 D% 5 55T5$ 585@ / 4 al f4p< ̙ ytA kd:+ $$If l 4 ֈ T D% T $ 8 @ ` < ̙ 0 D% 4
|
595l5 4 al pF Ob( ytC'p Gkd $$If l ֞ RPb% R
|
l al f4p< ̙ ytA d$$If l !v h#v #v#vT#v$ #v8#v@ :V l 4 ` < ̙ 0 D% 5 55T5$ 585@ / 4 al f4p< ̙ ytA kd. $$If l 4 ֈ T D% T $ 8 @ ` < ̙ 0 D% 4
|
9 l F Ob( 0 % 4
|
l al f4p< ̙ ytA $$If l !v h#v #v#vT#v$ #v8#v@ :V l 4 ` < ̙ 0 D% 5 55T5$ 585@ / / / 4 al f4p< ̙ ytA kd,2 $$If l 4 ֈ T D% T $ 8 @ ` < ̙ 0 D% 4
|
l al pF Ob( ytC'p t$$If l !v h#v R#v#v#v
|
l al f4p< ̙ ytA $$If l !v h#v #v#vT#v$ #v8#v@ :V l 4 ` < ̙ 0 D% 5 55T5$ 585@ / / / 4 al f4p< ̙ ytA kd5 $$If l 4 ֈ T D% T $ 8 @ ` < ̙ 0 D% 4
|
#v9#vl#v :V l F Ob( 0 % 5 R555
|
l al f4p< ̙ ytA $$If l !v h#v #v#vT#v$ #v8#v@ :V l 4 ` < ̙ 0 D% 5 55T5$ 585@ / / / 4 al f4p< ̙ ytA kdV9 $$If l 4 ֈ T D% T $ 8 @ ` < ̙ 0 D% 4
|
595l5 4 al pF Ob( ytC'p Gkdx $$If l ֞ RPb% R
|
l al f4p< ̙ ytA $$If l !v h#v #v#vT#v$ #v8#v@ :V l 4 ` < ̙ 0 D% 5 55T5$ 585@ / / / 4 al f4p< ̙ ytA kd< $$If l 4 ֈ T D% T $ 8 @ ` < ̙ 0 D% 4
|
9 l F Ob( 0 % 4
|
l al f4p< ̙ ytA $$If l !v h#v #v#vT#v$ #v8#v@ :V l 4 ` < ̙ 0 D% 5 55T5$ 585@ / / / 4 al f4p< ̙ ytA kd@ $$If l 4 ֈ T D% T $ 8 @ ` < ̙ 0 D% 4
|
l al pF Ob( ytC'p t$$If l !v h#v R#v#v#v
|
l al f4p< ̙ ytA $$If l !v h#v #v#vT#v$ #v8#v@ :V l 4 ` < ̙ 0 D% 5 55T5$ 585@ / / / 4 al f4p< ̙ ytA kdD $$If l 4 ֈ T D% T $ 8 @ ` < ̙ 0 D% 4
|
#v9#vl#v :V l F Ob( 0 % 5 R555
|
l al f4p< ̙ ytA d$$If l !v h#v #v#vT#v$ #v8#v@ :V l 4 ` < ̙ 0 D% 5 55T5$ 585@ / 4 al f4p< ̙ ytA kdG $$If l 4 ֈ T D% T $ 8 @ ` < ̙ 0 D% 4
|
595l5 4 al pF Ob( ytC'p Gkd7 $$If l ֞ RPb% R
|
l al f4p< ̙ ytA $$If l !v h#v #v#vT#v$ #v8#v@ :V l 4 ` < ̙ 0 D% 5 55T5$ 585@ / / / 4 al f4p< ̙ ytA kd#K $$If l 4 ֈ T D% T $ 8 @ ` < ̙ 0 D% 4
|
9 l F Ob( 0 % 4
|
l al f4p< ̙ ytA $$If l !v h#v #v#vT#v$ #v8#v@ :V l 4 ` < ̙ 0 D% 5 55T5$ 585@ / / / 4 al f4p< ̙ ytA kdN $$If l 4 ֈ T D% T $ 8 @ ` < ̙ 0 D% 4
|
l al pF Ob( ytC'p t$$If l !v h#v R#v#v#v
|
l al f4p< ̙ ytA $$If l !v h#v #v#vT#v$ #v8#v@ :V l 4 ` < ̙ 0 D% 5 55T5$ 585@ / / / 4 al f4p< ̙ ytA kdMR $$If l 4 ֈ T D% T $ 8 @ ` < ̙ 0 D% 4
|
#v9#vl#v :V l F Ob( 0 % 5 R555
|
l al f4p< ̙ ytA $$If l !v h#v #v#vT#v$ #v8#v@ :V l 4 ` < ̙ 0 D% 5 55T5$ 585@ / / / 4 al f4p< ̙ ytA kdU $$If l 4 ֈ T D% T $ 8 @ ` < ̙ 0 D% 4
|
595l5 4 al pF Ob( ytC'p Gkd $$If l ֞ RPb% R
|
l al f4p< ̙ ytA $$If l !v h#v #v#vT#v$ #v8#v@ :V l 4 ` < ̙ 0 D% 5 55T5$ 585@ / / / / / 4 al f4p< ̙ yt kdwY $$If l 4 ֈ T D% T $ 8 @ ` < ̙ 0 D% 4
|
9 l F Ob( 0 % 4
|
l al f4p< ̙ yt $$If l !v h#v #vH#v8#v@ :V l ( p0 0 D% 5 5H585@ / 4 al p( p0 yt $$If l !v h#v #vH#v8#v@ :V l ( p0 0 D% 5 5H585@ / 4 al p( p0 yt P$$If l !v h#v #v#v #v8#v@ :V l < 0 D% 5 55 585@ / 4 al p< ytfi kdX_ $$If l ֈ T$ D% 8 @ < 0 D% 4
|
l al pF Ob( ytC'p t$$If l !v h#v R#v#v#v
|
l al p< ytfi P$$If l !v h#v #v#v #v8#v@ :V l < 0 D% 5 55 585@ / 4 al p< ytfi kdb $$If l ֈ T$ D% 8 @ < 0 D% 4
|
#v9#vl#v :V l F Ob( 0 % 5 R555
|
l al p< ytfi $$If l !v h#v D%:V l
|
595l5 4 al pF Ob( ytC'p Gkd $$If l ֞ RPb% R
|
0 D% 5 D%/ 4 al p
|
9 l F Ob( 0 % 4
|
yt$ P$$If l !v h#v #v#v #v8#v@ :V l ` < ̙ ̙ 0 D% 5 55 585@ / 4 al p< ̙ ̙ yt kdf $$If l ֈ T$ D% 8 @ ` < ̙ ̙ 0 D% 4
|
l al pF Ob( ytC'p t$$If l !v h#v R#v#v#v
|
l al p< ̙ ̙ yt P$$If l !v h#v #v#v #v8#v@ :V l ` < ̙ ̙ 0 D% 5 55 585@ / 4 al p< ̙ ̙ yt kd!j $$If l ֈ T$ D% 8 @ ` < ̙ ̙ 0 D% 4
|
#v9#vl#v :V l F Ob( 0 % 5 R555
|
l al p< ̙ ̙ yt P$$If l !v h#v #v#v #v8#v@ :V l ` < ̙ ̙ 0 D% 5 55 585@ / 4 al p< ̙ ̙ yt kdm $$If l ֈ T$ D% 8 @ ` < ̙ ̙ 0 D% 4
|
595l5 4 al pF Ob( ytC'p Gkdt $$If l ֞ RPb% R
|
l al p< ̙ ̙ yt P$$If l !v h#v #v#v #v8#v@ :V l ` < ̙ ̙ 0 D% 5 55 585@ / 4 al p< ̙ ̙ yt kdp $$If l ֈ T$ D% 8 @ ` < ̙ ̙ 0 D% 4
|
9 l F Ob( 0 % 4
|
l al p< ̙ ̙ yt P$$If l !v h#v #v#v #v8#v@ :V l ` < ̙ ̙ 0 D% 5 55 585@ / 4 al p< ̙ ̙ yt kd>t $$If l ֈ T$ D% 8 @ ` < ̙ ̙ 0 D% 4
|
l al pF Ob( ytC'p t$$If l !v h#v R#v#v#v
|
l al p< ̙ ̙ yt P$$If l !v h#v #v#v #v8#v@ :V l ` < ̙ ̙ 0 D% 5 55 585@ / 4 al p< ̙ ̙ yt kdw $$If l ֈ T$ D% 8 @ ` < ̙ ̙ 0 D% 4
|
#v9#vl#v :V l F Ob( 0 % 5 R555
|
l al p< ̙ ̙ yt P$$If l !v h#v #v#v #v8#v@ :V l ` < ̙ ̙ 0 D% 5 55 585@ / 4 al p< ̙ ̙ yt kdz $$If l ֈ T$ D% 8 @ ` < ̙ ̙ 0 D% 4
|
595l5 4 al pF Ob( ytC'p Gkd3 $$If l ֞ RPb% R
|
l al p< ̙ ̙ yt P$$If l !v h#v #v#v #v8#v@ :V l ` < ̙ ̙ 0 D% 5 55 585@ / 4 al p< ̙ ̙ yt kd[~ $$If l ֈ T$ D% 8 @ ` < ̙ ̙ 0 D% 4
|
9 l F Ob( 0 % 4
|
l al p< ̙ ̙ yt P$$If l !v h#v #v#v #v8#v@ :V l ` < ̙ ̙ 0 D% 5 55 585@ / 4 al p< ̙ ̙ yt kd $$If l ֈ T$ D% 8 @ ` < ̙ ̙ 0 D% 4
|
l al pF Ob( ytC'p $$If l !v h#v R#v#v#v#v#v9#vl#v :V l 4 d P ̙ 0 % 5 R5555595l5 / / / / / / / / 4 al f4pP ̙ yt kd $$If l 4 ִ RP b% R 9 l d P ̙ 0 % 4
|
l al p< ̙ ̙ yt P$$If l !v h#v #v#v #v8#v@ :V l ` < ̙ ̙ 0 D% 5 55 585@ / 4 al p< ̙ ̙ yt kd $$If l ֈ T$ D% 8 @ ` < ̙ ̙ 0 D% 4
|
l al f4pP ̙ yt $$If l !v h#v R#v#v#v#v#v9#vl#v :V l 4 d P ̙ 0 % 5 R5555595l5 / / / / / 4 al f4pP ̙ ytC'p kd $$If l 4 ִ RP b% R 9 l d P ̙ 0 % 4
|
l al p< ̙ ̙ yt P$$If l !v h#v #v#v #v8#v@ :V l d d d d d< 0 D% 5 55 585@ / 4 al p< yt kdx $$If l ֈ T$ D% 8 @ d d d d d< 0 D% 4
|
l al f4pP ̙ ytC'p $$If l !v h#v R#v#v#v#v#v9#vl#v :V l 4 d P ̙ 0 % 5 R5555595l5 / / / / / 4 al f4pP ̙ ytC'p kd $$If l 4 ִ RP b% R 9 l d P ̙ 0 % 4
|
l al p< yt P$$If l !v h#v #v#v #v8#v@ :V l d d d d d< 0 D% 5 55 585@ / 4 al p< yt kd $$If l ֈ T$ D% 8 @ d d d d d< 0 D% 4
|
l al f4pP ̙ ytC'p $$If l !v h#v R#v#v#v#v#v9#vl#v :V l 4 d P ̙ 0 % 5 R5555595l5 / / / / / 4 al f4pP ̙ ytC'p kdo $$If l 4 ִ RP b% R 9 l d P ̙ 0 % 4
|
l al p< yt P$$If l !v h#v #v#v #v8#v@ :V l d d d d d< 0 D% 5 55 585@ / 4 al p< ytNZ kd6 $$If l ֈ T$ D% 8 @ d d d d d< 0 D% 4
|
l al f4pP ̙ ytC'p $$If l !v h#v R#v#v#v#v#v9#vl#v :V l 4 d P ̙ 0 % 5 R5555595l5 / / / / / 4 al f4pP ̙ ytC'p kd $$If l 4 ִ RP b% R 9 l d P ̙ 0 % 4
|
l al p< ytNZ $$If l !v h#v #v#v #ve#v8#v@ :V l P 0 D% 5 55 5e585@ / 4 al pP ytPU kd $$If l ִ T$ / D% e 8 8 @ P 0 D% 4
|
l al f4pP ̙ ytC'p $$If l !v h#v R#v#v#v#v#v9#vl#v :V l 4 d P ̙ 0 % 5 R5555595l5 / / / / / 4 al f4pP ̙ ytC'p kdQ $$If l 4 ִ RP b% R 9 l d P ̙ 0 % 4
|
l al pP ytPU $$If l !v h#v #v#v #ve#v8#v@ :V l P 0 D% 5 55 5e585@ / 4 al pP yt9Da kd $$If l ִ T$ / D% e 8 8 @ P 0 D% 4
|
l al f4pP ̙ ytC'p $$If l !v h#v R#v#v#v#v#v9#vl#v :V l 4 d P ̙ 0 % 5 R5555595l5 / / / / / 4 al f4pP ̙ ytC'p kd $$If l 4 ִ RP b% R 9 l d P ̙ 0 % 4
|
l al pP yt9Da $$If l !v h#v #v#v #ve#v8#v@ :V l P 0 D% 5 55 5e585@ / 4 al pP yt9Da kd $$If l ִ T$ / D% e 8 8 @ P 0 D% 4
|
l al f4pP ̙ ytC'p $$If l !v h#v R#v#v#v#v#v9#vl#v :V l 4 d P ̙ 0 % 5 R5555595l5 / / / / / 4 al f4pP ̙ ytC'p kd3 $$If l 4 ִ RP b% R 9 l d P ̙ 0 % 4
|
l al pP yt9Da $$If l !v h#v #v#v #ve#v8#v@ :V l P 0 D% 5 55 5e585@ / 4 al pP ytPU kdȞ $$If l ִ T$ / D% e 8 8 @ P 0 D% 4
|
l al f4pP ̙ ytC'p $$If l !v h#v R#v#v#v#v#v9#vl#v :V l 4 d P ̙ 0 % 5 R5555595l5 / / / / / 4 al f4pP ̙ ytC'p kd $$If l 4 ִ RP b% R 9 l d P ̙ 0 % 4
|
l al pP ytPU $$If l !v h#v #v#v #ve#v8#v@ :V l P 0 D% 5 55 5e585@ / 4 al pP yt9Da kd٢ $$If l ִ T$ / D% e 8 8 @ P 0 D% 4
|
l al f4pP ̙ ytC'p $$If l !v h#v R#v#v#v#v#v9#vl#v :V l 4 d P ̙ 0 % 5 R5555595l5 / / / / / 4 al f4pP ̙ ytC'p kd $$If l 4 ִ RP b% R 9 l d P ̙ 0 % 4
|
l al pP yt9Da $$If l !v h#v #v#v #ve#v8#v@ :V l P 0 D% 5 55 5e585@ / 4 al pP yt9Da kd $$If l ִ T$ / D% e 8 8 @ P 0 D% 4
|
l al f4pP ̙ ytC'p $$If l !v h#v D%:V l
|
l al pP yt9Da $$If l !v h#v #v#v #ve#v8#v@ :V l P 0 D% 5 55 5e585@ / 4 al pP yt9Da kd $$If l ִ T$ / D% e 8 8 @ P 0 D% 4
|
0 D% 5 D%/ 4 al p
|
l al pP yt9Da $$If l !v h#v #v#v #ve#v8#v@ :V l P 0 D% 5 55 5e585@ / 4 al pP yt9Da kd $$If l ִ T$ / D% e 8 8 @ P 0 D% 4
|
yt$ P$$If l !v h#v #v#v #v8#v@ :V l ` < ̙ ̙ 0 D% 5 55 585@ / 4 al p< ̙ ̙ yt kd2 $$If l ֈ T$ D% 8 @ ` < ̙ ̙ 0 D% 4
|
l al pP yt9Da $$If l !v h#v #v#v #ve#v8#v@ :V l P 0 D% 5 55 5e585@ / 4 al pP yt9Da kd $$If l ִ T$ / D% e 8 8 @ P 0 D% 4
|
l al p< ̙ ̙ yt P$$If l !v h#v #v#v #v8#v@ :V l ` < ̙ ̙ 0 D% 5 55 585@ / 4 al p< ̙ ̙ yt kd $$If l ֈ T$ D% 8 @ ` < ̙ ̙ 0 D% 4
|
l al pP yt9Da $$If l !v h#v #v#v #ve#v8#v@ :V l P 0 D% 5 55 5e585@ / 4 al pP yt9Da kd. $$If l ִ T$ / D% e 8 8 @ P 0 D% 4
|
l al p< ̙ ̙ yt P$$If l !v h#v #v#v #v8#v@ :V l ` < ̙ ̙ 0 D% 5 55 585@ / 4 al p< ̙ ̙ yt kd $$If l ֈ T$ D% 8 @ ` < ̙ ̙ 0 D% 4
|
l al pP yt9Da $$If l !v h#v #v#v #ve#v8#v@ :V l P 0 D% 5 55 5e585@ / 4 al pP yt9Da kd? $$If l ִ T$ / D% e 8 8 @ P 0 D% 4
|
l al p< ̙ ̙ yt P$$If l !v h#v #v#v #v8#v@ :V l ` < ̙ ̙ 0 D% 5 55 585@ / 4 al p< ̙ ̙ yt kdO# $$If l ֈ T$ D% 8 @ ` < ̙ ̙ 0 D% 4
|
l al pP yt9Da $$If l !v h#v #v#v #ve#v8#v@ :V l P 0 D% 5 55 5e585@ / 4 al pP yt9Da kdP $$If l ִ T$ / D% e 8 8 @ P 0 D% 4
|
l al p< ̙ ̙ yt P$$If l !v h#v #v#v #v8#v@ :V l ` < ̙ ̙ 0 D% 5 55 585@ / 4 al p< ̙ ̙ yt kd& $$If l ֈ T$ D% 8 @ ` < ̙ ̙ 0 D% 4
|
l al pP yt9Da $$If l !v h#v #v#v #ve#v8#v@ :V l P 0 D% 5 55 5e585@ / 4 al pP ytPU kda $$If l ִ T$ / D% e 8 8 @ P 0 D% 4
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l al p< ̙ ̙ yt P$$If l !v h#v #v#v #v8#v@ :V l ` < ̙ ̙ 0 D% 5 55 585@ / 4 al p< ̙ ̙ yt kd
* $$If l ֈ T$ D% 8 @ ` < ̙ ̙ 0 D% 4
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l al pP ytPU $$If l !v h#v #v#v #ve#v8#v@ :V l P 0 D% 5 55 5e585@ / 4 al pP ytPU kdr $$If l ִ T$ / D% e 8 8 @ P 0 D% 4
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l al p< ̙ ̙ yt P$$If l !v h#v #v#v #v8#v@ :V l ` < ̙ ̙ 0 D% 5 55 585@ / 4 al p< ̙ ̙ yt kdl- $$If l ֈ T$ D% 8 @ ` < ̙ ̙ 0 D% 4
|
l al pP ytPU $$If l !v h#v #v#v #ve#v8#v@ :V l P 0 D% 5 55 5e585@ / 4 al pP ytPU kd $$If l ִ T$ / D% e 8 8 @ P 0 D% 4
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l al p< ̙ ̙ yt P$$If l !v h#v #v#v #v8#v@ :V l ` < ̙ ̙ 0 D% 5 55 585@ / 4 al p< ̙ ̙ yt kd0 $$If l ֈ T$ D% 8 @ ` < ̙ ̙ 0 D% 4
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l al pP ytPU $$If l !v h#v #v#v #ve#v8#v@ :V l P 0 D% 5 55 5e585@ / 4 al pP ytPU kd $$If l ִ T$ / D% e 8 8 @ P 0 D% 4
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l al p< ̙ ̙ yt P$$If l !v h#v #v#v #v8#v@ :V l ` < ̙ ̙ 0 D% 5 55 585@ / 4 al p< ̙ ̙ yt kd*4 $$If l ֈ T$ D% 8 @ ` < ̙ ̙ 0 D% 4
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l al pP ytPU $$If l !v h#v #v#v #ve#v8#v@ :V l P 0 D% 5 55 5e585@ / 4 al pP ytPU kd $$If l ִ T$ / D% e 8 8 @ P 0 D% 4
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l al p< ̙ ̙ yt P$$If l !v h#v #v#v #v8#v@ :V l ` < ̙ ̙ 0 D% 5 55 585@ / 4 al p< ̙ ̙ yt kd7 $$If l ֈ T$ D% 8 @ ` < ̙ ̙ 0 D% 4
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l al pP ytPU $$If l !v h#v #v#v #ve#v8#v@ :V l P 0 D% 5 55 5e585@ / 4 al pP ytPU kd $$If l ִ T$ / D% e 8 8 @ P 0 D% 4
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l al p< ̙ ̙ yt P$$If l !v h#v #v#v #v8#v@ :V l d d d d d< 0 D% 5 55 585@ / 4 al p< yt kd: $$If l ֈ T$ D% 8 @ d d d d d< 0 D% 4
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l al pP ytPU $$If l !v h#v #v#v #ve#v8#v@ :V l P 0 D% 5 55 5e585@ / 4 al pP yt9Da kd $$If l ִ T$ / D% e 8 8 @ P 0 D% 4
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l al p< yt P$$If l !v h#v #v#v #v8#v@ :V l d d d d d< 0 D% 5 55 585@ / 4 al p< yt kdG> $$If l ֈ T$ D% 8 @ d d d d d< 0 D% 4
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l al pP yt9Da $$If l !v h#v #v#v #ve#v8#v@ :V l P 0 D% 5 55 5e585@ / 4 al pP ytPU kd $$If l ִ T$ / D% e 8 8 @ P 0 D% 4
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l al p< yt P$$If l !v h#v #v#v #v8#v@ :V l d d d d d< 0 D% 5 55 585@ / 4 al p< ytNZ kdA $$If l ֈ T$ D% 8 @ d d d d d< 0 D% 4
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l al pP ytPU P$$If l !v h#v #v#v #v8#v@ :V l < 0 D% 5 55 585@ / 4 al p< ytPU kd $$If l ֈ T$ D% 8 @ < 0 D% 4
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l al p< ytNZ $$If l !v h#v #v#v #ve#v8#v@ :V l d d P 0 D% 5 55 5e585@ / 4 al pP yt`i kdE $$If l ִ T$ / D% e 8 8 @ d d P 0 D% 4
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l al p< ytPU $$If l !v h#v #v#v8#v@ :V l 4 ` ( 0 D% 5 5585@ / 4 al f4p( yt?9 $$If !v h#v #v :V l
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l al pP yt`i $$If l !v h#v #v#v #ve#v8#v@ :V l d d P 0 D% 5 55 5e585@ / 4 al pP yt`i kdI $$If l ִ T$ / D% e 8 8 @ d d P 0 D% 4
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l al pP yt`i $$If l !v h#v #v#v #ve#v8#v@ :V l d d P 0 D% 5 55 5e585@ / 4 al pP yt`i kd'M $$If l ִ T$ / D% e 8 8 @ d d P 0 D% 4
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l al pP yt`i $$If l !v h#v #v#v #ve#v8#v@ :V l d d P 0 D% 5 55 5e585@ / 4 al pP yt`i kd8Q $$If l ִ T$ / D% e 8 8 @ d d P 0 D% 4
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l al pP yt`i $$If l !v h#v #v#v #ve#v8#v@ :V l d d P 0 D% 5 55 5e585@ / 4 al pP yt`i kdIU $$If l ִ T$ / D% e 8 8 @ d d P 0 D% 4
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l al pP yt`i $$If l !v h#v #v#v #ve#v8#v@ :V l d d P 0 D% 5 55 5e585@ / 4 al pP yt`i kdZY $$If l ִ T$ / D% e 8 8 @ d d P 0 D% 4
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l al pP yt`i $$If l !v h#v #v#v #ve#v8#v@ :V l d d P 0 D% 5 55 5e585@ / 4 al pP yt`i kdk] $$If l ִ T$ / D% e 8 8 @ d d P 0 D% 4
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t Z 0 $ , 5 5N5O5N5O5N5O5N5 O/ af4pZ ytC kd. $$If l 4
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l al pP yt`i $$If l !v h#v #v#v #ve#v8#v@ :V l d d P 0 D% 5 55 5e585@ / 4 al pP yt`i kd|a $$If l ִ T$ / D% e 8 8 @ d d P 0 D% 4
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l al pP yt`i $$If l !v h#v #v#v #ve#v8#v@ :V l d d P 0 D% 5 55 5e585@ / 4 al pP yt`i kde $$If l ִ T$ / D% e 8 8 @ d d P 0 D% 4
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t Z 0 $ $ $ $ $ 4 4
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l al pP yt`i $$If l !v h#v #v#v #ve#v8#v@ :V l d d P 0 D% 5 55 5e585@ / 4 al pP yt`i kdi $$If l ִ T$ / D% e 8 8 @ d d P 0 D% 4
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|
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Bird Computer ?a Raptor32 CPU Core Title [ 8 @ _PID_HLINKS A h[ ^ j a J A L c m C M P = e . . / r a p t o r 3 2 . h t m l J A L # J A L = e . . / r a p t o r 3 2 . h t m l J A L # J A L j a J A L # e . . / r a p t o r 3 2 . h t m l X O R # X O R j a J A L 2 e . . / r a p t o r 3 2 . h t m l S B C # S B C = e . . / r a p t o r 3 2 . h t m l J A L # J A L = e . . / r a p t o r 3 2 . h t m l J A L # J A L 8 e . . / r a p t o r 3 2 . h t m l N M I # N M I = e . . / r a p t o r 3 2 . h t m l J A L # J A L " e . . / r a p t o r 3 2 . h t m l B F I N S # B F I N S b c B c c b c B c c b c B c c b c B c c b c B c c b c B c c b c B c c b c B c c x o X O R X N O R t s T S R t r T R S s u S U B s h S H U s h S H R s h S H L s h S H s g S G N s b S B U s b S B r o R O R r o R O L m l M L O l h L H U l h L H l b L B U l b L B } F C c c S z F C c c S w F A D D t F A B S \ q F 2 I N T e n n E N D e i k E I d i h D I V d i e D I c c b C c c c c _ C c c c c \ C c c c c Y C c c c c V C c c c c S C c c
P C A L L b c M B c c b c J B c c b r G B R K b c D B c c b c A B c c b c > B c c b c ; B c c b c 8 B c c b c 5 B c c b c 2 B c c b c / B c c , B F I N S ) B F E X T
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& B F C L R # B F C H G b c B c c b c B c c a s A S R a n A N D a d A D D F C c c S F C c c S F C c c S F C c c S F C c c S \ F 2 I N T F N E G F N A B S F A B S F D I V F M U L F S U B F A D D F C c c S F C c c S F C c c S F C c c S F C c c S \ F 2 I N T F N E G F N A B S F A B S F D I V F M U L F S U B F A D D t s T S R t r T R S e n E N D w a W A I e n E N D S T O P r i R I e i E I d i D I r o R O L a s A S R s h S H R r o R O L s h S H L a s A S R a s A S R s h S H R r o R O L s h S H L o r O R a n A N D x o X O R c g C G T c l ~ C L E c n { C N E c e x C E Q c g u C G T c l r C L E c g o C G E c l l C L T c g i C G T c l f C L E c g c C G E c l ` C L T n o ] N O P j a Z J A L b c W B c c b c T B c c b c Q B c c b c N B c c b c K B c c b c H B c c b c E B c c b c B B c c b c ? B c c b c < B c c b c 9 B c c b c 6 B c c b c 3 B c c b c 0 B c c m e - D C A C H E m e * D C A C H E o r ' O R a n $ A N D x o ! X O R m o M O D M U L H d i D I V m u M U L s u S U B a d A D D B F I N S c g C G T c l C L E c n C N E c e C E Q c g C G T c l C L E c g C G E c l C L T c g C G T c l C L E c g C G E c l C L T n o N O P
C A L L j m J M P j a J A L b c B c c b c B c c b c B c c b c B c c b c B c c b c B c c b c B c c b c B c c b c B c c b c B c c b c B c c b c B c c b c B c c b c B c c m e D C A C H E m e D C A C H E B F I N S o r O R a n A N D x o X O R o r O R a n A N D x o X O R m l M L O o r O R a n A N D x o X O R m o M O D M U L H d i D I V m u M U L s u | S U B a d y A D D s u v S U B a d s A D D s u p S U B a d m A D D l h j L H Z l b g L B Z s w d S W s h a S H s b ^ S B l w [ L W l h X L H l b U L B R F D I V O F M U L s u L S U B a d I A D D
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F B F C L R C B F E X T @ B F I N S r o = R O R r o : R O L s h 7 S H R a s 4 A S R s h 1 S H L . X N O R n o + N O R ( N A N D n o % N O T x o " X O R o r O R a n A N D c c C c c c c C c c c c C c c c c C c c c c
C c c c c
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C c c c c C c c c c C c c c c C c c c c C c c m o M O D d i D I V M U L H m u M U L s u S U B a d A D D r t R T X s y S Y S j m J M P j a J A L r e R E T
C A L L b c B c c b c B c c b c B c c b c B c c b c B c c b c B c c b c B c c b c B c c b c B c c b c B c c b c B c c b c B c c c m C M P c m C M P c n C N E c e C E Q c g C G T c l C L E c g C G E c l C L T r i R I F d i D I e i E I t s T S R t r T R S 2 _ T o c 1 7 0 7 7 9 4 1 8 2 _ T o c 1 7 0 7 7 9 4 1 7 2 | _ T o c 1 7 0 7 7 9 4 1 6 2 v _ T o c 1 7 0 7 7 9 4 1 5 2 p _ T o c 1 7 0 7 7 9 4 1 4 2 j _ T o c 1 7 0 7 7 9 4 1 3 2 d _ T o c 1 7 0 7 7 9 4 1 2 2 ^ _ T o c 1 7 0 7 7 9 4 1 1 2 X _ T o c 1 7 0 7 7 9 4 1 0 2 R _ T o c 1 7 0 7 7 9 4 0 9 2 L _ T o c 1 7 0 7 7 9 4 0 8 2 F _ T o c 1 7 0 7 7 9 4 0 7 2 @ _ T o c 1 7 0 7 7 9 4 0 6 2 : _ T o c 1 7 0 7 7 9 4 0 5 2 4 _ T o c 1 7 0 7 7 9 4 0 4 2 . _ T o c 1 7 0 7 7 9 4 0 3 2 ( _ T o c 1 7 0 7 7 9 4 0 2 2 " _ T o c 1 7 0 7 7 9 4 0 1 2 _ T o c 1 7 0 7 7 9 4 0 0 5 _ T o c 1 7 0 7 7 9 3 9 9 5 _ T o c 1 7 0 7 7 9 3 9 8 5
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_ T o c 1 7 0 7 7 9 3 9 7 5 _ T o c 1 7 0 7 7 9 3 9 6 5 _ T o c 1 7 0 7 7 9 3 9 5 5 _ T o c 1 7 0 7 7 9 3 9 4 5 _ T o c 1 7 0 7 7 9 3 9 3 5 _ T o c 1 7 0 7 7 9 3 9 2 5 _ T o c 1 7 0 7 7 9 3 9 1 5 _ T o c 1 7 0 7 7 9 3 9 0 5 _ T o c 1 7 0 7 7 9 3 8 9 5 _ T o c 1 7 0 7 7 9 3 8 8 5 _ T o c 1 7 0 7 7 9 3 8 7 5 _ T o c 1 7 0 7 7 9 3 8 6 5 _ T o c 1 7 0 7 7 9 3 8 5 5 _ T o c 1 7 0 7 7 9 3 8 4 5 _ T o c 1 7 0 7 7 9 3 8 3 5 _ T o c 1 7 0 7 7 9 3 8 2 5 _ T o c 1 7 0 7 7 9 3 8 1 5 _ T o c 1 7 0 7 7 9 3 8 0 5 _ T o c 1 7 0 7 7 9 3 7 9 5 _ T o c 1 7 0 7 7 9 3 7 8 5 _ T o c 1 7 0 7 7 9 3 7 7 5 _ T o c 1 7 0 7 7 9 3 7 6 5 _ T o c 1 7 0 7 7 9 3 7 5 5 _ T o c 1 7 0 7 7 9 3 7 4 5 z _ T o c 1 7 0 7 7 9 3 7 3 5 t _ T o c 1 7 0 7 7 9 3 7 2 5 n _ T o c 1 7 0 7 7 9 3 7 1 5 h _ T o c 1 7 0 7 7 9 3 7 0 5 b _ T o c 1 7 0 7 7 9 3 6 9 5 \ _ T o c 1 7 0 7 7 9 3 6 8 5 V _ T o c 1 7 0 7 7 9 3 6 7 5 P _ T o c 1 7 0 7 7 9 3 6 6 5 J _ T o c 1 7 0 7 7 9 3 6 5 5 D _ T o c 1 7 0 7 7 9 3 6 4 5 > _ T o c 1 7 0 7 7 9 3 6 3 5 8 _ T o c 1 7 0 7 7 9 3 6 2 5 2 _ T o c 1 7 0 7 7 9 3 6 1 5 , _ T o c 1 7 0 7 7 9 3 6 0 5 & _ T o c 1 7 0 7 7 9 3 5 9 5 _ T o c 1 7 0 7 7 9 3 5 8 5 _ T o c 1 7 0 7 7 9 3 5 7 5 _ T o c 1 7 0 7 7 9 3 5 6 5 _ T o c 1 7 0 7 7 9 3 5 5 5 _ T o c 1 7 0 7 7 9 3 5 4 Y & h t t p : / / w w w . b i r d c o m p u t e r . c a / i n d e x . h t m l
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R o o t E n t r y F Axnk#
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1 T a b l e W o r d D o c u m e n t S u m m a r y I n f o r m a t i o n ( a
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D o c u m e n t S u m m a r y I n f o r m a t i o n 8 i
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F Microsoft Word 97-2003 Document
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