`include "Raptor64_opcodes.v"
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`include "Raptor64_opcodes.v"
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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//=============================================================================
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//=============================================================================
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// __
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// __
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// \\__/ o\ (C) 2011,2012 Robert Finch
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// \\__/ o\ (C) 2011-2013 Robert Finch, Stratford
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@opencores.org
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// \/_// robfinch<remove>@opencores.org
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// ||
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// ||
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//
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//
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// Raptor64_BranchHistory.v
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// Raptor64_BranchHistory.v
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//
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//
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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//
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//
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//=============================================================================
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//=============================================================================
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//
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//
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module Raptor64_BranchHistory(rst, clk, advanceX, xIR, pc, xpc, takb, predict_taken);
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module Raptor64_BranchHistory(rst, clk, advanceX, xIR, pc, xpc, takb, predict_taken);
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input rst;
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input rst;
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input clk;
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input clk;
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input advanceX;
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input advanceX;
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input [41:0] xIR;
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input [31:0] xIR;
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input [63:0] pc;
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input [63:0] pc;
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input [63:0] xpc;
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input [63:0] xpc;
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input takb;
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input takb;
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output predict_taken;
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output predict_taken;
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integer n;
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integer n;
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reg [2:0] gbl_branch_hist;
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reg [2:0] gbl_branch_hist;
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reg [1:0] branch_history_table [255:0];
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reg [1:0] branch_history_table [255:0];
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// For simulation only, initialize the history table to zeros.
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// For simulation only, initialize the history table to zeros.
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// In the real world we don't care.
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// In the real world we don't care.
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initial begin
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initial begin
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for (n = 0; n < 256; n = n + 1)
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for (n = 0; n < 256; n = n + 1)
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branch_history_table[n] = 0;
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branch_history_table[n] = 0;
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end
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end
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wire [7:0] bht_wa = {xpc[5:0],gbl_branch_hist[2:1]}; // write address
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wire [7:0] bht_wa = {xpc[7:2],gbl_branch_hist[2:1]}; // write address
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wire [7:0] bht_ra1 = {xpc[5:0],gbl_branch_hist[2:1]}; // read address (EX stage)
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wire [7:0] bht_ra1 = {xpc[7:2],gbl_branch_hist[2:1]}; // read address (EX stage)
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wire [7:0] bht_ra2 = {pc[5:0],gbl_branch_hist[2:1]}; // read address (IF stage)
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wire [7:0] bht_ra2 = {pc[7:2],gbl_branch_hist[2:1]}; // read address (IF stage)
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wire [1:0] bht_xbits = branch_history_table[bht_ra1];
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wire [1:0] bht_xbits = branch_history_table[bht_ra1];
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wire [1:0] bht_ibits = branch_history_table[bht_ra2];
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wire [1:0] bht_ibits = branch_history_table[bht_ra2];
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assign predict_taken = bht_ibits==2'd0 || bht_ibits==2'd1;
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assign predict_taken = bht_ibits==2'd0 || bht_ibits==2'd1;
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wire [6:0] xOpcode = xIR[41:35];
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wire [6:0] xOpcode = xIR[31:25];
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wire isxBranchI = (xOpcode==`BEQI || xOpcode==`BNEI ||
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wire isxBranchI = (xOpcode==`BEQI || xOpcode==`BNEI ||
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xOpcode==`BLTI || xOpcode==`BLEI || xOpcode==`BGTI || xOpcode==`BGEI ||
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xOpcode==`BLTI || xOpcode==`BLEI || xOpcode==`BGTI || xOpcode==`BGEI ||
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xOpcode==`BLTUI || xOpcode==`BLEUI || xOpcode==`BGTUI || xOpcode==`BGEUI)
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xOpcode==`BLTUI || xOpcode==`BLEUI || xOpcode==`BGTUI || xOpcode==`BGEUI)
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;
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;
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wire isxBranch = isxBranchI || xOpcode==`TRAPcc || xOpcode==`TRAPcci || xOpcode==`BTRI || xOpcode==`BTRR;
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wire isxBranch = isxBranchI || xOpcode==`TRAPcc || xOpcode==`TRAPcci || xOpcode==`BTRI || xOpcode==`BTRR;
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// Two bit saturating counter
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// Two bit saturating counter
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reg [1:0] xbits_new;
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reg [1:0] xbits_new;
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always @(takb or bht_xbits)
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always @(takb or bht_xbits)
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if (takb) begin
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if (takb) begin
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if (bht_xbits != 2'd1)
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if (bht_xbits != 2'd1)
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xbits_new <= bht_xbits + 2'd1;
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xbits_new <= bht_xbits + 2'd1;
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else
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else
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xbits_new <= bht_xbits;
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xbits_new <= bht_xbits;
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end
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end
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else begin
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else begin
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if (bht_xbits != 2'd2)
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if (bht_xbits != 2'd2)
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xbits_new <= bht_xbits - 2'd1;
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xbits_new <= bht_xbits - 2'd1;
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else
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else
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xbits_new <= bht_xbits;
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xbits_new <= bht_xbits;
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end
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end
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always @(posedge clk)
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always @(posedge clk)
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if (rst)
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if (rst)
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gbl_branch_hist <= 3'b000;
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gbl_branch_hist <= 3'b000;
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else begin
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else begin
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if (advanceX) begin
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if (advanceX) begin
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if (isxBranch) begin
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if (isxBranch) begin
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gbl_branch_hist <= {gbl_branch_hist[1:0],takb};
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gbl_branch_hist <= {gbl_branch_hist[1:0],takb};
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branch_history_table[bht_wa] <= xbits_new;
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branch_history_table[bht_wa] <= xbits_new;
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end
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end
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end
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end
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end
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end
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endmodule
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endmodule
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