`include "Raptor64_opcodes.v"
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`include "Raptor64_opcodes.v"
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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//=============================================================================
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//=============================================================================
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// __
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// __
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// \\__/ o\ (C) 2011,2012 Robert Finch
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// \\__/ o\ (C) 2011,2012 Robert Finch
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@opencores.org
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// \/_// robfinch<remove>@opencores.org
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// ||
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// ||
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//
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//
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// Raptor64_SetOperandRegs.v
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// Raptor64_SetOperandRegs.v
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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//
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//
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// If a register field is not used by an instruction, then the register
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// If a register field is not used by an instruction, then the register
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// selected is forced to r0 for that field. This causes load stalls to be
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// selected is forced to r0 for that field. This causes load stalls to be
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// avoided, which would otherwise occur.
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// avoided, which would otherwise occur.
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//=============================================================================
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//=============================================================================
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module Raptor64_SetOperandRegs(rst, clk, advanceI, advanceR, advanceX, b, AXC, insn, xIR, dRa, dRb, dRc);
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module Raptor64_SetOperandRegs(rst, clk, advanceI, advanceR, advanceX, b, AXC, insn, xIR, dRa, dRb, dRc);
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input rst;
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input rst;
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input clk;
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input clk;
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input advanceI;
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input advanceI;
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input advanceR;
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input advanceR;
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input advanceX;
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input advanceX;
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input [63:0] b;
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input [63:0] b;
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input [3:0] AXC;
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input [3:0] AXC;
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input [31:0] insn;
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input [31:0] insn;
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input [31:0] xIR;
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input [31:0] xIR;
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output [8:0] dRa;
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output [8:0] dRa;
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reg [8:0] dRa;
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reg [8:0] dRa;
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output [8:0] dRb;
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output [8:0] dRb;
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reg [8:0] dRb;
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reg [8:0] dRb;
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output [8:0] dRc;
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output [8:0] dRc;
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reg [8:0] dRc;
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reg [8:0] dRc;
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wire [6:0] iOpcode = insn[31:25];
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wire [6:0] iOpcode = insn[31:25];
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wire [6:0] xOpcode = xIR[31:25];
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wire [6:0] xOpcode = xIR[31:25];
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wire [5:0] xFunc = xIR[5:0];
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wire [5:0] xFunc = xIR[5:0];
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wire [6:0] iFunc7 = insn[6:0];
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wire [6:0] iFunc7 = insn[6:0];
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always @(posedge clk)
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always @(posedge clk)
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if (rst) begin
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if (rst) begin
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dRa <= 9'd0;
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dRa <= 9'd0;
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dRb <= 9'd0;
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dRb <= 9'd0;
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dRc <= 9'd0;
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dRc <= 9'd0;
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end
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end
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else begin
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else begin
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if (advanceI) begin
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if (advanceI) begin
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// Default settings, to be overridden
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// Default settings, to be overridden
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dRa <= {AXC,insn[24:20]};
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dRa <= {AXC,insn[24:20]};
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dRb <= {AXC,insn[19:15]};
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dRb <= {AXC,insn[19:15]};
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dRc <= {AXC,insn[14:10]};
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dRc <= {AXC,insn[14:10]};
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casex(iOpcode)
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casex(iOpcode)
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`MISC:
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`MISC:
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case(iFunc7)
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case(iFunc7)
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`IRET: begin
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`IRET: begin
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dRa <= {AXC,5'd25};
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dRa <= {AXC,5'd25};
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dRb <= 9'd0;
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dRb <= 9'd0;
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dRc <= 9'd0;
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dRc <= 9'd0;
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end
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end
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`ERET: begin
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`ERET: begin
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dRa <= {AXC,5'd24};
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dRa <= {AXC,5'd24};
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dRb <= 9'd0;
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dRb <= 9'd0;
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dRc <= 9'd0;
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dRc <= 9'd0;
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end
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end
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default:
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default:
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begin
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begin
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dRa <= 9'd0;
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dRa <= 9'd0;
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dRb <= 9'd0;
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dRb <= 9'd0;
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dRc <= 9'd0;
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dRc <= 9'd0;
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end
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end
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endcase
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endcase
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`R: begin dRb <= 9'd0; dRc <= 9'd0; end
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`RR: dRc <= 9'd0;
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`TRAPcc: dRc <= 9'd0;
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`TRAPcci: begin dRb <= 9'd0; dRc <= 9'd0; end
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`CALL,`JMP,`NOPI:
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`CALL,`JMP,`NOPI:
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begin
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begin
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dRa <= 9'd0;
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dRa <= 9'd0;
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dRb <= 9'd0;
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dRb <= 9'd0;
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dRc <= 9'd0;
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dRc <= 9'd0;
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end
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end
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`RET: begin
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`RET: begin
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dRa <= {AXC,5'd30};
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dRa <= {AXC,5'd30};
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dRb <= {AXC,5'd31};
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dRb <= {AXC,5'd31};
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dRc <= 9'd0;
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dRc <= 9'd0;
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end
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end
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`LB,`LBU,`LH,`LHU,`LC,`LCU,`LW,`LP,`LSH,`LSW,`LF,`LFD,`LFP,`LFDP,`LWR:
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begin
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dRb <= 9'd0;
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dRc <= 9'd0;
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end
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`SB,`SC,`SH,`SW,`SP,`SSH,`SSW,`SF,`SFD,`SFP,`SFDP,`SWC:
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dRc <= 9'd0;
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`INB,`INBU,`INCH,`INCU,`INH,`INHU,`INW:
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begin
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dRb <= 9'd0;
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dRc <= 9'd0;
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end
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`OUTB,`OUTC,`OUTH,`OUTW:
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dRc <= 9'd0;
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`BLTI,`BLEI,`BGTI,`BGEI,
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`BLTI,`BLEI,`BGTI,`BGEI,
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`BLTUI,`BLEUI,`BGTUI,`BGEUI,
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`BLTUI,`BLEUI,`BGTUI,`BGEUI,
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`BEQI,`BNEI:
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`BEQI,`BNEI:
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begin
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begin
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dRb <= 9'd0;
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dRb <= 9'd0;
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dRc <= 9'd0;
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dRc <= 9'd0;
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end
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end
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`BTRI: dRc <= 9'd0;
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`SLTI,`SLEI,`SGTI,`SGEI,
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`SLTI,`SLEI,`SGTI,`SGEI,
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`SLTUI,`SLEUI,`SGTUI,`SGEUI,
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`SLTUI,`SLEUI,`SGTUI,`SGEUI,
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`SEQI,`SNEI:
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`SEQI,`SNEI:
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begin
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begin
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dRb <= 9'd0;
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dRb <= 9'd0;
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dRc <= 9'd0;
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dRc <= 9'd0;
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end
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end
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`SETLO: dRa <= {AXC,insn[26:22]};
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`ADDI,`ADDUI,`SUBI,`SUBUI,`CMPI,`CMPUI,
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`SETMID: dRa <= {AXC,insn[26:22]};
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`ANDI,`XORI,`ORI,`MULUI,`MULSI,`DIVUI,`DIVSI:
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`SETHI: dRa <= {AXC,insn[26:22]};
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begin
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dRb <= 9'd0;
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dRc <= 9'd0;
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end
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`JAL:
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begin
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dRb <= 9'd0;
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dRc <= 9'd0;
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end
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`SETLO: begin dRa <= {AXC,insn[26:22]}; dRb <= 9'd0; dRc <= 9'd0; end
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`SETMID: begin dRa <= {AXC,insn[26:22]}; dRb <= 9'd0; dRc <= 9'd0; end
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`SETHI: begin dRa <= {AXC,insn[26:22]}; dRb <= 9'd0; dRc <= 9'd0; end
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default: dRa <= {AXC,insn[24:20]};
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default: dRa <= {AXC,insn[24:20]};
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endcase
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endcase
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end
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end
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else if (advanceR) begin
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else if (advanceR) begin
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dRa <= 9'd0;
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dRa <= 9'd0;
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dRb <= 9'd0;
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dRb <= 9'd0;
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dRc <= 9'd0;
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dRc <= 9'd0;
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end
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end
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// no else here
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// no else here
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if (advanceX) begin
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if (advanceX) begin
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if (xOpcode==`R) begin
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if (xOpcode==`R) begin
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if (xFunc==`EXEC) begin
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if (xFunc==`EXEC) begin
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dRa <= b[24:20];
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dRa <= b[24:20];
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dRb <= b[19:15];
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dRb <= b[19:15];
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dRc <= b[14:10];
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dRc <= b[14:10];
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end
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end
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end
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end
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end
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end
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end
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end
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endmodule
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endmodule
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