`include "Raptor64_opcodes.v"
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`include "Raptor64_opcodes.v"
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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//=============================================================================
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//=============================================================================
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// __
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// __
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// \\__/ o\ (C) 2011,2012 Robert Finch
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// \\__/ o\ (C) 2011,2012 Robert Finch
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@opencores.org
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// \/_// robfinch<remove>@opencores.org
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// ||
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// ||
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//
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//
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// Raptor64_TLB.v
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// Raptor64_TLB.v
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//
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//
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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//
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//
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// TLB
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// TLB
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// The TLB contains 64 entries, that are 8 way set associative.
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// The TLB contains 64 entries, that are 8 way set associative.
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// The TLB is dual ported and shared between the instruction and data streams.
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// The TLB is dual ported and shared between the instruction and data streams.
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//
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//
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//=============================================================================
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//=============================================================================
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//
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//
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`define TLBMissPage 52'hFFFF_FFFF_FFFF_F
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`define TLBMissPage 52'hFFFF_FFFF_FFFF_F
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module Raptor64_TLB(rst, clk, pc, ea, ppc, pea,
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module Raptor64_TLB(rst, clk, pc, ea, ppc, pea,
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m1IsStore, ASID,
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m1IsStore, ASID,
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wTlbp, wTlbrd, wTlbwr, wTlbwi,
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wTlbp, wTlbrd, wTlbwr, wTlbwi,
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xTlbrd, xTlbwr, xTlbwi,
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xTlbrd, xTlbwr, xTlbwi,
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wr, wregno, dati, xregno, dato, ITLBMiss, DTLBMiss, HTLBVirtPage);
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wr, wregno, dati, xregno, dato, ITLBMiss, DTLBMiss, HTLBVirtPage);
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input rst;
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input rst;
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input clk;
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input clk;
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input [63:0] pc;
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input [63:0] pc;
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input [63:0] ea;
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input [63:0] ea;
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output [63:0] ppc;
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output [63:0] ppc;
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output [63:0] pea;
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output [63:0] pea;
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input m1IsStore;
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input m1IsStore;
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input [7:0] ASID;
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input [7:0] ASID;
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input wTlbp;
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input wTlbp;
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input wTlbrd;
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input wTlbrd;
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input wTlbwr;
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input wTlbwr;
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input wTlbwi;
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input wTlbwi;
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input xTlbrd;
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input xTlbrd;
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input xTlbwr;
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input xTlbwr;
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input xTlbwi;
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input xTlbwi;
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input wr;
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input wr;
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input [5:0] wregno;
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input [5:0] wregno;
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input [63:0] dati;
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input [63:0] dati;
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input [5:0] xregno;
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input [5:0] xregno;
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output [63:0] dato;
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output [63:0] dato;
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reg [63:0] dato;
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reg [63:0] dato;
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output ITLBMiss;
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output ITLBMiss;
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output DTLBMiss;
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output DTLBMiss;
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output [63:0] HTLBVirtPage;
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output [63:0] HTLBVirtPage;
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integer n;
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integer n;
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// Holding registers
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// Holding registers
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// These allow the TLB to updated in a single cycle
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// These allow the TLB to updated in a single cycle
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reg [24:13] HTLBPageMask;
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reg [24:13] HTLBPageMask;
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reg [63:13] HTLBVirtPage;
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reg [63:13] HTLBVirtPage;
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reg [63:13] HTLBPhysPage0;
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reg [63:13] HTLBPhysPage0;
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reg [63:13] HTLBPhysPage1;
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reg [63:13] HTLBPhysPage1;
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reg [7:0] HTLBASID;
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reg [7:0] HTLBASID;
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reg HTLBG;
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reg HTLBG;
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reg HTLBD;
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reg HTLBD;
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reg HTLBValid;
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reg HTLBValid;
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reg [5:0] i;
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reg [5:0] i;
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reg [63:0] Index;
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reg [63:0] Index;
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reg [2:0] Random;
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reg [2:0] Random;
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reg [2:0] Wired;
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reg [2:0] Wired;
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reg [15:0] IMatch,DMatch;
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reg [15:0] IMatch,DMatch;
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reg [3:0] m;
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reg [3:0] m;
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reg [3:0] q;
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reg [3:0] q;
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reg [24:13] TLBPageMask [63:0];
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reg [24:13] TLBPageMask [63:0];
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reg [63:13] TLBVirtPage [63:0];
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reg [63:13] TLBVirtPage [63:0];
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reg [63:13] TLBPhysPage0 [63:0];
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reg [63:13] TLBPhysPage0 [63:0];
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reg [63:13] TLBPhysPage1 [63:0];
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reg [63:13] TLBPhysPage1 [63:0];
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reg [63:0] TLBG;
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reg [63:0] TLBG;
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reg [63:0] TLBD;
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reg [63:0] TLBD;
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reg [7:0] TLBASID [63:0];
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reg [7:0] TLBASID [63:0];
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reg [63:0] TLBValid;
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reg [63:0] TLBValid;
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initial begin
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initial begin
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for (n = 0; n < 64; n = n + 1)
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for (n = 0; n < 64; n = n + 1)
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begin
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begin
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TLBPageMask[n] = 0;
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TLBPageMask[n] = 0;
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TLBVirtPage[n] = 0;
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TLBVirtPage[n] = 0;
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TLBPhysPage0[n] = 0;
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TLBPhysPage0[n] = 0;
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TLBPhysPage1[n] = 0;
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TLBPhysPage1[n] = 0;
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TLBG[n] = 0;
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TLBG[n] = 0;
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TLBASID[n] = 0;
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TLBASID[n] = 0;
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TLBValid[n] = 0;
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TLBValid[n] = 0;
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end
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end
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end
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end
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wire unmappedArea = pc[63:52]==12'hFFD || pc[63:52]==12'hFFE || pc[63:52]==12'hFFF;
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wire unmappedArea = pc[63:52]==12'hFFD || pc[63:52]==12'hFFE || pc[63:52]==12'hFFF;
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wire unmappedDataArea = ea[63:52]==12'hFFD || ea[63:52]==12'hFFE || ea[63:52]==12'hFFF;
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wire unmappedDataArea = ea[63:52]==12'hFFD || ea[63:52]==12'hFFE || ea[63:52]==12'hFFF || ea[63:52]==12'h000;
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wire m1UnmappedDataArea = pea[63:13]>=12'hFFD;
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wire m1UnmappedDataArea = pea[63:52]==12'hFFD || pea[63:52]==12'hFFE || pea[63:52]==12'hFFF || pea[63:52]==12'h000;
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always @(posedge clk)
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always @(posedge clk)
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if (rst) begin
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if (rst) begin
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Random <= 4'hF;
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Random <= 3'h7;
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Wired <= 4'd0;
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Wired <= 3'd0;
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end
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end
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else begin
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else begin
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if (Random==Wired)
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if (Random==Wired)
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Random <= 3'd7;
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Random <= 3'd7;
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else
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else
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Random <= Random - 3'd1;
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Random <= Random - 3'd1;
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if (xTlbrd|xTlbwi)
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if (xTlbrd|xTlbwi)
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i <= {Index[5:3],HTLBVirtPage[15:13]};
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i <= {Index[5:3],HTLBVirtPage[15:13]};
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if (xTlbwr)
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if (xTlbwr)
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i <= {Random,HTLBVirtPage[15:13]};
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i <= {Random,HTLBVirtPage[15:13]};
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if (wr) begin
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if (wr) begin
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case(wregno)
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case(wregno)
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`TLBWired: Wired <= dati[2:0];
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`TLBWired: Wired <= dati[2:0];
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`TLBIndex: Index <= dati[5:0];
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`TLBIndex: Index <= dati[5:0];
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`TLBRandom: Random <= dati[2:0];
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`TLBRandom: Random <= dati[2:0];
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`TLBPageMask: HTLBPageMask <= {dati[63:13],13'd0};
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`TLBPageMask: HTLBPageMask <= dati[63:13];
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`TLBVirtPage: HTLBVirtPage <= {dati[63:13],13'd0};
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`TLBVirtPage: HTLBVirtPage <= dati[63:13];
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`TLBPhysPage0: HTLBPhysPage0 <= {dati[63:13],13'd0};
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`TLBPhysPage0: HTLBPhysPage0 <= dati[63:13];
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`TLBPhysPage1: HTLBPhysPage1 <= {dati[63:13],13'd0};
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`TLBPhysPage1: HTLBPhysPage1 <= dati[63:13];
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`TLBASID: begin
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`TLBASID: begin
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HTLBValid <= dati[0];
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HTLBValid <= dati[0];
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HTLBD <= dati[1];
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HTLBD <= dati[1];
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HTLBG <= dati[2];
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HTLBG <= dati[2];
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HTLBASID <= dati[15:8];
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HTLBASID <= dati[15:8];
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end
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end
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endcase
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endcase
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end
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end
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if (wTlbp)
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if (wTlbp)
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begin
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begin
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Index[63] <= ~|DMatch;
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Index[63] <= ~|DMatch;
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end
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end
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if (wTlbrd) begin
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if (wTlbrd) begin
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HTLBPageMask <= TLBPageMask[i];
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HTLBPageMask <= TLBPageMask[i];
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HTLBVirtPage <= TLBVirtPage[i];
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HTLBVirtPage <= TLBVirtPage[i];
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HTLBPhysPage0 <= TLBPhysPage0[i];
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HTLBPhysPage0 <= TLBPhysPage0[i];
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HTLBPhysPage1 <= TLBPhysPage1[i];
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HTLBPhysPage1 <= TLBPhysPage1[i];
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HTLBASID <= TLBASID[i];
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HTLBASID <= TLBASID[i];
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HTLBG <= TLBG[i];
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HTLBG <= TLBG[i];
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HTLBD <= TLBD[i];
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HTLBD <= TLBD[i];
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HTLBValid <= TLBValid[i];
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HTLBValid <= TLBValid[i];
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end
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end
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if (wTlbwi) begin
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else if (wTlbwi) begin
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TLBVirtPage[i] <= HTLBVirtPage;
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TLBVirtPage[i] <= HTLBVirtPage;
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TLBPhysPage0[i] <= HTLBPhysPage0;
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TLBPhysPage0[i] <= HTLBPhysPage0;
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TLBPhysPage1[i] <= HTLBPhysPage1;
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TLBPhysPage1[i] <= HTLBPhysPage1;
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TLBASID[i] <= HTLBASID;
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TLBASID[i] <= HTLBASID;
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TLBG[i] <= HTLBG;
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TLBG[i] <= HTLBG;
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TLBD[i] <= HTLBD;
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TLBD[i] <= HTLBD;
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TLBValid[i] <= HTLBValid;
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TLBValid[i] <= HTLBValid;
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end
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end
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if (wTlbwr) begin
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else if (wTlbwr) begin
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TLBVirtPage[i] <= HTLBVirtPage;
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TLBVirtPage[i] <= HTLBVirtPage;
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TLBPhysPage0[i] <= HTLBPhysPage0;
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TLBPhysPage0[i] <= HTLBPhysPage0;
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TLBPhysPage1[i] <= HTLBPhysPage1;
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TLBPhysPage1[i] <= HTLBPhysPage1;
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TLBASID[i] <= HTLBASID;
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TLBASID[i] <= HTLBASID;
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TLBG[i] <= HTLBG;
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TLBG[i] <= HTLBG;
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TLBD[i] <= HTLBD;
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TLBD[i] <= HTLBD;
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TLBValid[i] <= HTLBValid;
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TLBValid[i] <= HTLBValid;
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end
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end
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// Set the dirty bit on a store
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// Set the dirty bit on a store
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if (m1IsStore)
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if (m1IsStore)
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if (!m1UnmappedDataArea & !q[3])
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if (!m1UnmappedDataArea & !q[3])
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TLBD[{q[2:0],pea[15:13]}] <= 1'b1;
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TLBD[{q[2:0],pea[15:13]}] <= 1'b1;
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end
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end
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always @*
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always @*
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case(xregno)
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case(xregno)
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`TLBWired: dato = Wired;
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`TLBWired: dato = Wired;
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`TLBIndex: dato = Index;
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`TLBIndex: dato = Index;
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`TLBRandom: dato = Random;
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`TLBRandom: dato = Random;
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`TLBPhysPage0: dato = {HTLBPhysPage0,13'd0};
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`TLBPhysPage0: dato = {HTLBPhysPage0,13'd0};
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`TLBPhysPage1: dato = {HTLBPhysPage1,13'd0};
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`TLBPhysPage1: dato = {HTLBPhysPage1,13'd0};
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`TLBVirtPage: dato = {HTLBVirtPage,13'd0};
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`TLBVirtPage: dato = {HTLBVirtPage,13'd0};
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`TLBPageMask: dato = {HTLBPageMask,13'd0};
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`TLBPageMask: dato = {HTLBPageMask,13'd0};
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`TLBASID: begin
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`TLBASID: begin
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dato = 64'd0;
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dato = 64'd0;
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dato[0] = HTLBValid;
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dato[0] = HTLBValid;
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dato[1] = HTLBD;
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dato[1] = HTLBD;
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dato[2] = HTLBG;
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dato[2] = HTLBG;
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dato[15:8] = HTLBASID;
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dato[15:8] = HTLBASID;
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end
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end
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default: dato = 64'd0;
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default: dato = 64'd0;
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endcase
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endcase
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|
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always @*
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always @*
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for (n = 0; n < 8; n = n + 1)
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for (n = 0; n < 8; n = n + 1)
|
IMatch[n] = ((pc[63:13]|TLBPageMask[{n[2:0],pc[15:13]}])==(TLBVirtPage[{n[2:0],pc[15:13]}]|TLBPageMask[{n[2:0],pc[15:13]}])) &&
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IMatch[n] = ((pc[63:13]|TLBPageMask[{n[2:0],pc[15:13]}])==(TLBVirtPage[{n[2:0],pc[15:13]}]|TLBPageMask[{n[2:0],pc[15:13]}])) &&
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((TLBASID[{n,pc[15:13]}]==ASID) || TLBG[{n,pc[15:13]}]) &&
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((TLBASID[{n,pc[15:13]}]==ASID) || TLBG[{n,pc[15:13]}]) &&
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TLBValid[{n,pc[15:13]}];
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TLBValid[{n,pc[15:13]}];
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always @(IMatch)
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always @(IMatch)
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if (IMatch[0]) m <= 4'd0;
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if (IMatch[0]) m <= 4'd0;
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else if (IMatch[1]) m <= 4'd1;
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else if (IMatch[1]) m <= 4'd1;
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else if (IMatch[2]) m <= 4'd2;
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else if (IMatch[2]) m <= 4'd2;
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else if (IMatch[3]) m <= 4'd3;
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else if (IMatch[3]) m <= 4'd3;
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else if (IMatch[4]) m <= 4'd4;
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else if (IMatch[4]) m <= 4'd4;
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else if (IMatch[5]) m <= 4'd5;
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else if (IMatch[5]) m <= 4'd5;
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else if (IMatch[6]) m <= 4'd6;
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else if (IMatch[6]) m <= 4'd6;
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else if (IMatch[7]) m <= 4'd7;
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else if (IMatch[7]) m <= 4'd7;
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else m <= 4'd15;
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else m <= 4'd15;
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|
|
wire ioddpage = |({TLBPageMask[{m[2:0],pc[15:13]}]+19'd1,13'd0}&pc);
|
wire ioddpage = |({TLBPageMask[{m[2:0],pc[15:13]}]+19'd1,13'd0}&pc);
|
wire [63:13] IPFN = ioddpage ? TLBPhysPage1[{m[2:0],pc[15:13]}] : TLBPhysPage0[{m[2:0],pc[15:13]}];
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wire [63:13] IPFN = ioddpage ? TLBPhysPage1[{m[2:0],pc[15:13]}] : TLBPhysPage0[{m[2:0],pc[15:13]}];
|
|
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assign ITLBMiss = !unmappedArea & m[3];
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assign ITLBMiss = !unmappedArea & m[3];
|
|
|
assign ppc[63:13] = unmappedArea ? pc[63:13] : m[3] ? `TLBMissPage: IPFN;
|
assign ppc[63:13] = unmappedArea ? pc[63:13] : m[3] ? `TLBMissPage: IPFN;
|
assign ppc[12:0] = pc[12:0];
|
assign ppc[12:0] = pc[12:0];
|
|
|
always @(ea)
|
always @(ea)
|
for (n = 0; n < 7; n = n + 1)
|
for (n = 0; n < 7; n = n + 1)
|
DMatch[n] = ((ea[63:13]|TLBPageMask[{n,ea[15:13]}])==(TLBVirtPage[{n,ea[15:13]}]|TLBPageMask[{n,ea[15:13]}])) &&
|
DMatch[n] = ((ea[63:13]|TLBPageMask[{n,ea[15:13]}])==(TLBVirtPage[{n,ea[15:13]}]|TLBPageMask[{n,ea[15:13]}])) &&
|
((TLBASID[{n,ea[15:13]}]==ASID) || TLBG[{n,ea[15:13]}]) &&
|
((TLBASID[{n,ea[15:13]}]==ASID) || TLBG[{n,ea[15:13]}]) &&
|
TLBValid[{n,ea[15:13]}];
|
TLBValid[{n,ea[15:13]}];
|
always @(DMatch)
|
always @(DMatch)
|
if (DMatch[0]) q <= 4'd0;
|
if (DMatch[0]) q <= 4'd0;
|
else if (DMatch[1]) q <= 4'd1;
|
else if (DMatch[1]) q <= 4'd1;
|
else if (DMatch[2]) q <= 4'd2;
|
else if (DMatch[2]) q <= 4'd2;
|
else if (DMatch[3]) q <= 4'd3;
|
else if (DMatch[3]) q <= 4'd3;
|
else if (DMatch[4]) q <= 4'd4;
|
else if (DMatch[4]) q <= 4'd4;
|
else if (DMatch[5]) q <= 4'd5;
|
else if (DMatch[5]) q <= 4'd5;
|
else if (DMatch[6]) q <= 4'd6;
|
else if (DMatch[6]) q <= 4'd6;
|
else if (DMatch[7]) q <= 4'd7;
|
else if (DMatch[7]) q <= 4'd7;
|
else q <= 4'd15;
|
else q <= 4'd15;
|
|
|
wire doddpage = |({TLBPageMask[{q[2:0],ea[15:13]}]+19'd1,13'd0}&ea);
|
wire doddpage = |({TLBPageMask[{q[2:0],ea[15:13]}]+19'd1,13'd0}&ea);
|
wire [63:13] DPFN = doddpage ? TLBPhysPage1[{q[2:0],ea[15:13]}] : TLBPhysPage0[{q[2:0],ea[15:13]}];
|
wire [63:13] DPFN = doddpage ? TLBPhysPage1[{q[2:0],ea[15:13]}] : TLBPhysPage0[{q[2:0],ea[15:13]}];
|
|
|
assign DTLBMiss = !unmappedDataArea & q[3];
|
assign DTLBMiss = !unmappedDataArea & q[3];
|
|
|
assign pea[63:13] = unmappedDataArea ? ea[63:13] : q[3] ? `TLBMissPage: DPFN;
|
assign pea[63:13] = unmappedDataArea ? ea[63:13] : q[3] ? `TLBMissPage: DPFN;
|
assign pea[12:0] = ea[12:0];
|
assign pea[12:0] = ea[12:0];
|
|
|
endmodule
|
endmodule
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|
|
|
|
