`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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//=============================================================================
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//=============================================================================
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// __
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// __
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// \\__/ o\ (C) 2011,2012 Robert Finch
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// \\__/ o\ (C) 2011,2012 Robert Finch
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@opencores.org
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// \/_// robfinch<remove>@opencores.org
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// ||
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// ||
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//
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//
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// Raptor64_regfile.v
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// Raptor64_regfile.v
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// - register file and bypass muxes
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// - register file and bypass muxes
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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//
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//
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//=============================================================================
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//=============================================================================
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module Raptor64_regfile(clk, advanceR, advanceW, dRa, dRb, dRc, dpc,
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module Raptor64_regfile(clk, advanceR, advanceW, wIRvalid, dRa, dRb, dRc, dpc,
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xRt, m1Rt, m2Rt, wRt, tRt, xData, m1Data, m2Data, wData, tData, nxt_a, nxt_b, nxt_c);
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xRt, m1Rt, m2Rt, wRt, tRt, xData, m1Data, m2Data, wData, tData, nxt_a, nxt_b, nxt_c);
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input clk;
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input clk;
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input advanceR;
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input advanceR;
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input advanceW;
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input advanceW;
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input wIRvalid;
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input [8:0] dRa;
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input [8:0] dRa;
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input [8:0] dRb;
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input [8:0] dRb;
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input [8:0] dRc;
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input [8:0] dRc;
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input [63:0] dpc;
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input [63:0] dpc;
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input [8:0] xRt;
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input [8:0] xRt;
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input [8:0] m1Rt;
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input [8:0] m1Rt;
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input [8:0] m2Rt;
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input [8:0] m2Rt;
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input [8:0] wRt;
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input [8:0] wRt;
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input [8:0] tRt;
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input [8:0] tRt;
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input [63:0] xData;
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input [63:0] xData;
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input [63:0] m1Data;
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input [63:0] m1Data;
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input [63:0] m2Data;
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input [63:0] m2Data;
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input [63:0] wData;
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input [63:0] wData;
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input [63:0] tData;
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input [63:0] tData;
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output [63:0] nxt_a;
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output [63:0] nxt_a;
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output [63:0] nxt_b;
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output [63:0] nxt_b;
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output [63:0] nxt_c;
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output [63:0] nxt_c;
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wire [63:0] rfoa, rfob, rfoc;
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wire [63:0] rfoa, rfob, rfoc;
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syncRam512x64_1rw3r u1
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syncRam512x64_1rw3r u1
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(
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(
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.wrst(1'b0),
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.wrst(1'b0),
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.wclk(clk),
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.wclk(clk),
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.wce(advanceW),
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.wce(advanceW),
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.we(1'b1),
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.we(wIRvalid),
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.wadr(wRt),
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.wadr(wRt),
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.i(wData),
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.i(wData),
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.wo(),
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.wo(),
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.rrsta(1'b0),
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.rrsta(1'b0),
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.rclka(~clk),
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.rclka(~clk),
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.rcea(advanceR),
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.rcea(advanceR),
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.radra(dRa),
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.radra(dRa),
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.roa(rfoa),
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.roa(rfoa),
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.rrstb(1'b0),
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.rrstb(1'b0),
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.rclkb(~clk),
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.rclkb(~clk),
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.rceb(advanceR),
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.rceb(advanceR),
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.radrb(dRb),
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.radrb(dRb),
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.rob(rfob),
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.rob(rfob),
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.rrstc(1'b0),
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.rrstc(1'b0),
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.rclkc(~clk),
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.rclkc(~clk),
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.rcec(advanceR),
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.rcec(advanceR),
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.radrc(dRc),
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.radrc(dRc),
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.roc(rfoc)
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.roc(rfoc)
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);
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);
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reg [63:0] nxt_a;
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reg [63:0] nxt_a;
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always @(dRa or xData or m1Data or m2Data or wData or tData or rfoa or dpc or xRt or m1Rt or m2Rt or wRt or tRt)
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always @(dRa or xData or m1Data or m2Data or wData or tData or rfoa or dpc or xRt or m1Rt or m2Rt or wRt or tRt)
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casex(dRa)
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casex(dRa)
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9'bxxxx00000: nxt_a <= 64'd0;
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9'bxxxx00000: nxt_a <= 64'd0;
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9'bxxxx11101: nxt_a <= dpc;
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9'bxxxx11101: nxt_a <= dpc;
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xRt: nxt_a <= xData;
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xRt: nxt_a <= xData;
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m1Rt: nxt_a <= m1Data;
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m1Rt: nxt_a <= m1Data;
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m2Rt: nxt_a <= m2Data;
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m2Rt: nxt_a <= m2Data;
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wRt: nxt_a <= wData;
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wRt: nxt_a <= wData;
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tRt: nxt_a <= tData;
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tRt: nxt_a <= tData;
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default: nxt_a <= rfoa;
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default: nxt_a <= rfoa;
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endcase
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endcase
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reg [63:0] nxt_b;
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reg [63:0] nxt_b;
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always @(dRb or xData or m1Data or m2Data or wData or tData or rfob or dpc or xRt or m1Rt or m2Rt or wRt or tRt)
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always @(dRb or xData or m1Data or m2Data or wData or tData or rfob or dpc or xRt or m1Rt or m2Rt or wRt or tRt)
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casex(dRb)
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casex(dRb)
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9'bxxxx00000: nxt_b <= 64'd0;
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9'bxxxx00000: nxt_b <= 64'd0;
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9'bxxxx11101: nxt_b <= dpc;
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9'bxxxx11101: nxt_b <= dpc;
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xRt: nxt_b <= xData;
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xRt: nxt_b <= xData;
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m1Rt: nxt_b <= m1Data;
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m1Rt: nxt_b <= m1Data;
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m2Rt: nxt_b <= m2Data;
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m2Rt: nxt_b <= m2Data;
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wRt: nxt_b <= wData;
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wRt: nxt_b <= wData;
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tRt: nxt_b <= tData;
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tRt: nxt_b <= tData;
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default: nxt_b <= rfob;
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default: nxt_b <= rfob;
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endcase
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endcase
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reg [63:0] nxt_c;
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reg [63:0] nxt_c;
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always @(dRc or xData or m1Data or m2Data or wData or tData or rfoc or dpc or xRt or m1Rt or m2Rt or wRt or tRt)
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always @(dRc or xData or m1Data or m2Data or wData or tData or rfoc or dpc or xRt or m1Rt or m2Rt or wRt or tRt)
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casex(dRc)
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casex(dRc)
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9'bxxxx00000: nxt_c <= 64'd0;
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9'bxxxx00000: nxt_c <= 64'd0;
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9'bxxxx11101: nxt_c <= dpc;
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9'bxxxx11101: nxt_c <= dpc;
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xRt: nxt_c <= xData;
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xRt: nxt_c <= xData;
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m1Rt: nxt_c <= m1Data;
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m1Rt: nxt_c <= m1Data;
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m2Rt: nxt_c <= m2Data;
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m2Rt: nxt_c <= m2Data;
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wRt: nxt_c <= wData;
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wRt: nxt_c <= wData;
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tRt: nxt_c <= tData;
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tRt: nxt_c <= tData;
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default: nxt_c <= rfoc;
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default: nxt_c <= rfoc;
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endcase
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endcase
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endmodule
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endmodule
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