// ============================================================================
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// ============================================================================
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// (C) 2012 Robert Finch
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// (C) 2012 Robert Finch
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// All Rights Reserved.
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// All Rights Reserved.
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// robfinch<remove>@opencores.org
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// robfinch<remove>@opencores.org
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//
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//
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// Raptor64.v
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// Raptor64.v
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// - 64 bit CPU
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// - 64 bit CPU
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// ============================================================================
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// ============================================================================
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//
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//
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//`define RAS_PREDICTION 1
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`define ADDRESS_RESERVATION 1
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`define RAS_PREDICTION 1
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//`define BTB 1
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//`define BTB 1
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//`define TLB 1
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//`define TLB 1
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//`define BRANCH_PREDICTION_SIMPLE 1
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//`define BRANCH_PREDICTION_SIMPLE 1
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`define RESET_VECTOR 64'hFFFF_FFFF_FFFF_FFF0
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`define RESET_VECTOR 64'hFFFF_FFFF_FFFF_FFF0
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`define NMI_VECTOR 64'hFFFF_FFFF_FFFF_FFE0
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`define NMI_VECTOR 64'hFFFF_FFFF_FFFF_FFE0
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`define IRQ_VECTOR 64'hFFFF_FFFF_FFFF_FFD0
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`define IRQ_VECTOR 64'hFFFF_FFFF_FFFF_FFD0
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`define TRAP_VECTOR 64'h0000_0000_0000_0000
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`define TRAP_VECTOR 64'h0000_0000_0000_0000
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`define TLBMissPage 52'hFFFF_FFFF_FFFF_F
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`define TLBMissPage 52'hFFFF_FFFF_FFFF_F
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`define ITLB_MissHandler 64'hFFFF_FFFF_FFFF_FFC0
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`define ITLB_MissHandler 64'hFFFF_FFFF_FFFF_FFC0
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`define DTLB_MissHandler 64'hFFFF_FFFF_FFFF_FFB0
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`define DTLB_MissHandler 64'hFFFF_FFFF_FFFF_FFB0
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|
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`define GEN_TRAP_OFFSET 13'h0200
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`define GEN_TRAP_OFFSET 13'h0200
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`define DBZ_TRAP_OFFSET 13'h0050
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`define DBZ_TRAP_OFFSET 13'h0050
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`define OFL_TRAP_OFFSET 13'h0070
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`define OFL_TRAP_OFFSET 13'h0070
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`define PRIV_OFFSET 13'h0080
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`define PRIV_OFFSET 13'h0080
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`define EX_NON 8'd0
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`define EX_NON 8'd0
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`define EX_RST 8'd1
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`define EX_RST 8'd1
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`define EX_NMI 8'd2
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`define EX_NMI 8'd2
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`define EX_IRQ 8'd3
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`define EX_IRQ 8'd3
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`define EX_TRAP 8'd4
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`define EX_TRAP 8'd4
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`define EX_PRIV 8'd5 // priviledge violation
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`define EX_PRIV 8'd5 // priviledge violation
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`define EX_OFL 8'd16 // overflow
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`define EX_OFL 8'd16 // overflow
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`define EX_DBZ 8'd17 // divide by zero
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`define EX_DBZ 8'd17 // divide by zero
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`define EX_TLBI 8'd19 // TLB exception - ifetch
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`define EX_TLBI 8'd19 // TLB exception - ifetch
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`define EX_TLBD 8'd20 // TLB exception - data
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`define EX_TLBD 8'd20 // TLB exception - data
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`define EXCEPT_Int 5'd00
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`define EXCEPT_Int 5'd00
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`define EXCEPT_Mod 5'd01 // TLB modification
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`define EXCEPT_Mod 5'd01 // TLB modification
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`define EXCEPT_TLBL 5'd02 // TLB exception - load or ifetch
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`define EXCEPT_TLBL 5'd02 // TLB exception - load or ifetch
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`define EXCEPT_TLBS 5'd03 // TLB exception - store
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`define EXCEPT_TLBS 5'd03 // TLB exception - store
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`define EXCEPT_AdEL 5'd04 // Address error - load or ifetch
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`define EXCEPT_AdEL 5'd04 // Address error - load or ifetch
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`define EXCEPT_AdES 5'd05 // Address error - store
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`define EXCEPT_AdES 5'd05 // Address error - store
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`define EXCEPT_IBE 5'd06 // Bus Error - instruction fetch
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`define EXCEPT_IBE 5'd06 // Bus Error - instruction fetch
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`define EXCEPT_DBE 5'd07 // Bus Error - load or store
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`define EXCEPT_DBE 5'd07 // Bus Error - load or store
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`define EXCEPT_Sys 5'd08
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`define EXCEPT_Sys 5'd08
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`define EXCEPT_Bp 5'd09
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`define EXCEPT_Bp 5'd09
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`define EXCEPT_RI 5'd10 // reserved instruction
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`define EXCEPT_RI 5'd10 // reserved instruction
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`define EXCEPT_CpU 5'd11 // Coprocessor unusable
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`define EXCEPT_CpU 5'd11 // Coprocessor unusable
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`define EXCEPT_Ov 5'd12 // Integer Overflow
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`define EXCEPT_Ov 5'd12 // Integer Overflow
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`define EXCEPT_Tr 5'd13 // Trap exception
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`define EXCEPT_Tr 5'd13 // Trap exception
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// 14-22 Reserved
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// 14-22 Reserved
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`define EXCEPT_WATCH 5'd23
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`define EXCEPT_WATCH 5'd23
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`define EXCEPT_MCheck 5'd24 // Machine check
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`define EXCEPT_MCheck 5'd24 // Machine check
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// 25-31 Reserved
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// 25-31 Reserved
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`define MISC 7'd0
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`define MISC 7'd0
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`define BRK 7'd0
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`define BRK 7'd0
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`define IRQ 7'd1
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`define IRQ 7'd1
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`define ICACHE_ON 7'd10
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`define ICACHE_ON 7'd10
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`define ICACHE_OFF 7'd11
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`define ICACHE_OFF 7'd11
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`define DCACHE_ON 7'd12
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`define DCACHE_OFF 7'd13
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`define FIP 7'd20
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`define FIP 7'd20
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`define IRET 7'd32
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`define IRET 7'd32
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`define ERET 7'd33
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`define ERET 7'd33
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`define WAIT 7'd40
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`define WAIT 7'd40
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`define TLBP 7'd49
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`define TLBP 7'd49
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`define TLBR 7'd50
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`define TLBR 7'd50
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`define TLBWI 7'd51
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`define TLBWI 7'd51
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`define TLBWR 7'd52
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`define TLBWR 7'd52
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`define CLI 7'd64
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`define CLI 7'd64
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`define SEI 7'd65
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`define SEI 7'd65
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`define R 7'd1
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`define R 7'd1
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`define COM 7'd4
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`define COM 7'd4
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`define NOT 7'd5
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`define NOT 7'd5
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`define NEG 7'd6
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`define NEG 7'd6
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`define ABS 7'd7
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`define ABS 7'd7
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`define MOV 7'd9
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`define SWAP 7'd13
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`define SWAP 7'd13
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`define CTLZ 7'd16
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`define CTLZ 7'd16
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`define CTLO 7'd17
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`define CTLO 7'd17
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`define CTPOP 7'd18
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`define CTPOP 7'd18
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`define SEXT8 7'd19
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`define SEXT8 7'd19
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`define SEXT16 7'd20
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`define SEXT16 7'd20
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`define SEXT32 7'd21
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`define SEXT32 7'd21
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`define SQRT 7'd24
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`define SQRT 7'd24
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`define REDOR 7'd30
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`define REDOR 7'd30
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`define REDAND 7'd31
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`define REDAND 7'd31
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`define MFSPR 7'd40
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`define MFSPR 7'd40
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`define MTSPR 7'd41
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`define MTSPR 7'd41
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`define TLBIndex 6'd01
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`define TLBIndex 6'd01
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`define TLBRandom 6'd02
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`define TLBRandom 6'd02
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`define PageTableAddr 6'd04
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`define PageTableAddr 6'd04
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`define BadVAddr 6'd08
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`define BadVAddr 6'd08
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`define TLBPhysPage0 6'd10
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`define TLBPhysPage0 6'd10
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`define TLBPhysPage1 6'd11
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`define TLBPhysPage1 6'd11
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`define TLBVirtPage 6'd12
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`define TLBVirtPage 6'd12
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`define TLBPageMask 6'd13
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`define TLBPageMask 6'd13
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`define TLBASID 6'd14
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`define TLBASID 6'd14
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`define ASID 6'd15
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`define ASID 6'd15
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`define Wired 6'd16
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`define Wired 6'd16
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`define EP0 6'd17
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`define EP0 6'd17
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`define EP1 6'd18
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`define EP1 6'd18
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`define EP2 6'd19
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`define EP2 6'd19
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`define EP3 6'd20
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`define EP3 6'd20
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`define AXC 6'd21
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`define AXC 6'd21
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`define Tick 6'd22
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`define Tick 6'd22
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`define EPC 6'd23
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`define EPC 6'd23
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`define CauseCode 6'd24
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`define CauseCode 6'd24
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`define TBA 6'd25
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`define TBA 6'd25
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`define NON_ICACHE_SEG 6'd26
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`define NON_ICACHE_SEG 6'd26
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`define FPCR 6'd32
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`define IPC 6'd33
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`define OMG 7'd50
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`define OMG 7'd50
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`define CMG 7'd51
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`define CMG 7'd51
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`define OMGI 7'd52
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`define OMGI 7'd52
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`define CMGI 7'd53
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`define CMGI 7'd53
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`define EXEC 7'd58
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`define EXEC 7'd58
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`define MYST 7'd59
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`define RR 7'd2
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`define RR 7'd2
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`define ADD 7'd2
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`define ADD 7'd2
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`define ADDU 7'd3
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`define ADDU 7'd3
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`define SUB 7'd4
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`define SUB 7'd4
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`define SUBU 7'd5
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`define SUBU 7'd5
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`define CMP 7'd6
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`define CMP 7'd6
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`define CMPU 7'd7
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`define CMPU 7'd7
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`define AND 7'd8
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`define AND 7'd8
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`define OR 7'd9
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`define OR 7'd9
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`define XOR 7'd10
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`define XOR 7'd10
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`define ANDC 7'd11
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`define ANDC 7'd11
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`define NAND 7'd12
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`define NAND 7'd12
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`define NOR 7'd13
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`define NOR 7'd13
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`define XNOR 7'd14
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`define XNOR 7'd14
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`define ORC 7'd15
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`define ORC 7'd15
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`define MIN 7'd20
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`define MIN 7'd20
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`define MAX 7'd21
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`define MAX 7'd21
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`define MULU 7'd24
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`define MULU 7'd24
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`define MULS 7'd25
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`define MULS 7'd25
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`define DIVU 7'd26
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`define DIVU 7'd26
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`define DIVS 7'd27
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`define DIVS 7'd27
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`define MOD 7'd28
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`define MOD 7'd28
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`define MOVZ 7'd30
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`define MOVZ 7'd30
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`define MOVNZ 7'd31
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`define MOVNZ 7'd31
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`define SHL 7'd40
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`define SHL 7'd40
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`define SHRU 7'd41
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`define SHRU 7'd41
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`define ROL 7'd42
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`define ROL 7'd42
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`define ROR 7'd43
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`define ROR 7'd43
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`define SHR 7'd44
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`define SHR 7'd44
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`define ROLAM 7'd45
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`define ROLAM 7'd45
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`define NOP 7'd60
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`define NOP 7'd60
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`define SLT 7'd96
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`define SLT 7'd96
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`define SLE 7'd97
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`define SLE 7'd97
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`define SGT 7'd98
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`define SGT 7'd98
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`define SGE 7'd99
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`define SGE 7'd99
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`define SLTU 7'd100
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`define SLTU 7'd100
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`define SLEU 7'd101
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`define SLEU 7'd101
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`define SGTU 7'd102
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`define SGTU 7'd102
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`define SGEU 7'd103
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`define SGEU 7'd103
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`define SEQ 7'd104
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`define SEQ 7'd104
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`define SNE 7'd105
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`define SNE 7'd105
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`define BCD_ADD 7'd110
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`define BCD_ADD 7'd110
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`define BCD_SUB 7'd111
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`define BCD_SUB 7'd111
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`define SHFTI 7'd3
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`define SHFTI 7'd3
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`define SHLI 7'd0
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`define SHLI 7'd0
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`define SHRUI 7'd1
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`define SHRUI 7'd1
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`define ROLI 7'd2
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`define ROLI 7'd2
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`define SHRI 7'd3
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`define SHRI 7'd3
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`define RORI 7'd4
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`define RORI 7'd4
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`define ROLAMI 7'd5
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`define ROLAMI 7'd5
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`define BFINS 7'd8
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`define BFINS 7'd8
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`define BFSET 7'd9
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`define BFSET 7'd9
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`define BFCLR 7'd10
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`define BFCLR 7'd10
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`define BFCHG 7'd11
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`define BFCHG 7'd11
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`define ADDI 7'd4
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`define ADDI 7'd4
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`define ADDUI 7'd5
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`define ADDUI 7'd5
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`define SUBI 7'd6
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`define SUBI 7'd6
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`define SUBUI 7'd7
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`define SUBUI 7'd7
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`define CMPI 7'd8
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`define CMPI 7'd8
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`define CMPUI 7'd9
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`define CMPUI 7'd9
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`define ANDI 7'd10
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`define ANDI 7'd10
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`define ORI 7'd11
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`define ORI 7'd11
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`define XORI 7'd12
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`define XORI 7'd12
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`define MULUI 7'd13
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`define MULUI 7'd13
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`define MULSI 7'd14
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`define MULSI 7'd14
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`define DIVUI 7'd15
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`define DIVUI 7'd15
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`define DIVSI 7'd16
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`define DIVSI 7'd16
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`define TRAPcc 7'd17
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`define TRAPcc 7'd17
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`define TEQ 7'd0
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`define TEQ 7'd0
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`define TNE 7'd1
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`define TNE 7'd1
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`define TLT 7'd2
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`define TLT 7'd2
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`define TGE 7'd3
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`define TGE 7'd3
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`define TLE 7'd4
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`define TLE 7'd4
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`define TGT 7'd5
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`define TGT 7'd5
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`define TLTU 7'd6
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`define TLTU 7'd6
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`define TGEU 7'd7
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`define TGEU 7'd7
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`define TLEU 7'd8
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`define TLEU 7'd8
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`define TGTU 7'd9
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`define TGTU 7'd9
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`define TRAP 7'd10
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`define TRAP 7'd10
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`define TRN 7'd11
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`define TRN 7'd11
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`define TRAPcci 7'd18
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`define TRAPcci 7'd18
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`define TEQI 5'd0
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`define TEQI 5'd0
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`define TNEI 5'd1
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`define TNEI 5'd1
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`define TLTI 5'd2
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`define TLTI 5'd2
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`define TGEI 5'd3
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`define TGEI 5'd3
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`define TLEI 5'd4
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`define TLEI 5'd4
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`define TGTI 5'd5
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`define TGTI 5'd5
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`define TLTUI 5'd6
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`define TLTUI 5'd6
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`define TGEUI 5'd7
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`define TGEUI 5'd7
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`define TLEUI 5'd8
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`define TLEUI 5'd8
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`define TGTUI 5'd9
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`define TGTUI 5'd9
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`define TRAI 5'd10
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`define TRAI 5'd10
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`define TRNI 5'd11
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`define TRNI 5'd11
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// SETLO=20 to 23
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// SETLO=20 to 23
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`define SETLO 7'b00101xx
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`define SETLO 7'b00101xx
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`define CALL 7'd24
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`define CALL 7'd24
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`define JMP 7'd25
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`define JMP 7'd25
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`define JAL 7'd26
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`define JAL 7'd26
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`define RET 7'd27
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`define RET 7'd27
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// SETLO=28 to 31
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// SETLO=28 to 31
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`define SETHI 7'b00111xx
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`define SETHI 7'b00111xx
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`define LB 7'd32
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`define LB 7'd32
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`define LC 7'd33
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`define LC 7'd33
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`define LH 7'd34
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`define LH 7'd34
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`define LW 7'd35
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`define LW 7'd35
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`define LP 7'd36
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`define LP 7'd36
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`define LBU 7'd37
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`define LBU 7'd37
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`define LCU 7'd38
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`define LCU 7'd38
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`define LHU 7'd39
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`define LHU 7'd39
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`define LSH 7'd40
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`define LSH 7'd40
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`define LSW 7'd41
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`define LSW 7'd41
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`define LF 7'd42
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`define LF 7'd42
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`define LFD 7'd43
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`define LFD 7'd43
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`define LFP 7'd44
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`define LFP 7'd44
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`define LFDP 7'd45
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`define LFDP 7'd45
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`define LWR 7'd46
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`define LWR 7'd46
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`define LDONE 7'd47
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`define LDONE 7'd47
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`define SB 7'd48
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`define SB 7'd48
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`define SC 7'd49
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`define SC 7'd49
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`define SH 7'd50
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`define SH 7'd50
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`define SW 7'd51
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`define SW 7'd51
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`define SP 7'd52
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`define SP 7'd52
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`define MEMNDX 7'd53
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`define MEMNDX 7'd53
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`define SSH 7'd56
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`define SSH 7'd56
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`define SSW 7'd57
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`define SSW 7'd57
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`define SF 7'd58
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`define SF 7'd58
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`define SFD 7'd59
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`define SFD 7'd59
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`define SFP 7'd60
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`define SFP 7'd60
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`define SFDP 7'd61
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`define SFDP 7'd61
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`define SWC 7'd62
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`define SWC 7'd62
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`define INB 7'd64
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`define INB 7'd64
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`define INCH 7'd65
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`define INCH 7'd65
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`define INH 7'd66
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`define INH 7'd66
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`define INW 7'd67
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`define INW 7'd67
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`define INBU 7'd68
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`define INBU 7'd68
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`define INCU 7'd69
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`define INCU 7'd69
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`define INHU 7'd70
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`define INHU 7'd70
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`define OUTB 7'd72
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`define OUTB 7'd72
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`define OUTC 7'd73
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`define OUTC 7'd73
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`define OUTH 7'd74
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`define OUTH 7'd74
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`define OUTW 7'd75
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`define OUTW 7'd75
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`define LM 7'd78
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`define SM 7'd79
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`define BLTI 7'd80
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`define BLTI 7'd80
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`define BGEI 7'd81
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`define BGEI 7'd81
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`define BLEI 7'd82
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`define BLEI 7'd82
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`define BGTI 7'd83
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`define BGTI 7'd83
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`define BLTUI 7'd84
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`define BLTUI 7'd84
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`define BGEUI 7'd85
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`define BGEUI 7'd85
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`define BLEUI 7'd86
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`define BLEUI 7'd86
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`define BGTUI 7'd87
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`define BGTUI 7'd87
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`define BEQI 7'd88
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`define BEQI 7'd88
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`define BNEI 7'd89
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`define BNEI 7'd89
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`define BRAI 7'd90
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`define BRNI 7'd91
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`define BTRI 7'd94
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`define BTRI 7'd94
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`define BLTRI 5'd0
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`define BLTRI 5'd0
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`define BGERI 5'd1
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`define BGERI 5'd1
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`define BLERI 5'd2
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`define BLERI 5'd2
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`define BGTRI 5'd3
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`define BGTRI 5'd3
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`define BLTURI 5'd4
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`define BLTURI 5'd4
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`define BGEURI 5'd5
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`define BGEURI 5'd5
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`define BLEURI 5'd6
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`define BLEURI 5'd6
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`define BGTURI 5'd7
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`define BGTURI 5'd7
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`define BEQRI 5'd8
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`define BEQRI 5'd8
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`define BNERI 5'd9
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`define BNERI 5'd9
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`define BRARI 5'd10
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`define BRARI 5'd10
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`define BRNRI 5'd11
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`define BRNRI 5'd11
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`define BANDRI 5'd12
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`define BANDRI 5'd12
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`define BORRI 5'd13
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`define BORRI 5'd13
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`define BTRR 7'd95
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`define BTRR 7'd95
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`define BLT 5'd0
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`define BLT 5'd0
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`define BGE 5'd1
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`define BGE 5'd1
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`define BLE 5'd2
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`define BLE 5'd2
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`define BGT 5'd3
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`define BGT 5'd3
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`define BLTU 5'd4
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`define BLTU 5'd4
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`define BGEU 5'd5
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`define BGEU 5'd5
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`define BLEU 5'd6
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`define BLEU 5'd6
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`define BGTU 5'd7
|
`define BGTU 5'd7
|
`define BEQ 5'd8
|
`define BEQ 5'd8
|
`define BNE 5'd9
|
`define BNE 5'd9
|
`define BRA 5'd10
|
`define BRA 5'd10
|
`define BRN 5'd11
|
`define BRN 5'd11
|
`define BAND 5'd12
|
`define BAND 5'd12
|
`define BOR 5'd13
|
`define BOR 5'd13
|
`define BNR 5'd14
|
`define BNR 5'd14
|
|
`define LOOP 5'd15
|
`define BLTR 5'd16
|
`define BLTR 5'd16
|
`define BGER 5'd17
|
`define BGER 5'd17
|
`define BLER 5'd18
|
`define BLER 5'd18
|
`define BGTR 5'd19
|
`define BGTR 5'd19
|
`define BLTUR 5'd20
|
`define BLTUR 5'd20
|
`define BGEUR 5'd21
|
`define BGEUR 5'd21
|
`define BLEUR 5'd22
|
`define BLEUR 5'd22
|
`define BGTUR 5'd23
|
`define BGTUR 5'd23
|
`define BEQR 5'd24
|
`define BEQR 5'd24
|
`define BNER 5'd25
|
`define BNER 5'd25
|
`define BRAR 5'd26
|
`define BRAR 5'd26
|
`define BRNR 5'd27
|
`define BRNR 5'd27
|
|
|
|
|
`define SLTI 7'd96
|
`define SLTI 7'd96
|
`define SLEI 7'd97
|
`define SLEI 7'd97
|
`define SGTI 7'd98
|
`define SGTI 7'd98
|
`define SGEI 7'd99
|
`define SGEI 7'd99
|
`define SLTUI 7'd100
|
`define SLTUI 7'd100
|
`define SLEUI 7'd101
|
`define SLEUI 7'd101
|
`define SGTUI 7'd102
|
`define SGTUI 7'd102
|
`define SGEUI 7'd103
|
`define SGEUI 7'd103
|
`define SEQI 7'd104
|
`define SEQI 7'd104
|
`define SNEI 7'd105
|
`define SNEI 7'd105
|
|
|
`define FPLOO 7'd109
|
`define FPLOO 7'd109
|
`define FPZL 7'd110
|
`define FPZL 7'd110
|
`define NOPI 7'd111
|
`define NOPI 7'd111
|
|
|
`define IMM 3'd7
|
`define IMM 3'd7
|
|
|
`define NOP_INSN 42'b1101111_000_00000000_00000000_00000000_00000000
|
`define NOP_INSN 42'b1101111_000_00000000_00000000_00000000_00000000
|
|
|
module Raptor64sc(rst_i, clk_i, nmi_i, irq_i, bte_o, cti_o, bl_o,
|
module Raptor64sc(rst_i, clk_i, nmi_i, irq_i, bte_o, cti_o, bl_o,
|
cyc_o, stb_o, ack_i, we_o, sel_o, rsv_o, adr_o, dat_i, dat_o, sys_adv, sys_adr
|
cyc_o, stb_o, ack_i, we_o, sel_o, rsv_o, adr_o, dat_i, dat_o, sys_adv, sys_adr
|
);
|
);
|
parameter IDLE = 5'd1;
|
parameter IDLE = 5'd1;
|
parameter ICACT = 5'd2;
|
parameter ICACT = 5'd2;
|
parameter ICACT0 = 5'd3;
|
parameter ICACT0 = 5'd3;
|
parameter ICACT1 = 5'd4;
|
parameter ICACT1 = 5'd4;
|
parameter ICACT2 = 5'd5;
|
parameter ICACT2 = 5'd5;
|
parameter ICACT3 = 5'd6;
|
parameter ICACT3 = 5'd6;
|
parameter ICACT4 = 5'd7;
|
parameter ICACT4 = 5'd7;
|
parameter ICACT5 = 5'd8;
|
parameter ICACT5 = 5'd8;
|
parameter ICACT6 = 5'd9;
|
parameter ICACT6 = 5'd9;
|
parameter ICACT7 = 5'd10;
|
parameter ICACT7 = 5'd10;
|
parameter ICDLY = 5'd11;
|
parameter ICDLY = 5'd11;
|
parameter DCIDLE = 5'd20;
|
parameter DCIDLE = 5'd20;
|
parameter DCACT = 5'd21;
|
parameter DCACT = 5'd21;
|
parameter DCACT0 = 5'd22;
|
parameter DCACT0 = 5'd22;
|
parameter DCACT1 = 5'd23;
|
parameter DCACT1 = 5'd23;
|
parameter DCACT2 = 5'd24;
|
parameter DCACT2 = 5'd24;
|
parameter DCACT3 = 5'd25;
|
parameter DCACT3 = 5'd25;
|
parameter DCACT4 = 5'd26;
|
parameter DCACT4 = 5'd26;
|
parameter DCACT5 = 5'd27;
|
parameter DCACT5 = 5'd27;
|
parameter DCACT6 = 5'd28;
|
parameter DCACT6 = 5'd28;
|
parameter DCACT7 = 5'd29;
|
parameter DCACT7 = 5'd29;
|
parameter DCDLY = 5'd30;
|
parameter DCDLY = 5'd30;
|
|
|
input rst_i;
|
input rst_i;
|
input clk_i;
|
input clk_i;
|
input nmi_i;
|
input nmi_i;
|
input irq_i;
|
input irq_i;
|
|
|
output [1:0] bte_o;
|
output [1:0] bte_o;
|
reg [1:0] bte_o;
|
reg [1:0] bte_o;
|
output [2:0] cti_o;
|
output [2:0] cti_o;
|
reg [2:0] cti_o;
|
reg [2:0] cti_o;
|
output [4:0] bl_o;
|
output [4:0] bl_o;
|
reg [4:0] bl_o;
|
reg [4:0] bl_o;
|
output cyc_o;
|
output cyc_o;
|
reg cyc_o;
|
reg cyc_o;
|
output stb_o;
|
output stb_o;
|
reg stb_o;
|
reg stb_o;
|
input ack_i;
|
input ack_i;
|
output we_o;
|
output we_o;
|
reg we_o;
|
reg we_o;
|
output [7:0] sel_o;
|
output [7:0] sel_o;
|
reg [7:0] sel_o;
|
reg [7:0] sel_o;
|
output rsv_o;
|
output rsv_o;
|
reg rsv_o;
|
reg rsv_o;
|
output [63:0] adr_o;
|
output [63:0] adr_o;
|
reg [63:0] adr_o;
|
reg [63:0] adr_o;
|
input [63:0] dat_i;
|
input [63:0] dat_i;
|
output [63:0] dat_o;
|
output [63:0] dat_o;
|
reg [63:0] dat_o;
|
reg [63:0] dat_o;
|
|
|
input sys_adv;
|
input sys_adv;
|
input [63:5] sys_adr;
|
input [63:5] sys_adr;
|
|
|
reg resetA;
|
reg resetA;
|
reg im,bu_im; // interrupt mask
|
reg im,bu_im; // interrupt mask
|
|
reg im1; // temporary interrupt mask for LM/SM
|
reg [1:0] rm; // fp rounding mode
|
reg [1:0] rm; // fp rounding mode
|
reg [41:0] dIR;
|
reg [41:0] dIR;
|
|
reg [41:0] ndIR;
|
|
wire [6:0] dOpcode = dIR[41:35];
|
reg [41:0] xIR;
|
reg [41:0] xIR;
|
reg [63:0] pc;
|
reg [63:0] pc;
|
reg [63:0] ErrorEPC,EPC,IPC;
|
reg [63:0] ErrorEPC,EPC,IPC;
|
reg [63:0] dpc,m1pc,m2pc,wpc;
|
reg [63:0] dpc,m1pc,m2pc,wpc;
|
reg dpcv,xpcv,m1pcv,m2pcv,wpcv; // PC valid indicators
|
reg dpcv,xpcv,m1pcv,m2pcv,wpcv; // PC valid indicators
|
reg [63:0] xpc;
|
reg [63:0] xpc;
|
reg [63:0] tlbra; // return address for a TLB exception
|
reg [63:0] tlbra; // return address for a TLB exception
|
reg [8:0] dRa,dRb,dRc;
|
reg [8:0] dRa,dRb,dRc;
|
reg [8:0] wRt,mRt,m1Rt,m2Rt,tRt,dRt;
|
reg [8:0] wRt,mRt,m1Rt,m2Rt,tRt,dRt;
|
reg [8:0] xRt;
|
reg [8:0] xRt;
|
reg [63:0] dImm;
|
reg [63:0] dImm;
|
reg [63:0] ea;
|
reg [63:0] ea;
|
reg [63:0] iadr_o;
|
reg [63:0] iadr_o;
|
reg [31:0] idat;
|
reg [31:0] idat;
|
reg [4:0] cstate;
|
reg [4:0] cstate;
|
reg dbranch_taken,xbranch_taken;
|
reg dbranch_taken,xbranch_taken;
|
reg [63:0] mutex_gate;
|
reg [63:0] mutex_gate;
|
reg [63:0] TBA;
|
reg [63:0] TBA;
|
reg [1:0] dhwxtype,xhwxtype,m1hwxtype,m2hwxtype,whwxtype;
|
reg [1:0] dhwxtype,xhwxtype,m1hwxtype,m2hwxtype,whwxtype;
|
reg [3:0] AXC,dAXC,xAXC;
|
reg [3:0] AXC,dAXC,xAXC;
|
reg dtinit;
|
reg dtinit;
|
|
reg dcache_on;
|
reg [63:32] nonICacheSeg;
|
reg [63:32] nonICacheSeg;
|
|
|
//reg wr_icache;
|
|
reg dccyc;
|
reg dccyc;
|
wire [63:0] cdat;
|
wire [63:0] cdat;
|
reg [63:0] wr_addr;
|
reg [63:0] wr_addr;
|
reg [41:0] insn;
|
reg [41:0] insn;
|
wire [63:0] rfoa,rfob;
|
wire [63:0] rfoa,rfob;
|
reg clk_en;
|
reg clk_en;
|
reg cpu_clk_en;
|
reg cpu_clk_en;
|
reg StatusERL; // 1= in error processing
|
reg StatusERL; // 1= in error processing
|
reg StatusEXL; // 1= in exception processing
|
reg StatusEXL; // 1= in exception processing
|
reg StatusHWI; // 1= in interrupt processing
|
reg StatusHWI; // 1= in interrupt processing
|
reg StatusUM; // 1= user mode
|
reg StatusUM; // 1= user mode
|
reg [7:0] CauseCode;
|
reg [7:0] CauseCode;
|
reg [7:0] ASID; // address space identifier (process ID)
|
reg [7:0] ASID; // address space identifier (process ID)
|
integer n;
|
integer n;
|
reg [63:13] BadVAddr;
|
reg [63:13] BadVAddr;
|
reg [63:13] PageTableAddr;
|
reg [63:13] PageTableAddr;
|
|
|
function [63:0] fnIncPC;
|
function [63:0] fnIncPC;
|
input [63:0] fpc;
|
input [63:0] fpc;
|
begin
|
begin
|
case(fpc[3:2])
|
case(fpc[3:2])
|
2'd0: fnIncPC = {fpc[63:4],4'b0100};
|
2'd0: fnIncPC = {fpc[63:4],4'b0100};
|
2'd1: fnIncPC = {fpc[63:4],4'b1000};
|
2'd1: fnIncPC = {fpc[63:4],4'b1000};
|
2'd2: fnIncPC = {fpc[63:4]+60'd1,4'b0000};
|
2'd2: fnIncPC = {fpc[63:4]+60'd1,4'b0000};
|
2'd3: fnIncPC = {fpc[63:4]+60'd1,4'b0000};
|
2'd3: fnIncPC = {fpc[63:4]+60'd1,4'b0000};
|
endcase
|
endcase
|
end
|
end
|
endfunction
|
endfunction
|
|
|
wire KernelMode = StatusEXL;
|
wire KernelMode = StatusEXL;
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
// TLB
|
// TLB
|
// The TLB contains 64 entries, that are 8 way set associative.
|
// The TLB contains 64 entries, that are 8 way set associative.
|
// The TLB is dual ported and shared between the instruction and data streams.
|
// The TLB is dual ported and shared between the instruction and data streams.
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
|
|
wire unmappedArea = pc[63:52]==12'hFFD || pc[63:52]==12'hFFE || pc[63:52]==12'hFFF;
|
wire unmappedArea = pc[63:52]==12'hFFD || pc[63:52]==12'hFFE || pc[63:52]==12'hFFF;
|
wire unmappedDataArea = ea[63:52]==12'hFFD || ea[63:52]==12'hFFE || ea[63:52]==12'hFFF;
|
wire unmappedDataArea = ea[63:52]==12'hFFD || ea[63:52]==12'hFFE || ea[63:52]==12'hFFF;
|
wire [63:0] ppc;
|
wire [63:0] ppc;
|
wire [63:0] pea;
|
wire [63:0] pea;
|
|
|
`ifdef TLB
|
`ifdef TLB
|
reg [24:13] TLBPageMask;
|
reg [24:13] TLBPageMask;
|
reg [63:13] TLBVirtPage;
|
reg [63:13] TLBVirtPage;
|
reg [63:13] TLBPhysPage0;
|
reg [63:13] TLBPhysPage0;
|
reg [63:13] TLBPhysPage1;
|
reg [63:13] TLBPhysPage1;
|
reg [7:0] TLBASID;
|
reg [7:0] TLBASID;
|
reg TLBG;
|
reg TLBG;
|
reg TLBD;
|
reg TLBD;
|
reg TLBValid;
|
reg TLBValid;
|
reg [63:0] Index;
|
reg [63:0] Index;
|
reg [2:0] Random;
|
reg [2:0] Random;
|
reg [2:0] Wired;
|
reg [2:0] Wired;
|
reg [15:0] IMatch,DMatch;
|
reg [15:0] IMatch,DMatch;
|
|
|
reg [3:0] m;
|
reg [3:0] m;
|
reg [5:0] i;
|
reg [5:0] i;
|
reg [24:13] ITLBPageMask [63:0];
|
reg [24:13] ITLBPageMask [63:0];
|
reg [63:13] ITLBVirtPage [63:0];
|
reg [63:13] ITLBVirtPage [63:0];
|
reg [63:13] ITLBPhysPage0 [63:0];
|
reg [63:13] ITLBPhysPage0 [63:0];
|
reg [63:13] ITLBPhysPage1 [63:0];
|
reg [63:13] ITLBPhysPage1 [63:0];
|
reg [63:0] ITLBG;
|
reg [63:0] ITLBG;
|
reg [63:0] ITLBD;
|
reg [63:0] ITLBD;
|
reg [7:0] ITLBASID [63:0];
|
reg [7:0] ITLBASID [63:0];
|
reg [15:0] ITLBValid;
|
reg [15:0] ITLBValid;
|
initial begin
|
initial begin
|
for (n = 0; n < 64; n = n + 1)
|
for (n = 0; n < 64; n = n + 1)
|
begin
|
begin
|
ITLBPageMask[n] = 0;
|
ITLBPageMask[n] = 0;
|
ITLBVirtPage[n] = 0;
|
ITLBVirtPage[n] = 0;
|
ITLBPhysPage0[n] = 0;
|
ITLBPhysPage0[n] = 0;
|
ITLBPhysPage1[n] = 0;
|
ITLBPhysPage1[n] = 0;
|
ITLBG[n] = 0;
|
ITLBG[n] = 0;
|
ITLBASID[n] = 0;
|
ITLBASID[n] = 0;
|
ITLBValid[n] = 0;
|
ITLBValid[n] = 0;
|
end
|
end
|
end
|
end
|
always @*
|
always @*
|
for (n = 0; n < 8; n = n + 1)
|
for (n = 0; n < 8; n = n + 1)
|
IMatch[n] = ((pc[63:13]|ITLBPageMask[{n[2:0],pc[15:13]}])==(ITLBVirtPage[{n[2:0],pc[15:13]}]|ITLBPageMask[{n[2:0],pc[15:13]}])) &&
|
IMatch[n] = ((pc[63:13]|ITLBPageMask[{n[2:0],pc[15:13]}])==(ITLBVirtPage[{n[2:0],pc[15:13]}]|ITLBPageMask[{n[2:0],pc[15:13]}])) &&
|
((ITLBASID[{n,pc[15:13]}]==ASID) || ITLBG[{n,pc[15:13]}]) &&
|
((ITLBASID[{n,pc[15:13]}]==ASID) || ITLBG[{n,pc[15:13]}]) &&
|
ITLBValid[{n,pc[15:13]}];
|
ITLBValid[{n,pc[15:13]}];
|
always @(IMatch)
|
always @(IMatch)
|
if (IMatch[0]) m <= 4'd0;
|
if (IMatch[0]) m <= 4'd0;
|
else if (IMatch[1]) m <= 4'd1;
|
else if (IMatch[1]) m <= 4'd1;
|
else if (IMatch[2]) m <= 4'd2;
|
else if (IMatch[2]) m <= 4'd2;
|
else if (IMatch[3]) m <= 4'd3;
|
else if (IMatch[3]) m <= 4'd3;
|
else if (IMatch[4]) m <= 4'd4;
|
else if (IMatch[4]) m <= 4'd4;
|
else if (IMatch[5]) m <= 4'd5;
|
else if (IMatch[5]) m <= 4'd5;
|
else if (IMatch[6]) m <= 4'd6;
|
else if (IMatch[6]) m <= 4'd6;
|
else if (IMatch[7]) m <= 4'd7;
|
else if (IMatch[7]) m <= 4'd7;
|
else m <= 4'd15;
|
else m <= 4'd15;
|
|
|
wire ioddpage = |({ITLBPageMask[{m[2:0],pc[15:13]}]+19'd1,13'd0}&pc);
|
wire ioddpage = |({ITLBPageMask[{m[2:0],pc[15:13]}]+19'd1,13'd0}&pc);
|
wire [63:13] IPFN = ioddpage ? ITLBPhysPage1[{m[2:0],pc[15:13]}] : ITLBPhysPage0[{m[2:0],pc[15:13]}];
|
wire [63:13] IPFN = ioddpage ? ITLBPhysPage1[{m[2:0],pc[15:13]}] : ITLBPhysPage0[{m[2:0],pc[15:13]}];
|
|
|
wire ITLBMiss = !unmappedArea & m[3];
|
wire ITLBMiss = !unmappedArea & m[3];
|
|
|
assign ppc[63:13] = unmappedArea ? pc[63:13] : m[3] ? `TLBMissPage: IPFN;
|
assign ppc[63:13] = unmappedArea ? pc[63:13] : m[3] ? `TLBMissPage: IPFN;
|
assign ppc[12:0] = pc[12:0];
|
assign ppc[12:0] = pc[12:0];
|
|
|
reg [3:0] q;
|
reg [3:0] q;
|
always @(ea)
|
always @(ea)
|
for (n = 0; n < 7; n = n + 1)
|
for (n = 0; n < 7; n = n + 1)
|
DMatch[n] = ((ea[63:13]|ITLBPageMask[{n,ea[15:13]}])==(ITLBVirtPage[{n,ea[15:13]}]|ITLBPageMask[{n,ea[15:13]}])) &&
|
DMatch[n] = ((ea[63:13]|ITLBPageMask[{n,ea[15:13]}])==(ITLBVirtPage[{n,ea[15:13]}]|ITLBPageMask[{n,ea[15:13]}])) &&
|
((ITLBASID[{n,ea[15:13]}]==ASID) || ITLBG[{n,ea[15:13]}]) &&
|
((ITLBASID[{n,ea[15:13]}]==ASID) || ITLBG[{n,ea[15:13]}]) &&
|
ITLBValid[{n,ea[15:13]}];
|
ITLBValid[{n,ea[15:13]}];
|
always @(DMatch)
|
always @(DMatch)
|
if (DMatch[0]) q <= 4'd0;
|
if (DMatch[0]) q <= 4'd0;
|
else if (DMatch[1]) q <= 4'd1;
|
else if (DMatch[1]) q <= 4'd1;
|
else if (DMatch[2]) q <= 4'd2;
|
else if (DMatch[2]) q <= 4'd2;
|
else if (DMatch[3]) q <= 4'd3;
|
else if (DMatch[3]) q <= 4'd3;
|
else if (DMatch[4]) q <= 4'd4;
|
else if (DMatch[4]) q <= 4'd4;
|
else if (DMatch[5]) q <= 4'd5;
|
else if (DMatch[5]) q <= 4'd5;
|
else if (DMatch[6]) q <= 4'd6;
|
else if (DMatch[6]) q <= 4'd6;
|
else if (DMatch[7]) q <= 4'd7;
|
else if (DMatch[7]) q <= 4'd7;
|
else q <= 4'd15;
|
else q <= 4'd15;
|
|
|
wire doddpage = |({ITLBPageMask[{q[2:0],ea[15:13]}]+19'd1,13'd0}&ea);
|
wire doddpage = |({ITLBPageMask[{q[2:0],ea[15:13]}]+19'd1,13'd0}&ea);
|
wire [63:13] DPFN = doddpage ? ITLBPhysPage1[{q[2:0],ea[15:13]}] : ITLBPhysPage0[{q[2:0],ea[15:13]}];
|
wire [63:13] DPFN = doddpage ? ITLBPhysPage1[{q[2:0],ea[15:13]}] : ITLBPhysPage0[{q[2:0],ea[15:13]}];
|
|
|
wire DTLBMiss = !unmappedDataArea & q[3];
|
wire DTLBMiss = !unmappedDataArea & q[3];
|
|
|
assign pea[63:13] = unmappedDataArea ? ea[63:13] : q[3] ? `TLBMissPage: DPFN;
|
assign pea[63:13] = unmappedDataArea ? ea[63:13] : q[3] ? `TLBMissPage: DPFN;
|
assign pea[12:0] = ea[12:0];
|
assign pea[12:0] = ea[12:0];
|
`else
|
`else
|
assign ppc = pc;
|
assign ppc = pc;
|
assign pea = ea;
|
assign pea = ea;
|
`endif
|
`endif
|
wire m1UnmappedDataArea = pea[63:13]>=12'hFFD;
|
wire m1UnmappedDataArea = pea[63:13]>=12'hFFD;
|
|
|
wire dram_bus = !pea[63];
|
wire dram_bus = !pea[63];
|
wire m2_dram_bus = !m2Addr[63];
|
wire m2_dram_bus = !m2Addr[63];
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
// Clock control
|
// Clock control
|
// - reset or NMI reenables the clock
|
// - reset or NMI reenables the clock
|
// - this circuit must be under the clk_i domain
|
// - this circuit must be under the clk_i domain
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
//
|
//
|
BUFGCE u20 (.CE(cpu_clk_en), .I(clk_i), .O(clk) );
|
BUFGCE u20 (.CE(cpu_clk_en), .I(clk_i), .O(clk) );
|
|
|
always @(posedge clk_i)
|
always @(posedge clk_i)
|
if (rst_i) begin
|
if (rst_i) begin
|
cpu_clk_en <= 1'b1;
|
cpu_clk_en <= 1'b1;
|
end
|
end
|
else begin
|
else begin
|
if (nmi_i)
|
if (nmi_i)
|
cpu_clk_en <= 1'b1;
|
cpu_clk_en <= 1'b1;
|
else
|
else
|
cpu_clk_en <= clk_en;
|
cpu_clk_en <= clk_en;
|
end
|
end
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
// Instruction Cache
|
// Instruction Cache
|
// 8kB
|
// 8kB
|
//
|
//
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
|
//reg lfdir;
|
|
wire lfdir = ((dOpcode==`LM || dOpcode==`SM) && dIR[31:0]!=32'd0) && ndIR[31:0]!=32'd0;
|
|
wire ldnop = ((dOpcode==`LM || dOpcode==`SM) && (dIR[31:0]==32'd0 || ndIR[31:0]==32'd0));
|
reg icaccess;
|
reg icaccess;
|
//wire nonICachedArea;
|
|
|
|
//Raptor64_icache_ram_x32 u1
|
|
//(
|
|
// .clk(clk),
|
|
// .wr(icaccess & ack_i),
|
|
// .adr_i(adr_o[12:0]),
|
|
// .dat_i(dat_i),
|
|
// .pc(pc),
|
|
// .insn(insn)
|
|
//);
|
|
reg ICacheOn;
|
reg ICacheOn;
|
wire ibufrdy;
|
wire ibufrdy;
|
reg [63:0] tmpbuf;
|
reg [63:0] tmpbuf;
|
wire [127:0] insnbundle;
|
wire [127:0] insnbundle;
|
reg [127:0] insnbuf;
|
reg [127:0] insnbuf0,insnbuf1;
|
reg [63:4] ibuftag;
|
reg [63:4] ibuftag0,ibuftag1;
|
wire isICached = ppc[63:32]!=nonICacheSeg;
|
wire isICached = ppc[63:32]!=nonICacheSeg;
|
wire ICacheAct = ICacheOn & isICached;
|
wire ICacheAct = ICacheOn & isICached;
|
|
|
Raptor64_icache_ram u1
|
Raptor64_icache_ram u1
|
(
|
(
|
.clka(clk), // input clka
|
.clka(clk), // input clka
|
.wea(icaccess & ack_i), // input [0 : 0] wea
|
.wea(icaccess & ack_i), // input [0 : 0] wea
|
.addra(adr_o[12:3]), // input [9 : 0] addra
|
.addra(adr_o[12:3]), // input [9 : 0] addra
|
.dina(dat_i), // input [63 : 0] dina
|
.dina(dat_i), // input [63 : 0] dina
|
.clkb(~clk), // input clkb
|
.clkb(~clk), // input clkb
|
.addrb(pc[12:4]), // input [9 : 0] addrb
|
.addrb(pc[12:4]), // input [8 : 0] addrb
|
.doutb(insnbundle) // output [63 : 0] doutb
|
.doutb(insnbundle) // output [127 : 0] doutb
|
);
|
);
|
|
|
always @(pc or insnbundle or ICacheAct or insnbuf)
|
always @(ppc or insnbundle or ICacheAct or insnbuf0 or insnbuf1 or ndIR or lfdir or ldnop)
|
begin
|
begin
|
case({ICacheAct,pc[3:2]})
|
casex({ldnop,lfdir,ICacheAct,ibuftag1==ppc[63:4],pc[3:2]})
|
3'd0: insn <= insnbuf[ 41: 0];
|
6'b1xxxxx: insn <= 42'h37800000000;
|
3'd1: insn <= insnbuf[ 83:42];
|
6'b01xxxx: insn <= ndIR;
|
3'd2: insn <= insnbuf[125:84];
|
6'b001x00: insn <= insnbundle[ 41: 0];
|
3'd3: insn <= 42'h37800000000;
|
6'b001x01: insn <= insnbundle[ 83:42];
|
3'd4: insn <= insnbundle[ 41: 0];
|
6'b001x10: insn <= insnbundle[125:84];
|
3'd5: insn <= insnbundle[ 83:42];
|
6'b001x11: insn <= 42'h37800000000; // NOP instruction
|
3'd6: insn <= insnbundle[125:84];
|
6'b000000: insn <= insnbuf0[ 41: 0];
|
3'd7: insn <= 42'h37800000000; // NOP instruction
|
6'b000001: insn <= insnbuf0[ 83:42];
|
|
6'b000010: insn <= insnbuf0[125:84];
|
|
6'b000011: insn <= 42'h37800000000;
|
|
6'b000100: insn <= insnbuf1[ 41: 0];
|
|
6'b000101: insn <= insnbuf1[ 83:42];
|
|
6'b000110: insn <= insnbuf1[125:84];
|
|
6'b000111: insn <= 42'h37800000000;
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
reg [63:13] tmem [127:0];
|
reg [63:13] tmem [127:0];
|
reg [127:0] tvalid;
|
reg [127:0] tvalid;
|
|
|
initial begin
|
initial begin
|
for (n=0; n < 128; n = n + 1)
|
for (n=0; n < 128; n = n + 1)
|
tmem[n] = 0;
|
tmem[n] = 0;
|
for (n=0; n < 128; n = n + 1)
|
for (n=0; n < 128; n = n + 1)
|
tvalid[n] = 0;
|
tvalid[n] = 0;
|
end
|
end
|
|
|
wire [64:13] tgout;
|
wire [64:13] tgout;
|
assign tgout = {tvalid[pc[12:6]],tmem[pc[12:6]]};
|
assign tgout = {tvalid[pc[12:6]],tmem[pc[12:6]]};
|
assign ihit = (tgout=={1'b1,ppc[63:13]});
|
assign ihit = (tgout=={1'b1,ppc[63:13]});
|
assign ibufrdy = ibuftag==ppc[63:4];
|
assign ibufrdy = ibuftag0==ppc[63:4] || ibuftag1==ppc[63:4];
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
// Data Cache
|
// Data Cache
|
// No-allocate on write
|
// No-allocate on write
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
reg dcaccess;
|
reg dcaccess;
|
wire dhit;
|
wire dhit;
|
wire [64:15] dtgout;
|
wire [64:15] dtgout;
|
reg wrhit;
|
reg wrhit;
|
reg [7:0] dsel_o;
|
reg [7:0] dsel_o;
|
reg [63:0] dadr_o;
|
reg [63:0] dadr_o;
|
reg [31:0] ddat;
|
reg [31:0] ddat;
|
reg wr_dcache;
|
reg wr_dcache;
|
|
|
// cache RAM 16Kb
|
// cache RAM 32Kb
|
/*Raptor64_dcache_ram u10
|
|
(
|
|
.clk(clk),
|
|
.wr(dcaccess ? wr_dcache : wrhit ? (dram_bus ? wr_en: we_o): 1'b0),
|
|
.sel(dcaccess ? 4'b1111 : wrhit ? ~wr_mask : 4'b0000),
|
|
.wadr(dcaccess ? dadr_o[13:2] : wr_addr[13:2]),
|
|
.i(dcaccess ? ddat : wr_data),
|
|
.radr(pea[13:3]),
|
|
.o(cdat)
|
|
);
|
|
*/
|
|
Raptor64_dcache_ram u10
|
Raptor64_dcache_ram u10
|
(
|
(
|
.clka(clk), // input clka
|
.clka(clk), // input clka
|
.ena(1'b1),
|
.ena(1'b1),
|
.wea(dcaccess ? {8{ack_i}} : wrhit ? sel_o : 8'h00), // input [7 : 0] wea
|
.wea(dcaccess ? {8{ack_i}} : wrhit ? sel_o : 8'h00), // input [7 : 0] wea
|
.addra(adr_o[14:3]), // input [11 : 0] addra
|
.addra(adr_o[14:3]), // input [11 : 0] addra
|
.dina(dcaccess ? dat_i : dat_o), // input [63 : 0] dina
|
.dina(dcaccess ? dat_i : dat_o), // input [63 : 0] dina
|
|
|
.clkb(~clk), // input clkb
|
.clkb(~clk), // input clkb
|
.addrb(adr_o[14:3]), // input [11 : 0] addrb
|
.addrb(pea[14:3]), // input [11 : 0] addrb
|
.doutb(cdat) // output [63 : 0] doutb
|
.doutb(cdat) // output [63 : 0] doutb
|
);
|
);
|
|
|
|
|
Raptor64_dcache_tagram u11
|
Raptor64_dcache_tagram u11
|
(
|
(
|
.clka(clk), // input clka
|
.clka(clk), // input clka
|
.ena(dtinit | (adr_o[5:3]==3'b111)), // input ena
|
.ena(dtinit | (adr_o[5:3]==3'b111)), // input ena
|
.wea(dtinit | (dcaccess & ack_i)), // input [0 : 0] wea
|
.wea(dtinit | (dcaccess & ack_i)), // input [0 : 0] wea
|
.addra({1'b0,adr_o[14:6]}), // input [9 : 0] addra
|
.addra({1'b0,adr_o[14:6]}), // input [9 : 0] addra
|
.dina(dtinit ? {1'b0,adr_o[63:15]} : {1'b1,adr_o[63:15]}), // input [48 : 0] dina
|
.dina(dtinit ? {1'b0,adr_o[63:15]} : {1'b1,adr_o[63:15]}), // input [48 : 0] dina
|
|
|
.clkb(~clk), // input clkb
|
.clkb(~clk), // input clkb
|
.addrb({1'b0,pea[14:6]}), // input [9 : 0] addrb
|
.addrb({1'b0,pea[14:6]}), // input [9 : 0] addrb
|
.doutb(dtgout) // output [48 : 0] doutb
|
.doutb(dtgout) // output [48 : 0] doutb
|
);
|
);
|
// tag ram
|
|
//syncRam512x64_1rw1r u11
|
|
//(
|
|
// .wrst(1'b0),
|
|
// .wclk(clk),
|
|
// .wce(adr_o[4:2]==3'b111),
|
|
// .we(ack_i),
|
|
// .wadr(adr_o[14:5]),
|
|
// .i({14'h3FFF,dadr_o[63:14]}),
|
|
// .wo(),
|
|
//
|
|
// .rrst(1'b0),
|
|
// .rclk(~clk),
|
|
// .rce(1'b1),
|
|
// .radr(pea[13:5]),
|
|
// .ro({dtign,dtgout})
|
|
//);
|
|
|
|
assign dhit = (dtgout=={1'b1,pea[63:15]});
|
assign dhit = (dtgout=={1'b1,pea[63:15]});
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
|
|
reg [64:0] xData;
|
reg [64:0] xData;
|
wire xisCacheElement = xData[63:52] != 12'hFFD && xData[63:52]!=12'hFFF;
|
wire xisCacheElement = (xData[63:52] != 12'hFFD && xData[63:52]!=12'hFFF) && dcache_on;
|
reg m1IsCacheElement;
|
reg m1IsCacheElement;
|
|
|
reg nopI;
|
reg nopI;
|
wire [6:0] iFunc = insn[6:0];
|
wire [6:0] iFunc = insn[6:0];
|
wire [6:0] dFunc = dIR[6:0];
|
wire [6:0] dFunc = dIR[6:0];
|
wire [6:0] xFunc = xIR[6:0];
|
wire [6:0] xFunc = xIR[6:0];
|
wire [6:0] iOpcode = insn[41:35];
|
wire [6:0] iOpcode = insn[41:35];
|
wire [6:0] xOpcode = xIR[41:35];
|
wire [6:0] xOpcode = xIR[41:35];
|
wire [6:0] dOpcode = dIR[41:35];
|
|
reg [6:0] m1Opcode,m2Opcode;
|
reg [6:0] m1Opcode,m2Opcode;
|
reg [6:0] m1Func,m2Func;
|
reg [6:0] m1Func,m2Func;
|
reg [63:0] m1Data,m2Data,wData,tData;
|
reg [63:0] m1Data,m2Data,wData,tData;
|
reg [63:0] m2Addr;
|
reg [63:0] m2Addr;
|
reg [63:0] tick;
|
reg [63:0] tick;
|
reg [63:0] tba;
|
reg [63:0] tba;
|
reg [63:0] exception_address,ipc;
|
reg [63:0] exception_address,ipc;
|
reg [63:0] a,b,c,imm,m1b;
|
reg [63:0] a,b,c,imm,m1b;
|
reg prev_ihit;
|
reg prev_ihit;
|
reg rsf;
|
reg rsf;
|
reg [63:5] resv_address;
|
reg [63:5] resv_address;
|
reg dirqf,rirqf,m1irqf,m2irqf,wirqf,tirqf;
|
reg dirqf,rirqf,m1irqf,m2irqf,wirqf,tirqf;
|
reg xirqf;
|
reg xirqf;
|
reg [7:0] dextype,m1extype,m2extype,wextype,textype,exception_type;
|
reg [7:0] dextype,m1extype,m2extype,wextype,textype,exception_type;
|
reg [7:0] xextype;
|
reg [7:0] xextype;
|
wire advanceX_edge;
|
wire advanceX_edge;
|
reg takb;
|
reg takb;
|
|
|
wire [127:0] mult_out;
|
wire [127:0] mult_out;
|
wire [63:0] sqrt_out;
|
wire [63:0] sqrt_out;
|
wire [63:0] div_q;
|
wire [63:0] div_q;
|
wire [63:0] div_r;
|
wire [63:0] div_r;
|
wire sqrt_done,mult_done,div_done;
|
wire sqrt_done,mult_done,div_done;
|
wire isSqrt = xOpcode==`R && xFunc==`SQRT;
|
wire isSqrt = xOpcode==`R && xFunc==`SQRT;
|
wire [7:0] bcdaddo,bcdsubo;
|
wire [7:0] bcdaddo,bcdsubo;
|
|
|
BCDAdd u40(.ci(1'b0),.a(a[7:0]),.b(b[7:0]),.o(bcdaddo),.c());
|
BCDAdd u40(.ci(1'b0),.a(a[7:0]),.b(b[7:0]),.o(bcdaddo),.c());
|
BCDSub u41(.ci(1'b0),.a(a[7:0]),.b(b[7:0]),.o(bcdsubo),.c());
|
BCDSub u41(.ci(1'b0),.a(a[7:0]),.b(b[7:0]),.o(bcdsubo),.c());
|
|
|
isqrt #(64) u14
|
isqrt #(64) u14
|
(
|
(
|
.rst(rst_i),
|
.rst(rst_i),
|
.clk(clk),
|
.clk(clk),
|
.ce(1'b1),
|
.ce(1'b1),
|
.ld(isSqrt),
|
.ld(isSqrt),
|
.a(a),
|
.a(a),
|
.o(sqrt_out),
|
.o(sqrt_out),
|
.done(sqrt_done)
|
.done(sqrt_done)
|
);
|
);
|
|
|
wire isMulu = xOpcode==`RR && xFunc==`MULU;
|
wire isMulu = xOpcode==`RR && xFunc==`MULU;
|
wire isMuls = (xOpcode==`RR && xFunc==`MULS) || xOpcode==`MULSI;
|
wire isMuls = (xOpcode==`RR && xFunc==`MULS) || xOpcode==`MULSI;
|
wire isMuli = xOpcode==`MULSI || xOpcode==`MULUI;
|
wire isMuli = xOpcode==`MULSI || xOpcode==`MULUI;
|
wire isMult = xOpcode==`MULSI || xOpcode==`MULUI || (xOpcode==`RR && (xFunc==`MULS || xFunc==`MULU));
|
wire isMult = xOpcode==`MULSI || xOpcode==`MULUI || (xOpcode==`RR && (xFunc==`MULS || xFunc==`MULU));
|
wire isDivu = xOpcode==`RR && xFunc==`DIVU;
|
wire isDivu = xOpcode==`RR && xFunc==`DIVU;
|
wire isDivs = (xOpcode==`RR && xFunc==`DIVS) || xOpcode==`DIVSI;
|
wire isDivs = (xOpcode==`RR && xFunc==`DIVS) || xOpcode==`DIVSI;
|
wire isDivi = xOpcode==`DIVSI || xOpcode==`DIVUI;
|
wire isDivi = xOpcode==`DIVSI || xOpcode==`DIVUI;
|
wire isDiv = xOpcode==`DIVSI || xOpcode==`DIVUI || (xOpcode==`RR && (xFunc==`DIVS || xFunc==`DIVU));
|
wire isDiv = xOpcode==`DIVSI || xOpcode==`DIVUI || (xOpcode==`RR && (xFunc==`DIVS || xFunc==`DIVU));
|
|
|
wire disRRShift = dOpcode==`RR && (
|
wire disRRShift = dOpcode==`RR && (
|
dFunc==`SHL || dFunc==`ROL || dFunc==`SHR ||
|
dFunc==`SHL || dFunc==`ROL || dFunc==`SHR ||
|
dFunc==`SHRU || dFunc==`ROR || dFunc==`ROLAM
|
dFunc==`SHRU || dFunc==`ROR || dFunc==`ROLAM
|
);
|
);
|
wire disRightShift = dOpcode==`RR && (
|
wire disRightShift = dOpcode==`RR && (
|
dFunc==`SHR || dFunc==`SHRU || dFunc==`ROR
|
dFunc==`SHR || dFunc==`SHRU || dFunc==`ROR
|
);
|
);
|
|
|
Raptor64Mult u18
|
Raptor64Mult u18
|
(
|
(
|
.rst(rst_i),
|
.rst(rst_i),
|
.clk(clk),
|
.clk(clk),
|
.ld(isMult),
|
.ld(isMult),
|
.sgn(isMuls),
|
.sgn(isMuls),
|
.isMuli(isMuli),
|
.isMuli(isMuli),
|
.a(a),
|
.a(a),
|
.b(b),
|
.b(b),
|
.imm(imm),
|
.imm(imm),
|
.o(mult_out),
|
.o(mult_out),
|
.done(mult_done)
|
.done(mult_done)
|
);
|
);
|
|
|
Raptor64Div u19
|
Raptor64Div u19
|
(
|
(
|
.rst(rst_i),
|
.rst(rst_i),
|
.clk(clk),
|
.clk(clk),
|
.ld(isDiv),
|
.ld(isDiv),
|
.sgn(isDivs),
|
.sgn(isDivs),
|
.isDivi(isDivi),
|
.isDivi(isDivi),
|
.a(a),
|
.a(a),
|
.b(b),
|
.b(b),
|
.imm(imm),
|
.imm(imm),
|
.qo(div_q),
|
.qo(div_q),
|
.ro(div_r),
|
.ro(div_r),
|
.dvByZr(),
|
.dvByZr(),
|
.done(div_done)
|
.done(div_done)
|
);
|
);
|
|
|
wire [63:0] fpZLOut;
|
wire [63:0] fpZLOut;
|
wire [63:0] fpLooOut;
|
wire [63:0] fpLooOut;
|
wire fpLooDone;
|
wire fpLooDone;
|
|
|
fpZLUnit #(64) u30
|
fpZLUnit #(64) u30
|
(
|
(
|
.op(xFunc[5:0]),
|
.op(xFunc[5:0]),
|
.a(a),
|
.a(a),
|
.b(b), // for fcmp
|
.b(b), // for fcmp
|
.o(fpZLOut),
|
.o(fpZLOut),
|
.nanx()
|
.nanx()
|
);
|
);
|
|
|
fpLOOUnit #(64) u31
|
fpLOOUnit #(64) u31
|
(
|
(
|
.clk(clk),
|
.clk(clk),
|
.ce(1'b1),
|
.ce(1'b1),
|
.rm(rm),
|
.rm(rm),
|
.op(xFunc[5:0]),
|
.op(xFunc[5:0]),
|
.a(a),
|
.a(a),
|
.o(fpLooOut),
|
.o(fpLooOut),
|
.done(fpLooDone)
|
.done(fpLooDone)
|
);
|
);
|
|
|
function [2:0] popcnt6;
|
function [2:0] popcnt6;
|
input [5:0] a;
|
input [5:0] a;
|
begin
|
begin
|
case(a)
|
case(a)
|
6'b000000: popcnt6 = 3'd0;
|
6'b000000: popcnt6 = 3'd0;
|
6'b000001: popcnt6 = 3'd1;
|
6'b000001: popcnt6 = 3'd1;
|
6'b000010: popcnt6 = 3'd1;
|
6'b000010: popcnt6 = 3'd1;
|
6'b000011: popcnt6 = 3'd2;
|
6'b000011: popcnt6 = 3'd2;
|
6'b000100: popcnt6 = 3'd1;
|
6'b000100: popcnt6 = 3'd1;
|
6'b000101: popcnt6 = 3'd2;
|
6'b000101: popcnt6 = 3'd2;
|
6'b000110: popcnt6 = 3'd2;
|
6'b000110: popcnt6 = 3'd2;
|
6'b000111: popcnt6 = 3'd3;
|
6'b000111: popcnt6 = 3'd3;
|
6'b001000: popcnt6 = 3'd1;
|
6'b001000: popcnt6 = 3'd1;
|
6'b001001: popcnt6 = 3'd2;
|
6'b001001: popcnt6 = 3'd2;
|
6'b001010: popcnt6 = 3'd2;
|
6'b001010: popcnt6 = 3'd2;
|
6'b001011: popcnt6 = 3'd3;
|
6'b001011: popcnt6 = 3'd3;
|
6'b001100: popcnt6 = 3'd2;
|
6'b001100: popcnt6 = 3'd2;
|
6'b001101: popcnt6 = 3'd3;
|
6'b001101: popcnt6 = 3'd3;
|
6'b001110: popcnt6 = 3'd3;
|
6'b001110: popcnt6 = 3'd3;
|
6'b001111: popcnt6 = 3'd4;
|
6'b001111: popcnt6 = 3'd4;
|
6'b010000: popcnt6 = 3'd1;
|
6'b010000: popcnt6 = 3'd1;
|
6'b010001: popcnt6 = 3'd2;
|
6'b010001: popcnt6 = 3'd2;
|
6'b010010: popcnt6 = 3'd2;
|
6'b010010: popcnt6 = 3'd2;
|
6'b010011: popcnt6 = 3'd3;
|
6'b010011: popcnt6 = 3'd3;
|
6'b010100: popcnt6 = 3'd2;
|
6'b010100: popcnt6 = 3'd2;
|
6'b010101: popcnt6 = 3'd3;
|
6'b010101: popcnt6 = 3'd3;
|
6'b010110: popcnt6 = 3'd3;
|
6'b010110: popcnt6 = 3'd3;
|
6'b010111: popcnt6 = 3'd4;
|
6'b010111: popcnt6 = 3'd4;
|
6'b011000: popcnt6 = 3'd2;
|
6'b011000: popcnt6 = 3'd2;
|
6'b011001: popcnt6 = 3'd3;
|
6'b011001: popcnt6 = 3'd3;
|
6'b011010: popcnt6 = 3'd3;
|
6'b011010: popcnt6 = 3'd3;
|
6'b011011: popcnt6 = 3'd4;
|
6'b011011: popcnt6 = 3'd4;
|
6'b011100: popcnt6 = 3'd3;
|
6'b011100: popcnt6 = 3'd3;
|
6'b011101: popcnt6 = 3'd4;
|
6'b011101: popcnt6 = 3'd4;
|
6'b011110: popcnt6 = 3'd4;
|
6'b011110: popcnt6 = 3'd4;
|
6'b011111: popcnt6 = 3'd5;
|
6'b011111: popcnt6 = 3'd5;
|
6'b100000: popcnt6 = 3'd1;
|
6'b100000: popcnt6 = 3'd1;
|
6'b100001: popcnt6 = 3'd2;
|
6'b100001: popcnt6 = 3'd2;
|
6'b100010: popcnt6 = 3'd2;
|
6'b100010: popcnt6 = 3'd2;
|
6'b100011: popcnt6 = 3'd3;
|
6'b100011: popcnt6 = 3'd3;
|
6'b100100: popcnt6 = 3'd2;
|
6'b100100: popcnt6 = 3'd2;
|
6'b100101: popcnt6 = 3'd3;
|
6'b100101: popcnt6 = 3'd3;
|
6'b100110: popcnt6 = 3'd3;
|
6'b100110: popcnt6 = 3'd3;
|
6'b100111: popcnt6 = 3'd4;
|
6'b100111: popcnt6 = 3'd4;
|
6'b101000: popcnt6 = 3'd2;
|
6'b101000: popcnt6 = 3'd2;
|
6'b101001: popcnt6 = 3'd3;
|
6'b101001: popcnt6 = 3'd3;
|
6'b101010: popcnt6 = 3'd3;
|
6'b101010: popcnt6 = 3'd3;
|
6'b101011: popcnt6 = 3'd4;
|
6'b101011: popcnt6 = 3'd4;
|
6'b101100: popcnt6 = 3'd3;
|
6'b101100: popcnt6 = 3'd3;
|
6'b101101: popcnt6 = 3'd4;
|
6'b101101: popcnt6 = 3'd4;
|
6'b101110: popcnt6 = 3'd4;
|
6'b101110: popcnt6 = 3'd4;
|
6'b101111: popcnt6 = 3'd5;
|
6'b101111: popcnt6 = 3'd5;
|
6'b110000: popcnt6 = 3'd2;
|
6'b110000: popcnt6 = 3'd2;
|
6'b110001: popcnt6 = 3'd3;
|
6'b110001: popcnt6 = 3'd3;
|
6'b110010: popcnt6 = 3'd3;
|
6'b110010: popcnt6 = 3'd3;
|
6'b110011: popcnt6 = 3'd4;
|
6'b110011: popcnt6 = 3'd4;
|
6'b110100: popcnt6 = 3'd3;
|
6'b110100: popcnt6 = 3'd3;
|
6'b110101: popcnt6 = 3'd4;
|
6'b110101: popcnt6 = 3'd4;
|
6'b110110: popcnt6 = 3'd4;
|
6'b110110: popcnt6 = 3'd4;
|
6'b110111: popcnt6 = 3'd5;
|
6'b110111: popcnt6 = 3'd5;
|
6'b111000: popcnt6 = 3'd3;
|
6'b111000: popcnt6 = 3'd3;
|
6'b111001: popcnt6 = 3'd4;
|
6'b111001: popcnt6 = 3'd4;
|
6'b111010: popcnt6 = 3'd4;
|
6'b111010: popcnt6 = 3'd4;
|
6'b111011: popcnt6 = 3'd5;
|
6'b111011: popcnt6 = 3'd5;
|
6'b111100: popcnt6 = 3'd4;
|
6'b111100: popcnt6 = 3'd4;
|
6'b111101: popcnt6 = 3'd5;
|
6'b111101: popcnt6 = 3'd5;
|
6'b111110: popcnt6 = 3'd5;
|
6'b111110: popcnt6 = 3'd5;
|
6'b111111: popcnt6 = 3'd6;
|
6'b111111: popcnt6 = 3'd6;
|
endcase
|
endcase
|
end
|
end
|
endfunction
|
endfunction
|
|
|
|
function [5:0] popcnt36;
|
|
input [35:0] a;
|
|
begin
|
|
popcnt36 = popcnt6(a[5:0]) +
|
|
popcnt6(a[11:6]) +
|
|
popcnt6(a[17:12]) +
|
|
popcnt6(a[23:18]) +
|
|
popcnt6(a[29:24]) +
|
|
popcnt6(a[35:30]);
|
|
end
|
|
endfunction
|
|
|
wire [63:0] jmp_tgt = dOpcode[6:4]==`IMM ? {dIR[26:0],insn[34:0],2'b00} : {pc[63:37],insn[34:0],2'b00};
|
wire [63:0] jmp_tgt = dOpcode[6:4]==`IMM ? {dIR[26:0],insn[34:0],2'b00} : {pc[63:37],insn[34:0],2'b00};
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
|
// Stack for return address predictor
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
`ifdef RAS_PREDICTION
|
`ifdef RAS_PREDICTION
|
reg [63:0] ras [63:0]; // return address stack, return predictions
|
reg [63:0] ras [63:0]; // return address stack, return predictions
|
reg [5:0] ras_sp;
|
reg [5:0] ras_sp; // stack pointer
|
`endif
|
`endif
|
`ifdef BTB
|
`ifdef BTB
|
reg [63:0] btb [63:0]; // branch target buffer
|
reg [63:0] btb [63:0]; // branch target buffer
|
`endif
|
`endif
|
|
|
`ifdef BRANCH_PREDICTION_SIMPLE
|
`ifdef BRANCH_PREDICTION_SIMPLE
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
// Simple predictor:
|
// Simple predictor:
|
// - backwards branches are predicted taken, others predicted not taken.
|
// - backwards branches are predicted taken, others predicted not taken.
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
reg predict_taken;
|
reg predict_taken;
|
|
|
always @(iOpcode or insn)
|
always @(iOpcode or insn)
|
case(iOpcode)
|
case(iOpcode)
|
`BTRR:
|
`BTRR:
|
case(insn[4:0])
|
case(insn[4:0])
|
`BEQ,`BNE,`BLT,`BLE,`BGT,`BGE,`BLTU,`BLEU,`BGTU,`BGEU,`BAND,`BOR,`BNR:
|
`BEQ,`BNE,`BLT,`BLE,`BGT,`BGE,`BLTU,`BLEU,`BGTU,`BGEU,`BAND,`BOR,`BNR:
|
predict_taken = insn[24];
|
predict_taken = insn[24];
|
default: predict_taken = 1'd0;
|
default: predict_taken = 1'd0;
|
endcase
|
endcase
|
`BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
|
`BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
|
predict_taken = insn[29];
|
predict_taken = insn[29];
|
default:
|
default:
|
predict_taken = 1'd0;
|
predict_taken = 1'd0;
|
endcase
|
endcase
|
`else
|
`else
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
// Branch history table.
|
// Branch history table.
|
// The history table is updated by the EX stage and read in
|
// The history table is updated by the EX stage and read in
|
// both the EX and IF stages.
|
// both the EX and IF stages.
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
reg [2:0] gbl_branch_hist;
|
reg [2:0] gbl_branch_hist;
|
reg [1:0] branch_history_table [255:0];
|
reg [1:0] branch_history_table [255:0];
|
wire [7:0] bht_wa = {xpc[5:0],gbl_branch_hist[2:1]}; // write address
|
wire [7:0] bht_wa = {xpc[5:0],gbl_branch_hist[2:1]}; // write address
|
wire [7:0] bht_ra1 = {xpc[5:0],gbl_branch_hist[2:1]}; // read address (EX stage)
|
wire [7:0] bht_ra1 = {xpc[5:0],gbl_branch_hist[2:1]}; // read address (EX stage)
|
wire [7:0] bht_ra2 = {pc[5:0],gbl_branch_hist[2:1]}; // read address (IF stage)
|
wire [7:0] bht_ra2 = {pc[5:0],gbl_branch_hist[2:1]}; // read address (IF stage)
|
wire [1:0] bht_xbits = branch_history_table[bht_ra1];
|
wire [1:0] bht_xbits = branch_history_table[bht_ra1];
|
wire [1:0] bht_ibits = branch_history_table[bht_ra2];
|
wire [1:0] bht_ibits = branch_history_table[bht_ra2];
|
wire predict_taken = bht_ibits==2'd0 || bht_ibits==2'd1;
|
wire predict_taken = bht_ibits==2'd0 || bht_ibits==2'd1;
|
|
|
wire isxBranchI = (xOpcode==`BRAI || xOpcode==`BRNI || xOpcode==`BEQI || xOpcode==`BNEI ||
|
wire isxBranchI = (xOpcode==`BEQI || xOpcode==`BNEI ||
|
xOpcode==`BLTI || xOpcode==`BLEI || xOpcode==`BGTI || xOpcode==`BGEI ||
|
xOpcode==`BLTI || xOpcode==`BLEI || xOpcode==`BGTI || xOpcode==`BGEI ||
|
xOpcode==`BLTUI || xOpcode==`BLEUI || xOpcode==`BGTUI || xOpcode==`BGEUI)
|
xOpcode==`BLTUI || xOpcode==`BLEUI || xOpcode==`BGTUI || xOpcode==`BGEUI)
|
;
|
;
|
wire isxBranch = isxBranchI || xOpcode==`TRAPcc || xOpcode==`TRAPcci || xOpcode==`BTRI || xOpcode==`BTRR;
|
wire isxBranch = isxBranchI || xOpcode==`TRAPcc || xOpcode==`TRAPcci || xOpcode==`BTRI || xOpcode==`BTRR;
|
|
|
reg [1:0] xbits_new;
|
reg [1:0] xbits_new;
|
|
|
always @(takb or bht_xbits)
|
always @(takb or bht_xbits)
|
if (takb) begin
|
if (takb) begin
|
if (bht_xbits != 2'd1)
|
if (bht_xbits != 2'd1)
|
xbits_new <= bht_xbits + 2'd1;
|
xbits_new <= bht_xbits + 2'd1;
|
else
|
else
|
xbits_new <= bht_xbits;
|
xbits_new <= bht_xbits;
|
end
|
end
|
else begin
|
else begin
|
if (bht_xbits != 2'd2)
|
if (bht_xbits != 2'd2)
|
xbits_new <= bht_xbits - 2'd1;
|
xbits_new <= bht_xbits - 2'd1;
|
else
|
else
|
xbits_new <= bht_xbits;
|
xbits_new <= bht_xbits;
|
end
|
end
|
|
|
// For simulation only, initialize the history table to zeros.
|
// For simulation only, initialize the history table to zeros.
|
// In the real world we don't care.
|
// In the real world we don't care.
|
initial begin
|
initial begin
|
for (n = 0; n < 256; n = n + 1)
|
for (n = 0; n < 256; n = n + 1)
|
branch_history_table[n] = 0;
|
branch_history_table[n] = 0;
|
end
|
end
|
`endif
|
`endif
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
// Evaluate branch conditions.
|
// Evaluate branch conditions.
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
wire signed [63:0] as = a;
|
wire signed [63:0] as = a;
|
wire signed [63:0] bs = b;
|
wire signed [63:0] bs = b;
|
wire signed [63:0] imms = imm;
|
wire signed [63:0] imms = imm;
|
wire aeqz = a==64'd0;
|
wire aeqz = a==64'd0;
|
wire beqz = b==64'd0;
|
wire beqz = b==64'd0;
|
wire immeqz = imm==64'd0;
|
wire immeqz = imm==64'd0;
|
wire eq = a==b;
|
wire eq = a==b;
|
wire eqi = a==imm;
|
wire eqi = a==imm;
|
wire lt = $signed(a) < $signed(b);
|
wire lt = $signed(a) < $signed(b);
|
wire lti = as < imms;
|
wire lti = as < imms;
|
wire ltu = a < b;
|
wire ltu = a < b;
|
wire ltui = a < imm;
|
wire ltui = a < imm;
|
|
|
always @(xOpcode or xFunc or a or eq or eqi or lt or lti or ltu or ltui or aeqz or beqz or rsf or xIR)
|
always @(xOpcode or xFunc or a or eq or eqi or lt or lti or ltu or ltui or aeqz or beqz or rsf or xIR)
|
case (xOpcode)
|
case (xOpcode)
|
`BTRR:
|
`BTRR:
|
case(xIR[4:0])
|
case(xIR[4:0])
|
`BRA: takb = 1'b1;
|
`BRA: takb = 1'b1;
|
`BRN: takb = 1'b0;
|
`BRN: takb = 1'b0;
|
`BEQ: takb = eq;
|
`BEQ: takb = eq;
|
`BNE: takb = !eq;
|
`BNE: takb = !eq;
|
`BLT: takb = lt;
|
`BLT: takb = lt;
|
`BLE: takb = lt|eq;
|
`BLE: takb = lt|eq;
|
`BGT: takb = !(lt|eq);
|
`BGT: takb = !(lt|eq);
|
`BGE: takb = !lt;
|
`BGE: takb = !lt;
|
`BLTU: takb = ltu;
|
`BLTU: takb = ltu;
|
`BLEU: takb = ltu|eq;
|
`BLEU: takb = ltu|eq;
|
`BGTU: takb = !(ltu|eq);
|
`BGTU: takb = !(ltu|eq);
|
`BGEU: takb = !ltu;
|
`BGEU: takb = !ltu;
|
`BOR: takb = !aeqz || !beqz;
|
`BOR: takb = !aeqz || !beqz;
|
`BAND: takb = !aeqz && !beqz;
|
`BAND: takb = !aeqz && !beqz;
|
`BNR: takb = !rsf;
|
`BNR: takb = !rsf;
|
|
`LOOP: takb = !beqz;
|
`BEQR: takb = eq;
|
`BEQR: takb = eq;
|
`BNER: takb = !eq;
|
`BNER: takb = !eq;
|
`BLTR: takb = lt;
|
`BLTR: takb = lt;
|
`BLER: takb = lt|eq;
|
`BLER: takb = lt|eq;
|
`BGTR: takb = !(lt|eq);
|
`BGTR: takb = !(lt|eq);
|
`BGER: takb = !lt;
|
`BGER: takb = !lt;
|
`BLTUR: takb = ltu;
|
`BLTUR: takb = ltu;
|
`BLEUR: takb = ltu|eq;
|
`BLEUR: takb = ltu|eq;
|
`BGTUR: takb = !(ltu|eq);
|
`BGTUR: takb = !(ltu|eq);
|
`BGEUR: takb = !ltu;
|
`BGEUR: takb = !ltu;
|
default: takb = 1'b0;
|
default: takb = 1'b0;
|
endcase
|
endcase
|
`BRAI: takb = 1'b1;
|
|
`BRNI: takb = 1'b0;
|
|
`BEQI: takb = eqi;
|
`BEQI: takb = eqi;
|
`BNEI: takb = !eqi;
|
`BNEI: takb = !eqi;
|
`BLTI: takb = lti;
|
`BLTI: takb = lti;
|
`BLEI: takb = lti|eqi;
|
`BLEI: takb = lti|eqi;
|
`BGTI: takb = !(lti|eqi);
|
`BGTI: takb = !(lti|eqi);
|
`BGEI: takb = !lti;
|
`BGEI: takb = !lti;
|
`BLTUI: takb = ltui;
|
`BLTUI: takb = ltui;
|
`BLEUI: takb = ltui|eqi;
|
`BLEUI: takb = ltui|eqi;
|
`BGTUI: takb = !(ltui|eqi);
|
`BGTUI: takb = !(ltui|eqi);
|
`BGEUI: takb = !ltui;
|
`BGEUI: takb = !ltui;
|
`BTRI:
|
`BTRI:
|
case(xIR[24:18])
|
case(xIR[24:18])
|
`BRA: takb = 1'b1;
|
`BRA: takb = 1'b1;
|
`BRN: takb = 1'b0;
|
`BRN: takb = 1'b0;
|
`BEQ: takb = eqi;
|
`BEQ: takb = eqi;
|
`BNE: takb = !eqi;
|
`BNE: takb = !eqi;
|
`BLT: takb = lti;
|
`BLT: takb = lti;
|
`BLE: takb = lti|eqi;
|
`BLE: takb = lti|eqi;
|
`BGT: takb = !(lti|eqi);
|
`BGT: takb = !(lti|eqi);
|
`BGE: takb = !lti;
|
`BGE: takb = !lti;
|
`BLTU: takb = ltui;
|
`BLTU: takb = ltui;
|
`BLEU: takb = ltui|eqi;
|
`BLEU: takb = ltui|eqi;
|
`BGTU: takb = !(ltui|eqi);
|
`BGTU: takb = !(ltui|eqi);
|
`BGEU: takb = !ltui;
|
`BGEU: takb = !ltui;
|
default: takb = 1'b0;
|
default: takb = 1'b0;
|
endcase
|
endcase
|
`TRAPcc:
|
`TRAPcc:
|
case(xFunc)
|
case(xFunc)
|
`TEQ: takb = eq;
|
`TEQ: takb = eq;
|
`TNE: takb = !eq;
|
`TNE: takb = !eq;
|
`TLT: takb = lt;
|
`TLT: takb = lt;
|
`TLE: takb = lt|eq;
|
`TLE: takb = lt|eq;
|
`TGT: takb = !(lt|eq);
|
`TGT: takb = !(lt|eq);
|
`TGE: takb = !lt;
|
`TGE: takb = !lt;
|
`TLTU: takb = ltu;
|
`TLTU: takb = ltu;
|
`TLEU: takb = ltu|eq;
|
`TLEU: takb = ltu|eq;
|
`TGTU: takb = !(ltu|eq);
|
`TGTU: takb = !(ltu|eq);
|
`TGEU: takb = !ltu;
|
`TGEU: takb = !ltu;
|
default: takb = 1'b0;
|
default: takb = 1'b0;
|
endcase
|
endcase
|
`TRAPcci:
|
`TRAPcci:
|
case(xIR[29:25])
|
case(xIR[29:25])
|
`TEQI: takb = eqi;
|
`TEQI: takb = eqi;
|
`TNEI: takb = !eqi;
|
`TNEI: takb = !eqi;
|
`TLTI: takb = lti;
|
`TLTI: takb = lti;
|
`TLEI: takb = lti|eqi;
|
`TLEI: takb = lti|eqi;
|
`TGTI: takb = !(lti|eqi);
|
`TGTI: takb = !(lti|eqi);
|
`TGEI: takb = !lti;
|
`TGEI: takb = !lti;
|
`TLTUI: takb = ltui;
|
`TLTUI: takb = ltui;
|
`TLEUI: takb = ltui|eqi;
|
`TLEUI: takb = ltui|eqi;
|
`TGTUI: takb = !(ltui|eqi);
|
`TGTUI: takb = !(ltui|eqi);
|
`TGEUI: takb = !ltui;
|
`TGEUI: takb = !ltui;
|
default: takb = 1'b0;
|
default: takb = 1'b0;
|
endcase
|
endcase
|
default:
|
default:
|
takb = 1'b0;
|
takb = 1'b0;
|
endcase
|
endcase
|
|
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
// Datapath (ALU) operations.
|
// Datapath (ALU) operations.
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
wire [6:0] cntlzo,cntloo;
|
wire [6:0] cntlzo,cntloo;
|
cntlz64 u12 ( .i(a), .o(cntlzo) );
|
cntlz64 u12 ( .i(a), .o(cntlzo) );
|
cntlo64 u13 ( .i(a), .o(cntloo) );
|
cntlo64 u13 ( .i(a), .o(cntloo) );
|
|
|
reg [1:0] shftop;
|
reg [1:0] shftop;
|
wire [63:0] shfto;
|
wire [63:0] shfto;
|
always @(xFunc)
|
always @(xFunc)
|
if (xFunc==`SHL)
|
if (xFunc==`SHL)
|
shftop = 2'b00;
|
shftop = 2'b00;
|
else if (xFunc==`ROL || xFunc==`ROR)
|
else if (xFunc==`ROL || xFunc==`ROR)
|
shftop = 2'b01;
|
shftop = 2'b01;
|
else if (xFunc==`SHRU)
|
else if (xFunc==`SHRU)
|
shftop = 2'b10;
|
shftop = 2'b10;
|
else if (xFunc==`SHR)
|
else if (xFunc==`SHR)
|
shftop = 2'b11;
|
shftop = 2'b11;
|
else
|
else
|
shftop = 2'b01;
|
shftop = 2'b01;
|
|
|
wire [63:0] masko;
|
wire [63:0] masko;
|
shiftAndMask u15
|
shiftAndMask u15
|
(
|
(
|
.op(shftop),
|
.op(shftop),
|
.oz(1'b0), // zero the output
|
.oz(1'b0), // zero the output
|
.a(a),
|
.a(a),
|
.b(b[5:0]),
|
.b(b[5:0]),
|
.mb(xIR[12:7]),
|
.mb(xIR[12:7]),
|
.me(xIR[18:13]),
|
.me(xIR[18:13]),
|
.o(shfto),
|
.o(shfto),
|
.mo(masko)
|
.mo(masko)
|
);
|
);
|
|
|
always @(xOpcode or xFunc or a or b or imm or as or bs or imms or xpc or
|
always @(xOpcode or xFunc or a or b or imm or as or bs or imms or xpc or
|
sqrt_out or cntlzo or cntloo or tick or ipc or tba or AXC or
|
sqrt_out or cntlzo or cntloo or tick or ipc or tba or AXC or
|
lt or eq or ltu or mult_out or lti or eqi or ltui or xIR or div_q or div_r or
|
lt or eq or ltu or mult_out or lti or eqi or ltui or xIR or div_q or div_r or
|
shfto or masko or bcdaddo or bcdsubo or fpLooOut or fpZLOut
|
shfto or masko or bcdaddo or bcdsubo or fpLooOut or fpZLOut
|
`ifdef TLB
|
`ifdef TLB
|
or Wired or Index or Random or TLBPhysPage0 or TLBPhysPage1 or TLBVirtPage or TLBASID or
|
or Wired or Index or Random or TLBPhysPage0 or TLBPhysPage1 or TLBVirtPage or TLBASID or
|
PageTableAddr or BadVAddr or ASID or TLBPageMask
|
PageTableAddr or BadVAddr or ASID or TLBPageMask
|
`endif
|
`endif
|
|
or ASID or EPC or mutex_gate or IPC or CauseCode or TBA or xAXC or nonICacheSeg or rm
|
)
|
)
|
casex(xOpcode)
|
casex(xOpcode)
|
`R:
|
`R:
|
casex(xFunc)
|
casex(xFunc)
|
`COM: xData = ~a;
|
`COM: xData = ~a;
|
`NOT: xData = ~|a;
|
`NOT: xData = ~|a;
|
`NEG: xData = -a;
|
`NEG: xData = -a;
|
`ABS: xData = a[63] ? -a : a;
|
`ABS: xData = a[63] ? -a : a;
|
|
`MOV: xData = a;
|
`SQRT: xData = sqrt_out;
|
`SQRT: xData = sqrt_out;
|
`SWAP: xData = {a[31:0],a[63:32]};
|
`SWAP: xData = {a[31:0],a[63:32]};
|
|
|
`REDOR: xData = |a;
|
`REDOR: xData = |a;
|
`REDAND: xData = &a;
|
`REDAND: xData = &a;
|
|
|
`CTLZ: xData = cntlzo;
|
`CTLZ: xData = cntlzo;
|
`CTLO: xData = cntloo;
|
`CTLO: xData = cntloo;
|
`CTPOP: xData = {4'd0,popcnt6(a[5:0])} +
|
`CTPOP: xData = {4'd0,popcnt6(a[5:0])} +
|
{4'd0,popcnt6(a[11:6])} +
|
{4'd0,popcnt6(a[11:6])} +
|
{4'd0,popcnt6(a[17:12])} +
|
{4'd0,popcnt6(a[17:12])} +
|
{4'd0,popcnt6(a[23:18])} +
|
{4'd0,popcnt6(a[23:18])} +
|
{4'd0,popcnt6(a[29:24])} +
|
{4'd0,popcnt6(a[29:24])} +
|
{4'd0,popcnt6(a[35:30])} +
|
{4'd0,popcnt6(a[35:30])} +
|
{4'd0,popcnt6(a[41:36])} +
|
{4'd0,popcnt6(a[41:36])} +
|
{4'd0,popcnt6(a[47:42])} +
|
{4'd0,popcnt6(a[47:42])} +
|
{4'd0,popcnt6(a[53:48])} +
|
{4'd0,popcnt6(a[53:48])} +
|
{4'd0,popcnt6(a[59:54])} +
|
{4'd0,popcnt6(a[59:54])} +
|
{4'd0,popcnt6(a[63:60])}
|
{4'd0,popcnt6(a[63:60])}
|
;
|
;
|
`SEXT8: xData = {{56{a[7]}},a[7:0]};
|
`SEXT8: xData = {{56{a[7]}},a[7:0]};
|
`SEXT16: xData = {{48{a[15]}},a[15:0]};
|
`SEXT16: xData = {{48{a[15]}},a[15:0]};
|
`SEXT32: xData = {{32{a[31]}},a[31:0]};
|
`SEXT32: xData = {{32{a[31]}},a[31:0]};
|
|
|
`MFSPR:
|
`MFSPR:
|
case(xIR[12:7])
|
case(xIR[12:7])
|
`ifdef TLB
|
`ifdef TLB
|
`Wired: xData = Wired;
|
`Wired: xData = Wired;
|
`TLBIndex: xData = Index;
|
`TLBIndex: xData = Index;
|
`TLBRandom: xData = Random;
|
`TLBRandom: xData = Random;
|
`TLBPhysPage0: xData = {TLBPhysPage0,13'd0};
|
`TLBPhysPage0: xData = {TLBPhysPage0,13'd0};
|
`TLBPhysPage1: xData = {TLBPhysPage1,13'd0};
|
`TLBPhysPage1: xData = {TLBPhysPage1,13'd0};
|
`TLBVirtPage: xData = {TLBVirtPage,13'd0};
|
`TLBVirtPage: xData = {TLBVirtPage,13'd0};
|
`TLBPageMask: xData = {TLBPageMask,13'd0};
|
`TLBPageMask: xData = {TLBPageMask,13'd0};
|
`TLBASID: begin
|
`TLBASID: begin
|
xData = 65'd0;
|
xData = 65'd0;
|
xData[0] = TLBValid;
|
xData[0] = TLBValid;
|
xData[1] = TLBD;
|
xData[1] = TLBD;
|
xData[2] = TLBG;
|
xData[2] = TLBG;
|
xData[15:8] = TLBASID;
|
xData[15:8] = TLBASID;
|
end
|
end
|
`PageTableAddr: xData = {PageTableAddr,13'd0};
|
`PageTableAddr: xData = {PageTableAddr,13'd0};
|
`BadVAddr: xData = {BadVAddr,13'd0};
|
`BadVAddr: xData = {BadVAddr,13'd0};
|
`endif
|
`endif
|
`ASID: xData = ASID;
|
`ASID: xData = ASID;
|
`Tick: xData = tick;
|
`Tick: xData = tick;
|
`EPC: xData = EPC;
|
`EPC: xData = EPC;
|
|
`IPC: xData = IPC;
|
`CauseCode: xData = CauseCode;
|
`CauseCode: xData = CauseCode;
|
`TBA: xData = TBA;
|
`TBA: xData = TBA;
|
`AXC: xData = xAXC;
|
`AXC: xData = xAXC;
|
`NON_ICACHE_SEG: xData = nonICacheSeg;
|
`NON_ICACHE_SEG: xData = nonICacheSeg;
|
|
`FPCR: xData = {rm,30'd0};
|
default: xData = 65'd0;
|
default: xData = 65'd0;
|
endcase
|
endcase
|
`OMG: xData = mutex_gate[a[5:0]];
|
`OMG: xData = mutex_gate[a[5:0]];
|
`CMG: xData = mutex_gate[a[5:0]];
|
`CMG: xData = mutex_gate[a[5:0]];
|
`OMGI: begin
|
`OMGI: begin
|
xData = mutex_gate[xIR[12:7]];
|
xData = mutex_gate[xIR[12:7]];
|
$display("mutex_gate[%d]=%d",xIR[12:7],mutex_gate[xIR[12:7]]);
|
$display("mutex_gate[%d]=%d",xIR[12:7],mutex_gate[xIR[12:7]]);
|
end
|
end
|
`CMGI: xData = mutex_gate[xIR[12:7]];
|
`CMGI: xData = mutex_gate[xIR[12:7]];
|
default: xData = 65'd0;
|
default: xData = 65'd0;
|
endcase
|
endcase
|
`RR:
|
`RR:
|
case(xFunc)
|
case(xFunc)
|
`ADD: xData = a + b;
|
`ADD: xData = a + b;
|
`ADDU: xData = a + b;
|
`ADDU: xData = a + b;
|
`SUB: xData = a - b;
|
`SUB: xData = a - b;
|
`SUBU: xData = a - b;
|
`SUBU: xData = a - b;
|
`CMP: xData = lt ? 64'hFFFFFFFFFFFFF : eq ? 64'd0 : 64'd1;
|
`CMP: xData = lt ? 64'hFFFFFFFFFFFFF : eq ? 64'd0 : 64'd1;
|
`CMPU: xData = ltu ? 64'hFFFFFFFFFFFFF : eq ? 64'd0 : 64'd1;
|
`CMPU: xData = ltu ? 64'hFFFFFFFFFFFFF : eq ? 64'd0 : 64'd1;
|
`SEQ: xData = eq;
|
`SEQ: xData = eq;
|
`SNE: xData = !eq;
|
`SNE: xData = !eq;
|
`SLT: xData = lt;
|
`SLT: xData = lt;
|
`SLE: xData = lt|eq;
|
`SLE: xData = lt|eq;
|
`SGT: xData = !(lt|eq);
|
`SGT: xData = !(lt|eq);
|
`SGE: xData = !lt;
|
`SGE: xData = !lt;
|
`SLTU: xData = ltu;
|
`SLTU: xData = ltu;
|
`SLEU: xData = ltu|eq;
|
`SLEU: xData = ltu|eq;
|
`SGTU: xData = !(ltu|eq);
|
`SGTU: xData = !(ltu|eq);
|
`SGEU: xData = !ltu;
|
`SGEU: xData = !ltu;
|
`AND: xData = a & b;
|
`AND: xData = a & b;
|
`OR: xData = a | b;
|
`OR: xData = a | b;
|
`XOR: xData = a ^ b;
|
`XOR: xData = a ^ b;
|
`ANDC: xData = a & ~b;
|
`ANDC: xData = a & ~b;
|
`NAND: xData = ~(a & b);
|
`NAND: xData = ~(a & b);
|
`NOR: xData = ~(a | b);
|
`NOR: xData = ~(a | b);
|
`XNOR: xData = ~(a ^ b);
|
`XNOR: xData = ~(a ^ b);
|
`ORC: xData = a | ~b;
|
`ORC: xData = a | ~b;
|
`MIN: xData = lt ? a : b;
|
`MIN: xData = lt ? a : b;
|
`MAX: xData = lt ? b : a;
|
`MAX: xData = lt ? b : a;
|
`MOVZ: xData = b;
|
`MOVZ: xData = b;
|
`MOVNZ: xData = b;
|
`MOVNZ: xData = b;
|
`MULS: xData = mult_out[63:0];
|
`MULS: xData = mult_out[63:0];
|
`MULU: xData = mult_out[63:0];
|
`MULU: xData = mult_out[63:0];
|
`DIVS: xData = div_q;
|
`DIVS: xData = div_q;
|
`DIVU: xData = div_q;
|
`DIVU: xData = div_q;
|
`MOD: xData = div_r;
|
`MOD: xData = div_r;
|
|
|
`SHL: xData = shfto;
|
`SHL: xData = shfto;
|
`SHRU: xData = shfto;
|
`SHRU: xData = shfto;
|
`ROL: xData = shfto;
|
`ROL: xData = shfto;
|
`ROR: xData = {a[0],a[63:1]};
|
`ROR: xData = {a[0],a[63:1]};
|
`SHR: xData = shfto;
|
`SHR: xData = shfto;
|
`ROLAM: xData = shfto & masko;
|
`ROLAM: xData = shfto & masko;
|
|
|
`BCD_ADD: xData = bcdaddo;
|
`BCD_ADD: xData = bcdaddo;
|
`BCD_SUB: xData = bcdsubo;
|
`BCD_SUB: xData = bcdsubo;
|
|
|
default: xData = 65'd0;
|
default: xData = 65'd0;
|
endcase
|
endcase
|
`SHFTI:
|
`SHFTI:
|
case(xFunc)
|
case(xFunc)
|
`SHLI: xData = shfto;
|
`SHLI: xData = shfto;
|
`SHRUI: xData = shfto;
|
`SHRUI: xData = shfto;
|
`ROLI: xData = shfto;
|
`ROLI: xData = shfto;
|
`RORI: xData = {a[0],a[63:1]};
|
`RORI: xData = {a[0],a[63:1]};
|
`SHRI: xData = shfto;
|
`SHRI: xData = shfto;
|
`ROLAMI: xData = shfto & masko;
|
`ROLAMI: xData = shfto & masko;
|
`BFINS: begin for (n = 0; n < 64; n = n + 1) xData[n] = masko[n] ? shfto[n] : b[n]; xData[64] = 1'b0; end
|
`BFINS: begin for (n = 0; n < 64; n = n + 1) xData[n] = masko[n] ? shfto[n] : b[n]; xData[64] = 1'b0; end
|
`BFSET: begin for (n = 0; n < 64; n = n + 1) xData[n] = masko[n] ? 1'b1 : b[n]; xData[64] = 1'b0; end
|
`BFSET: begin for (n = 0; n < 64; n = n + 1) xData[n] = masko[n] ? 1'b1 : b[n]; xData[64] = 1'b0; end
|
`BFCLR: begin for (n = 0; n < 64; n = n + 1) xData[n] = masko[n] ? 1'b0 : b[n]; xData[64] = 1'b0; end
|
`BFCLR: begin for (n = 0; n < 64; n = n + 1) xData[n] = masko[n] ? 1'b0 : b[n]; xData[64] = 1'b0; end
|
`BFCHG: begin for (n = 0; n < 64; n = n + 1) xData[n] = masko[n] ? ~b[n] : b[n]; xData[64] = 1'b0; end
|
`BFCHG: begin for (n = 0; n < 64; n = n + 1) xData[n] = masko[n] ? ~b[n] : b[n]; xData[64] = 1'b0; end
|
default: xData = 65'd0;
|
default: xData = 65'd0;
|
endcase
|
endcase
|
|
`BTRR:
|
|
case(xIR[4:0])
|
|
`LOOP: xData = b - 64'd1;
|
|
default: xData = 64'd0;
|
|
endcase
|
`SETLO: xData = {{32{xIR[31]}},xIR[31:0]};
|
`SETLO: xData = {{32{xIR[31]}},xIR[31:0]};
|
`SETHI: xData = {xIR[31:0],a[31:0]};
|
`SETHI: xData = {xIR[31:0],a[31:0]};
|
`ADDI: xData = a + imm;
|
`ADDI: xData = a + imm;
|
`ADDUI: xData = a + imm;
|
`ADDUI: xData = a + imm;
|
`SUBI: xData = a - imm;
|
`SUBI: xData = a - imm;
|
`SUBUI: xData = a - imm;
|
`SUBUI: xData = a - imm;
|
`CMPI: xData = lti ? 64'hFFFFFFFFFFFFF : eqi ? 64'd0 : 64'd1;
|
`CMPI: xData = lti ? 64'hFFFFFFFFFFFFF : eqi ? 64'd0 : 64'd1;
|
`CMPUI: xData = ltui ? 64'hFFFFFFFFFFFFF : eqi ? 64'd0 : 64'd1;
|
`CMPUI: xData = ltui ? 64'hFFFFFFFFFFFFF : eqi ? 64'd0 : 64'd1;
|
`MULSI: xData = mult_out[63:0];
|
`MULSI: xData = mult_out[63:0];
|
`MULUI: xData = mult_out[63:0];
|
`MULUI: xData = mult_out[63:0];
|
`DIVSI: xData = div_q;
|
`DIVSI: xData = div_q;
|
`DIVUI: xData = div_q;
|
`DIVUI: xData = div_q;
|
`ANDI: xData = a & imm;
|
`ANDI: xData = a & imm;
|
`ORI: xData = a | imm;
|
`ORI: xData = a | imm;
|
`XORI: xData = a ^ imm;
|
`XORI: xData = a ^ imm;
|
`SEQI: xData = eqi;
|
`SEQI: xData = eqi;
|
`SNEI: xData = !eqi;
|
`SNEI: xData = !eqi;
|
`SLTI: xData = lti;
|
`SLTI: xData = lti;
|
`SLEI: xData = lti|eqi;
|
`SLEI: xData = lti|eqi;
|
`SGTI: xData = !(lti|eqi);
|
`SGTI: xData = !(lti|eqi);
|
`SGEI: xData = !lti;
|
`SGEI: xData = !lti;
|
`SLTUI: xData = ltui;
|
`SLTUI: xData = ltui;
|
`SLEUI: xData = ltui|eqi;
|
`SLEUI: xData = ltui|eqi;
|
`SGTUI: xData = !(ltui|eqi);
|
`SGTUI: xData = !(ltui|eqi);
|
`SGEUI: xData = !ltui;
|
`SGEUI: xData = !ltui;
|
`INB,`INCH,`INH,`INW:
|
`INB,`INCH,`INH,`INW:
|
xData = a + imm;
|
xData = a + imm;
|
`OUTB,`OUTC,`OUTH,`OUTW:
|
`OUTB,`OUTC,`OUTH,`OUTW:
|
xData = a + imm;
|
xData = a + imm;
|
`LW,`LH,`LC,`LB,`LHU,`LCU,`LBU,`LWR:
|
`LW,`LH,`LC,`LB,`LHU,`LCU,`LBU,`LWR,`LF,`LFD:
|
xData = a + imm;
|
xData = a + imm;
|
`SW,`SH,`SC,`SB,`SWC:
|
`SW,`SH,`SC,`SB,`SWC,`SF,`SFD:
|
xData = a + imm;
|
xData = a + imm;
|
`MEMNDX:
|
`MEMNDX:
|
xData = a + b + imm;
|
xData = a + b + imm;
|
`BEQ,`BNE,`BLT,`BLE,`BGT,`BGE,`BLTU,`BLEU,`BGTU,`BGEU,`BOR,`BAND:
|
`SM: xData = a + {popcnt36(xIR[31:0]),3'b000};
|
xData = 64'd0;
|
`LM: xData = a + {popcnt36(xIR[31:0]),3'b000};
|
`TRAPcc: xData = fnIncPC(xpc);
|
`TRAPcc: xData = fnIncPC(xpc);
|
`TRAPcci: xData = fnIncPC(xpc);
|
`TRAPcci: xData = fnIncPC(xpc);
|
`CALL: xData = fnIncPC(xpc);
|
`CALL: xData = fnIncPC(xpc);
|
`JAL: xData = xpc + {xIR[29:25],2'b00};
|
`JAL: xData = xpc + {xIR[29:25],2'b00};
|
`RET: xData = a + {imm,2'b00};
|
`RET: xData = a + imm;
|
`FPLOO: xData = fpLooOut;
|
`FPLOO: xData = fpLooOut;
|
`FPZL: xData = fpZLOut;
|
`FPZL: xData = fpZLOut;
|
default: xData = 65'd0;
|
default: xData = 65'd0;
|
endcase
|
endcase
|
|
|
wire v_ri,v_rr;
|
wire v_ri,v_rr;
|
overflow u2 (.op(xOpcode==`SUBI), .a(a[63]), .b(imm[63]), .s(xData[63]), .v(v_ri));
|
overflow u2 (.op(xOpcode==`SUBI), .a(a[63]), .b(imm[63]), .s(xData[63]), .v(v_ri));
|
overflow u3 (.op(xOpcode==`RR && xFunc==`SUB), .a(a[63]), .b(b[63]), .s(xData[63]), .v(v_rr));
|
overflow u3 (.op(xOpcode==`RR && xFunc==`SUB), .a(a[63]), .b(b[63]), .s(xData[63]), .v(v_rr));
|
|
|
wire dbz_error = (xOpcode==`DIVSI||xOpcode==`DIVUI) && b==64'd0;
|
wire dbz_error = (xOpcode==`DIVSI||xOpcode==`DIVUI) && b==64'd0;
|
wire ovr_error = ((xOpcode==`ADDI || xOpcode==`SUBI) && v_ri) || ((xOpcode==`RR && (xFunc==`SUB || xFunc==`ADD)) && v_rr);
|
wire ovr_error = ((xOpcode==`ADDI || xOpcode==`SUBI) && v_ri) || ((xOpcode==`RR && (xFunc==`SUB || xFunc==`ADD)) && v_rr);
|
wire priv_violation = !KernelMode && (xOpcode==`MISC &&
|
wire priv_violation = !KernelMode && (xOpcode==`MISC &&
|
(xFunc==`IRET || xFunc==`ERET || xFunc==`CLI || xFunc==`SEI ||
|
(xFunc==`IRET || xFunc==`ERET || xFunc==`CLI || xFunc==`SEI ||
|
xFunc==`TLBP || xFunc==`TLBR || xFunc==`TLBWR || xFunc==`TLBWI
|
xFunc==`TLBP || xFunc==`TLBR || xFunc==`TLBWR || xFunc==`TLBWI
|
));
|
));
|
wire xIsSqrt = xOpcode==`R && xFunc==`SQRT;
|
wire xIsSqrt = xOpcode==`R && xFunc==`SQRT;
|
wire xIsMult = (xOpcode==`RR && (xFunc==`MULU || xFunc==`MULS)) ||
|
wire xIsMult = (xOpcode==`RR && (xFunc==`MULU || xFunc==`MULS)) ||
|
xOpcode==`MULSI || xOpcode==`MULUI;
|
xOpcode==`MULSI || xOpcode==`MULUI;
|
wire xIsDiv = (xOpcode==`RR && (xFunc==`DIVU || xFunc==`DIVS)) ||
|
wire xIsDiv = (xOpcode==`RR && (xFunc==`DIVU || xFunc==`DIVS)) ||
|
xOpcode==`DIVSI || xOpcode==`DIVUI;
|
xOpcode==`DIVSI || xOpcode==`DIVUI;
|
|
|
wire xIsLoad =
|
wire xIsLoad =
|
xOpcode==`LW || xOpcode==`LH || xOpcode==`LB || xOpcode==`LWR ||
|
xOpcode==`LW || xOpcode==`LH || xOpcode==`LB || xOpcode==`LWR ||
|
xOpcode==`LHU || xOpcode==`LBU ||
|
xOpcode==`LHU || xOpcode==`LBU ||
|
xOpcode==`LC || xOpcode==`LCU ||
|
xOpcode==`LC || xOpcode==`LCU || xOpcode==`LM ||
|
xOpcode==`INW || xOpcode==`INB || xOpcode==`INH || xOpcode==`INCH
|
xOpcode==`LF || xOpcode==`LFD
|
;
|
;
|
wire xIsStore =
|
wire xIsStore =
|
xOpcode==`SW || xOpcode==`SH || xOpcode==`SB || xOpcode==`SC || xOpcode==`SWC ||
|
xOpcode==`SW || xOpcode==`SH || xOpcode==`SB || xOpcode==`SC || xOpcode==`SWC || xOpcode==`SM ||
|
|
xOpcode==`SF || xOpcode==`SFD ||
|
xOpcode==`OUTW || xOpcode==`OUTH || xOpcode==`OUTB || xOpcode==`OUTC
|
xOpcode==`OUTW || xOpcode==`OUTH || xOpcode==`OUTB || xOpcode==`OUTC
|
;
|
;
|
wire xIsSWC = xOpcode==`SWC;
|
wire xIsSWC = xOpcode==`SWC;
|
wire xIsIn =
|
wire xIsIn =
|
xOpcode==`INW || xOpcode==`INH || xOpcode==`INCH || xOpcode==`INB
|
xOpcode==`INW || xOpcode==`INH || xOpcode==`INCH || xOpcode==`INB
|
;
|
;
|
//wire mIsSWC = mOpcode==`SWC;
|
//wire mIsSWC = mOpcode==`SWC;
|
|
|
//wire mIsLoad =
|
//wire mIsLoad =
|
// mOpcode==`LW || mOpcode==`LH || mOpcode==`LB || mOpcode==`LC || mOpcode==`LWR ||
|
// mOpcode==`LW || mOpcode==`LH || mOpcode==`LB || mOpcode==`LC || mOpcode==`LWR ||
|
// mOpcode==`LHU || mOpcode==`LBU || mOpcode==`LCU ||
|
// mOpcode==`LHU || mOpcode==`LBU || mOpcode==`LCU ||
|
// mOpcode==`INW || mOpcode==`INB || mOpcode==`INH
|
// mOpcode==`INW || mOpcode==`INB || mOpcode==`INH
|
// ;
|
// ;
|
wire m1IsLoad =
|
wire m1IsLoad =
|
m1Opcode==`LW || m1Opcode==`LH || m1Opcode==`LB || m1Opcode==`LC || m1Opcode==`LWR ||
|
m1Opcode==`LW || m1Opcode==`LH || m1Opcode==`LB || m1Opcode==`LC || m1Opcode==`LWR ||
|
m1Opcode==`LHU || m1Opcode==`LBU || m1Opcode==`LCU
|
m1Opcode==`LHU || m1Opcode==`LBU || m1Opcode==`LCU || m1Opcode==`LM ||
|
|
m1Opcode==`LF || m1Opcode==`LFD
|
;
|
;
|
wire m1IsIn =
|
wire m1IsIn =
|
m1Opcode==`INW || m1Opcode==`INH || m1Opcode==`INCH || m1Opcode==`INB
|
m1Opcode==`INW || m1Opcode==`INH || m1Opcode==`INCH || m1Opcode==`INB
|
;
|
;
|
wire m2IsInW = m2Opcode==`INW;
|
wire m2IsInW = m2Opcode==`INW;
|
wire m1IsStore =
|
wire m1IsStore = m1Opcode==`SW || m1Opcode==`SH || m1Opcode==`SB || m1Opcode==`SC || m1Opcode==`SWC || m1Opcode==`SM ||
|
m1Opcode==`SW || m1Opcode==`SH || m1Opcode==`SB || m1Opcode==`SC || m1Opcode==`SWC
|
m1Opcode==`SF || m1Opcode==`SFD;
|
;
|
wire m2IsStore = m2Opcode==`SW || m2Opcode==`SWC || m2Opcode==`SH || m2Opcode==`SC || m2Opcode==`SB || m2Opcode==`SM ||
|
|
m2Opcode==`SF || m2Opcode==`SFD;
|
wire xIsIO =
|
wire xIsIO =
|
xIsIn ||
|
xIsIn ||
|
xOpcode==`OUTW || xOpcode==`OUTH || xOpcode==`OUTC || xOpcode==`OUTB
|
xOpcode==`OUTW || xOpcode==`OUTH || xOpcode==`OUTC || xOpcode==`OUTB
|
;
|
;
|
wire m1IsIO =
|
wire m1IsIO =
|
m1IsIn ||
|
m1IsIn ||
|
m1Opcode==`OUTW || m1Opcode==`OUTH || m1Opcode==`OUTC || m1Opcode==`OUTB
|
m1Opcode==`OUTW || m1Opcode==`OUTH || m1Opcode==`OUTC || m1Opcode==`OUTB
|
;
|
;
|
wire m2IsLoad =
|
wire m2IsLoad =
|
m2Opcode==`LW || m2Opcode==`LH || m2Opcode==`LB || m2Opcode==`LC || m2Opcode==`LWR ||
|
m2Opcode==`LW || m2Opcode==`LH || m2Opcode==`LB || m2Opcode==`LC || m2Opcode==`LWR ||
|
m2Opcode==`LHU || m2Opcode==`LBU || m2Opcode==`LCU
|
m2Opcode==`LHU || m2Opcode==`LBU || m2Opcode==`LCU || m2Opcode==`LM ||
|
|
m2Opcode==`LF || m2Opcode==`LFD
|
;
|
;
|
wire m2IsStore =
|
|
m2Opcode==`SW || m2Opcode==`SWC || m2Opcode==`SH || m2Opcode==`SC || m2Opcode==`SB;
|
|
|
|
wire xIsFPLoo = xOpcode==`FPLOO;
|
wire xIsFPLoo = xOpcode==`FPLOO;
|
|
|
wire xneedBus = xIsIO;
|
wire xneedBus = xIsIO;
|
wire m1needBus = (m1IsLoad & !m1IsCacheElement) || m1IsStore || m1IsIO;
|
wire m1needBus = (m1IsLoad & !m1IsCacheElement) || m1IsStore || m1IsIO;
|
wire m2needBus = (m2IsLoad | m2IsStore);
|
wire m2needBus = (m2IsLoad | m2IsStore);
|
|
|
// Stall on SWC allows rsf flag to be loaded for the next instruction
|
// Stall on SWC allows rsf flag to be loaded for the next instruction
|
// Currently stalls on load of R0, but doesn't need to.
|
// Currently stalls on load of R0, but doesn't need to.
|
wire StallR = (((xIsLoad||xIsIn) && ((xRt==dRa)||(xRt==dRb)||(xRt==dRt))) || xIsSWC) ||
|
wire StallR = (((xIsLoad||xIsIn) && ((xRt==dRa)||(xRt==dRb)||(xRt==dRt))) || xIsSWC) ||
|
(((m1IsLoad||m1IsIn) && ((m1Rt==dRa)||(m1Rt==dRb)||(m1Rt==dRt)))) ||
|
(((m1IsLoad||m1IsIn) && ((m1Rt==dRa)||(m1Rt==dRb)||(m1Rt==dRt)))) ||
|
(((m2IsLoad) && ((m2Rt==dRa)||(m2Rt==dRb)||(m2Rt==dRt))))
|
(((m2IsLoad) && ((m2Rt==dRa)||(m2Rt==dRb)||(m2Rt==dRt))))
|
;
|
;
|
wire StallX = xneedBus & (m1needBus|m2needBus|icaccess|dcaccess);
|
wire StallX = xneedBus & (m1needBus|m2needBus|icaccess|dcaccess);
|
wire StallM1 = m1needBus & (m2needBus|icaccess|dcaccess);
|
wire StallM1 = (m1needBus & (m2needBus|icaccess|dcaccess)) ||
|
|
( m1IsLoad & m1IsCacheElement & m2IsStore) // wait for a preceding store to complete
|
|
;
|
wire StallM2 = icaccess|dcaccess;
|
wire StallM2 = icaccess|dcaccess;
|
|
|
wire advanceT = !resetA;
|
wire advanceT = !resetA;
|
wire advanceW = advanceT;
|
wire advanceW = advanceT;
|
wire advanceM2 = advanceW &&
|
wire advanceM2 = advanceW &&
|
((m2IsLoad || m2IsStore) ? ack_i : 1'b1) &&
|
((m2IsLoad || m2IsStore) ? ack_i : 1'b1) &&
|
!StallM2
|
!StallM2
|
;
|
;
|
wire advanceM1 = advanceM2 &
|
wire advanceM1 = advanceM2 &
|
(m1IsIO ? ack_i : 1'b1) &
|
(m1IsIO ? ack_i : 1'b1) &
|
((m1IsLoad & m1IsCacheElement) ? dhit : 1'b1) &
|
((m1IsLoad & m1IsCacheElement) ? dhit : 1'b1) &
|
!StallM1
|
!StallM1
|
;
|
;
|
wire advanceX = advanceM1 & (
|
wire advanceX = advanceM1 & (
|
xIsSqrt ? sqrt_done :
|
xIsSqrt ? sqrt_done :
|
xIsMult ? mult_done :
|
xIsMult ? mult_done :
|
xIsDiv ? div_done :
|
xIsDiv ? div_done :
|
xIsFPLoo ? fpLooDone :
|
xIsFPLoo ? fpLooDone :
|
1'b1) &
|
1'b1) &
|
!StallX;
|
!StallX;
|
wire advanceR = advanceX & !StallR;
|
wire advanceR = advanceX & !StallR;
|
wire advanceI = advanceR & (ICacheOn ? ihit : ibufrdy);
|
wire advanceI = advanceR & (ICacheOn ? ihit : ibufrdy);
|
|
|
wire triggerDCacheLoad = (m1IsLoad & m1IsCacheElement & !dhit) && // there is a miss
|
wire triggerDCacheLoad = (m1IsLoad & m1IsCacheElement & !dhit) && // there is a miss
|
!(icaccess | dcaccess) && // caches are not active
|
!(icaccess | dcaccess) && // caches are not active
|
m2Opcode==`NOPI // and the pipeline is free of memory-ops
|
m2Opcode==`NOPI // and the pipeline is free of memory-ops
|
;
|
;
|
// Since IMM is "sticky" we have to check for it.
|
// Since IMM is "sticky" we have to check for it.
|
wire triggerICacheLoad = (ICacheAct ? !ihit : !ibufrdy) && !triggerDCacheLoad && // There is a miss
|
wire triggerICacheLoad1 = ICacheAct && !ihit && !triggerDCacheLoad && // There is a miss
|
!(icaccess | dcaccess) && // caches are not active
|
!(icaccess | dcaccess) && // caches are not active
|
(dOpcode==`NOPI || dOpcode[6:4]==`IMM) && // and the pipeline is flushed
|
(dOpcode==`NOPI || dOpcode[6:4]==`IMM) && // and the pipeline is flushed
|
(xOpcode==`NOPI || xOpcode[6:4]==`IMM) &&
|
(xOpcode==`NOPI || xOpcode[6:4]==`IMM) &&
|
m1Opcode==`NOPI &&
|
m1Opcode==`NOPI &&
|
m2Opcode==`NOPI
|
m2Opcode==`NOPI
|
;
|
;
|
|
wire triggerICacheLoad2 = (!ICacheAct && !ibufrdy) && !triggerDCacheLoad && // There is a miss
|
|
!(icaccess | dcaccess) // caches are not active
|
|
;
|
|
wire triggerICacheLoad = triggerICacheLoad1 | triggerICacheLoad2;
|
|
|
wire EXexception_pending = ovr_error || dbz_error || priv_violation || xOpcode==`TRAPcci || xOpcode==`TRAPcc;
|
wire EXexception_pending = ovr_error || dbz_error || priv_violation || xOpcode==`TRAPcci || xOpcode==`TRAPcc;
|
`ifdef TLB
|
`ifdef TLB
|
wire M1exception_pending = advanceM1 & (m1IsLoad|m1IsStore) & DTLBMiss;
|
wire M1exception_pending = advanceM1 & (m1IsLoad|m1IsStore) & DTLBMiss;
|
`else
|
`else
|
wire M1exception_pending = 1'b0;
|
wire M1exception_pending = 1'b0;
|
`endif
|
`endif
|
wire exception_pending = EXexception_pending | M1exception_pending;
|
wire exception_pending = EXexception_pending | M1exception_pending;
|
|
|
wire xWillLoadStore = (xIsLoad||xIsStore) & advanceX;
|
|
wire stallCacheLoad = xWillLoadStore;
|
|
|
|
reg prev_nmi,nmi_edge;
|
reg prev_nmi,nmi_edge;
|
|
|
|
always @(dOpcode or dIR)
|
|
begin
|
|
ndIR <= dIR;
|
|
if ((dOpcode==`LM || dOpcode==`SM) && dIR[31:0]!=32'd0) begin
|
|
$display("LM/SM %h",dIR[31:0]);
|
|
if (dIR[0])
|
|
ndIR[0] <= 1'b0;
|
|
else if (dIR[1])
|
|
ndIR[1] <= 1'b0;
|
|
else if (dIR[2])
|
|
ndIR[2] <= 1'b0;
|
|
else if (dIR[3])
|
|
ndIR[3] <= 1'b0;
|
|
else if (dIR[4])
|
|
ndIR[4] <= 1'b0;
|
|
else if (dIR[5])
|
|
ndIR[5] <= 1'b0;
|
|
else if (dIR[6])
|
|
ndIR[6] <= 1'b0;
|
|
else if (dIR[7])
|
|
ndIR[7] <= 1'b0;
|
|
else if (dIR[8])
|
|
ndIR[8] <= 1'b0;
|
|
else if (dIR[9])
|
|
ndIR[9] <= 1'b0;
|
|
else if (dIR[10])
|
|
ndIR[10] <= 1'b0;
|
|
else if (dIR[11])
|
|
ndIR[11] <= 1'b0;
|
|
else if (dIR[12])
|
|
ndIR[12] <= 1'b0;
|
|
else if (dIR[13])
|
|
ndIR[13] <= 1'b0;
|
|
else if (dIR[14])
|
|
ndIR[14] <= 1'b0;
|
|
else if (dIR[15])
|
|
ndIR[15] <= 1'b0;
|
|
else if (dIR[16])
|
|
ndIR[16] <= 1'b0;
|
|
else if (dIR[17])
|
|
ndIR[17] <= 1'b0;
|
|
else if (dIR[18])
|
|
ndIR[18] <= 1'b0;
|
|
else if (dIR[19])
|
|
ndIR[19] <= 1'b0;
|
|
else if (dIR[20])
|
|
ndIR[20] <= 1'b0;
|
|
else if (dIR[21])
|
|
ndIR[21] <= 1'b0;
|
|
else if (dIR[22])
|
|
ndIR[22] <= 1'b0;
|
|
else if (dIR[23])
|
|
ndIR[23] <= 1'b0;
|
|
else if (dIR[24])
|
|
ndIR[24] <= 1'b0;
|
|
else if (dIR[25])
|
|
ndIR[25] <= 1'b0;
|
|
else if (dIR[26])
|
|
ndIR[26] <= 1'b0;
|
|
else if (dIR[27])
|
|
ndIR[27] <= 1'b0;
|
|
else if (dIR[28])
|
|
ndIR[28] <= 1'b0;
|
|
else if (dIR[29])
|
|
ndIR[29] <= 1'b0;
|
|
else if (dIR[30])
|
|
ndIR[30] <= 1'b0;
|
|
else
|
|
ndIR[31] <= 1'b0;
|
|
end
|
|
end
|
|
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
// Register file.
|
// Register file.
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
|
|
syncRam512x64_1rw3r u5
|
syncRam512x64_1rw3r u5
|
(
|
(
|
.wrst(1'b0),
|
.wrst(1'b0),
|
.wclk(clk),
|
.wclk(clk),
|
.wce(advanceW),
|
.wce(advanceW),
|
.we(1'b1),
|
.we(1'b1),
|
.wadr(wRt),
|
.wadr(wRt),
|
.i(wData),
|
.i(wData),
|
.wo(),
|
.wo(),
|
|
|
.rrsta(1'b0),
|
.rrsta(1'b0),
|
.rclka(~clk),
|
.rclka(~clk),
|
.rcea(advanceR),
|
.rcea(advanceR),
|
.radra(dRa),
|
.radra(dRa),
|
.roa(rfoa),
|
.roa(rfoa),
|
|
|
.rrstb(1'b0),
|
.rrstb(1'b0),
|
.rclkb(~clk),
|
.rclkb(~clk),
|
.rceb(advanceR),
|
.rceb(advanceR),
|
.radrb(dRb),
|
.radrb(dRb),
|
.rob(rfob),
|
.rob(rfob),
|
|
|
.rrstc(1'b0),
|
.rrstc(1'b0),
|
.rclkc(~clk),
|
.rclkc(~clk),
|
.rcec(advanceR),
|
.rcec(advanceR),
|
.radrc(dRc),
|
.radrc(dRc),
|
.roc(rfoc)
|
.roc(rfoc)
|
);
|
);
|
|
|
|
|
reg m1clkoff,m2clkoff,m3clkoff,m4clkoff,wclkoff;
|
reg m1clkoff,m2clkoff,m3clkoff,m4clkoff,wclkoff;
|
reg dFip,xFip,m1Fip,m2Fip,m3Fip,m4Fip,wFip;
|
reg dFip,xFip,m1Fip,m2Fip,m3Fip,m4Fip,wFip;
|
|
reg cyc1;
|
|
|
|
reg [63:0] nxt_c;
|
|
always @(dRc or xData or m1Data or m2Data or wData or tData or rfoc)
|
|
casex(dRc)
|
|
9'bxxxx00000: nxt_c <= 64'd0;
|
|
xRt: nxt_c <= xData;
|
|
m1Rt: nxt_c <= m1Data;
|
|
m2Rt: nxt_c <= m2Data;
|
|
wRt: nxt_c <= wData;
|
|
tRt: nxt_c <= tData;
|
|
default: nxt_c <= rfoc;
|
|
endcase
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
if (rst_i) begin
|
if (rst_i) begin
|
bte_o <= 2'b00;
|
bte_o <= 2'b00;
|
cti_o <= 3'b000;
|
cti_o <= 3'b000;
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
we_o <= 1'b0;
|
we_o <= 1'b0;
|
sel_o <= 8'h00;
|
sel_o <= 8'h00;
|
adr_o <= 64'd0;
|
adr_o <= 64'd0;
|
dat_o <= 64'd0;
|
dat_o <= 64'd0;
|
dccyc <= 1'b0;
|
dccyc <= 1'b0;
|
|
|
nonICacheSeg <= 32'hFFFF_FFFD;
|
nonICacheSeg <= 32'hFFFF_FFFD;
|
TBA <= 64'd0;
|
TBA <= 64'd0;
|
pc <= `RESET_VECTOR;
|
pc <= `RESET_VECTOR;
|
m1Opcode <= `NOPI;
|
m1Opcode <= `NOPI;
|
m2Opcode <= `NOPI;
|
m2Opcode <= `NOPI;
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
dRt <= 9'd0;
|
dRt <= 9'd0;
|
tRt <= 9'd0;
|
tRt <= 9'd0;
|
wRt <= 9'd0;
|
wRt <= 9'd0;
|
m1Rt <= 9'd0;
|
m1Rt <= 9'd0;
|
m2Rt <= 9'd0;
|
m2Rt <= 9'd0;
|
tData <= 64'd0;
|
tData <= 64'd0;
|
wData <= 64'd0;
|
wData <= 64'd0;
|
m1Data <= 64'd0;
|
m1Data <= 64'd0;
|
m2Data <= 64'd0;
|
m2Data <= 64'd0;
|
icaccess <= 1'b0;
|
icaccess <= 1'b0;
|
dcaccess <= 1'b0;
|
dcaccess <= 1'b0;
|
nopI <= 1'b0;
|
nopI <= 1'b0;
|
prev_ihit <= 1'b0;
|
prev_ihit <= 1'b0;
|
dhwxtype <= 2'b00;
|
dhwxtype <= 2'b00;
|
xhwxtype <= 2'b00;
|
xhwxtype <= 2'b00;
|
m1hwxtype <= 2'b00;
|
m1hwxtype <= 2'b00;
|
m2hwxtype <= 2'b00;
|
m2hwxtype <= 2'b00;
|
whwxtype <= 2'b00;
|
whwxtype <= 2'b00;
|
wFip <= 1'b0;
|
wFip <= 1'b0;
|
m2Fip <= 1'b0;
|
m2Fip <= 1'b0;
|
m1Fip <= 1'b0;
|
m1Fip <= 1'b0;
|
xFip <= 1'b0;
|
xFip <= 1'b0;
|
dFip <= 1'b0;
|
dFip <= 1'b0;
|
dirqf <= 1'b0;
|
dirqf <= 1'b0;
|
dpcv <= 1'b0;
|
dpcv <= 1'b0;
|
xpcv <= 1'b0;
|
xpcv <= 1'b0;
|
m1pcv <= 1'b0;
|
m1pcv <= 1'b0;
|
m2pcv <= 1'b0;
|
m2pcv <= 1'b0;
|
wpcv <= 1'b0;
|
wpcv <= 1'b0;
|
tick <= 32'd0;
|
tick <= 32'd0;
|
cstate <= IDLE;
|
cstate <= IDLE;
|
dImm <= 64'd0;
|
dImm <= 64'd0;
|
AXC <= 4'd0;
|
AXC <= 4'd0;
|
dAXC <= 4'd0;
|
dAXC <= 4'd0;
|
xirqf <= 1'b0;
|
xirqf <= 1'b0;
|
xextype <= 8'h00;
|
xextype <= 8'h00;
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xpc <= 64'd0;
|
xpc <= 64'd0;
|
a <= 64'd0;
|
a <= 64'd0;
|
b <= 64'd0;
|
b <= 64'd0;
|
imm <= 64'd0;
|
imm <= 64'd0;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
clk_en <= 1'b1;
|
clk_en <= 1'b1;
|
`ifdef TLB
|
`ifdef TLB
|
Random <= 4'hF;
|
Random <= 4'hF;
|
Wired <= 4'd0;
|
Wired <= 4'd0;
|
`endif
|
`endif
|
StatusEXL <= 1'b1;
|
StatusEXL <= 1'b1;
|
StatusHWI <= 1'b0;
|
StatusHWI <= 1'b0;
|
resetA <= 1'b1;
|
resetA <= 1'b1;
|
mutex_gate <= 64'h0;
|
mutex_gate <= 64'h0;
|
`ifndef BRANCH_PREDICTION_SIMPLE
|
`ifndef BRANCH_PREDICTION_SIMPLE
|
gbl_branch_hist <= 3'b000;
|
gbl_branch_hist <= 3'b000;
|
`endif
|
`endif
|
|
dcache_on <= 1'b0;
|
ICacheOn <= 1'b0;
|
ICacheOn <= 1'b0;
|
ibuftag <= 64'h0;
|
ibuftag0 <= 64'h0;
|
|
ibuftag1 <= 64'h0;
|
m1IsCacheElement <= 1'b0;
|
m1IsCacheElement <= 1'b0;
|
dtinit <= 1'b1;
|
dtinit <= 1'b1;
|
`ifdef RAS_PREDICTION
|
`ifdef RAS_PREDICTION
|
ras_sp <= 6'd63;
|
ras_sp <= 6'd63;
|
`endif
|
`endif
|
|
im <= 1'b1;
|
|
im1 <= 1'b1;
|
end
|
end
|
else begin
|
else begin
|
|
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
// Initialize program counters
|
// Initialize program counters
|
// Initialize data tags to zero.
|
// Initialize data tags to zero.
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
if (resetA) begin
|
if (resetA) begin
|
pc <= `RESET_VECTOR;
|
pc <= `RESET_VECTOR;
|
adr_o[14:6] <= adr_o[14:6]+9'd1;
|
adr_o[14:6] <= adr_o[14:6]+9'd1;
|
if (adr_o[14:6]==9'h1FF) begin
|
if (adr_o[14:6]==9'h1FF) begin
|
dtinit <= 1'b0;
|
dtinit <= 1'b0;
|
resetA <= 1'b0;
|
resetA <= 1'b0;
|
end
|
end
|
end
|
end
|
|
|
`ifdef TLB
|
`ifdef TLB
|
if (Random==Wired)
|
if (Random==Wired)
|
Random <= 3'd7;
|
Random <= 3'd7;
|
else
|
else
|
Random <= Random - 3'd1;
|
Random <= Random - 3'd1;
|
`endif
|
`endif
|
|
|
tick <= tick + 64'd1;
|
tick <= tick + 64'd1;
|
|
|
prev_nmi <= nmi_i;
|
prev_nmi <= nmi_i;
|
if (!prev_nmi & nmi_i)
|
if (!prev_nmi & nmi_i)
|
nmi_edge <= 1'b1;
|
nmi_edge <= 1'b1;
|
|
|
|
|
|
`ifdef ADDRESS_RESERVATION
|
// A store by any device in the system to a reserved address blcok
|
// A store by any device in the system to a reserved address blcok
|
// clears the reservation.
|
// clears the reservation.
|
|
|
if (sys_adv && sys_adr[63:5]==resv_address)
|
if (sys_adv && sys_adr[63:5]==resv_address)
|
resv_address <= 59'd0;
|
resv_address <= 59'd0;
|
|
`endif
|
|
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
// TRAILER:
|
// TRAILER:
|
// - placeholder to allow the use of synchronous register
|
// - placeholder to allow the use of synchronous register
|
// memory
|
// memory
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
if (advanceT) begin
|
if (advanceT) begin
|
tRt <= 9'd0;
|
tRt <= 9'd0;
|
tData <= 64'd0;
|
tData <= 64'd0;
|
end
|
end
|
|
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
// WRITEBACK:
|
// WRITEBACK:
|
// - update the register file with results
|
// - update the register file with results
|
// - record exception address and type
|
// - record exception address and type
|
// - jump to exception handler routine (below)
|
// - jump to exception handler routine (below)
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
if (advanceW) begin
|
if (advanceW) begin
|
textype <= wextype;
|
textype <= wextype;
|
wextype <= `EX_NON;
|
wextype <= `EX_NON;
|
tRt <= wRt;
|
tRt <= wRt;
|
tData <= wData;
|
tData <= wData;
|
if (wRt!=5'd0)
|
if (wRt!=5'd0)
|
$display("Writing regfile[%d:%d] with %h", wRt[8:5],wRt[4:0], wData);
|
$display("Writing regfile[%d:%d] with %h", wRt[8:5],wRt[4:0], wData);
|
wRt <= 9'd0;
|
wRt <= 9'd0;
|
wData <= 64'd0;
|
wData <= 64'd0;
|
if (|whwxtype) begin
|
if (|whwxtype) begin
|
dhwxtype <= 2'b00;
|
dhwxtype <= 2'b00;
|
xhwxtype <= 2'b00;
|
xhwxtype <= 2'b00;
|
m1hwxtype <= 2'b00;
|
m1hwxtype <= 2'b00;
|
m2hwxtype <= 2'b00;
|
m2hwxtype <= 2'b00;
|
whwxtype <= 2'b00;
|
whwxtype <= 2'b00;
|
end
|
end
|
clk_en <= 1'b1;
|
clk_en <= 1'b1;
|
if (wclkoff)
|
if (wclkoff)
|
clk_en <= 1'b0;
|
clk_en <= 1'b0;
|
wclkoff <= 1'b0;
|
wclkoff <= 1'b0;
|
m1clkoff <= 1'b0;
|
m1clkoff <= 1'b0;
|
m2clkoff <= 1'b0;
|
m2clkoff <= 1'b0;
|
if (wFip) begin
|
if (wFip) begin
|
wFip <= 1'b0;
|
wFip <= 1'b0;
|
m2Fip <= 1'b0;
|
m2Fip <= 1'b0;
|
m1Fip <= 1'b0;
|
m1Fip <= 1'b0;
|
xFip <= 1'b0;
|
xFip <= 1'b0;
|
dFip <= 1'b0;
|
dFip <= 1'b0;
|
end
|
end
|
end
|
end
|
|
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
// MEMORY:
|
// MEMORY:
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
if (advanceM2) begin
|
if (advanceM2) begin
|
wData <= m2Data;
|
wData <= m2Data;
|
whwxtype <= m2hwxtype;
|
whwxtype <= m2hwxtype;
|
wextype <= m2extype;
|
wextype <= m2extype;
|
wRt <= m2Rt;
|
wRt <= m2Rt;
|
wpc <= m2pc;
|
wpc <= m2pc;
|
wpcv <= m2pcv;
|
wpcv <= m2pcv;
|
wclkoff <= m2clkoff;
|
wclkoff <= m2clkoff;
|
wFip <= m2Fip;
|
wFip <= m2Fip;
|
|
|
m2Rt <= 9'd0;
|
m2Rt <= 9'd0;
|
m2Opcode <= `NOPI;
|
m2Opcode <= `NOPI;
|
m2Func <= 7'd0;
|
m2Func <= 7'd0;
|
m2Addr <= 64'd0;
|
m2Addr <= 64'd0;
|
m2Data <= 64'd0;
|
m2Data <= 64'd0;
|
m2clkoff <= 1'b0;
|
m2clkoff <= 1'b0;
|
m2pc <= 64'd0;
|
m2pc <= 64'd0;
|
m2extype <= `EX_NON;
|
m2extype <= `EX_NON;
|
if (m2extype==`EX_NON) begin
|
if (m2extype==`EX_NON) begin
|
case(m2Opcode)
|
case(m2Opcode)
|
`SH,`SC,`SB,`SW,`SWC:
|
`SH,`SC,`SB,`SW,`SWC,`SM,`SF,`SFD:
|
begin
|
begin
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
we_o <= 1'b0;
|
we_o <= 1'b0;
|
sel_o <= 4'h0;
|
sel_o <= 4'h0;
|
end
|
end
|
`LH:
|
`LH,`LF:
|
begin
|
begin
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
sel_o <= 8'h00;
|
sel_o <= 8'h00;
|
wData <= sel_o[7] ? {{32{dat_i[63]}},dat_i[63:32]}:{{32{dat_i[31]}},dat_i[31: 0]};
|
wData <= sel_o[7] ? {{32{dat_i[63]}},dat_i[63:32]}:{{32{dat_i[31]}},dat_i[31: 0]};
|
end
|
end
|
`LW,`LWR:
|
`LW,`LWR,`LM,`LFD:
|
begin
|
begin
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
sel_o <= 8'h00;
|
sel_o <= 8'h00;
|
wData <= dat_i;
|
wData <= dat_i;
|
end
|
end
|
`LHU:
|
`LHU:
|
begin
|
begin
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
sel_o <= 8'h00;
|
sel_o <= 8'h00;
|
wData <= sel_o[7] ? dat_i[63:32] : dat_i[31: 0];
|
wData <= sel_o[7] ? dat_i[63:32] : dat_i[31: 0];
|
end
|
end
|
`LC:
|
`LC:
|
begin
|
begin
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
sel_o <= 8'h00;
|
sel_o <= 8'h00;
|
case(sel_o)
|
case(sel_o)
|
8'b00000011: wData <= {{48{dat_i[15]}},dat_i[15: 0]};
|
8'b00000011: wData <= {{48{dat_i[15]}},dat_i[15: 0]};
|
8'b00001100: wData <= {{48{dat_i[31]}},dat_i[31:16]};
|
8'b00001100: wData <= {{48{dat_i[31]}},dat_i[31:16]};
|
8'b00110000: wData <= {{48{dat_i[47]}},dat_i[47:32]};
|
8'b00110000: wData <= {{48{dat_i[47]}},dat_i[47:32]};
|
8'b11000000: wData <= {{48{dat_i[63]}},dat_i[63:48]};
|
8'b11000000: wData <= {{48{dat_i[63]}},dat_i[63:48]};
|
default: wData <= 64'hDEADDEADDEADDEAD;
|
default: wData <= 64'hDEADDEADDEADDEAD;
|
endcase
|
endcase
|
end
|
end
|
`LCU:
|
`LCU:
|
begin
|
begin
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
sel_o <= 8'h00;
|
sel_o <= 8'h00;
|
case(sel_o)
|
case(sel_o)
|
8'b00000011: wData <= dat_i[15: 0];
|
8'b00000011: wData <= dat_i[15: 0];
|
8'b00001100: wData <= dat_i[31:16];
|
8'b00001100: wData <= dat_i[31:16];
|
8'b00110000: wData <= dat_i[47:32];
|
8'b00110000: wData <= dat_i[47:32];
|
8'b11000000: wData <= dat_i[63:48];
|
8'b11000000: wData <= dat_i[63:48];
|
default: wData <= 64'hDEADDEADDEADDEAD;
|
default: wData <= 64'hDEADDEADDEADDEAD;
|
endcase
|
endcase
|
end
|
end
|
`LB:
|
`LB:
|
begin
|
begin
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
sel_o <= 8'h00;
|
sel_o <= 8'h00;
|
case(sel_o)
|
case(sel_o)
|
8'b00000001: wData <= {{56{dat_i[ 7]}},dat_i[ 7: 0]};
|
8'b00000001: wData <= {{56{dat_i[ 7]}},dat_i[ 7: 0]};
|
8'b00000010: wData <= {{56{dat_i[15]}},dat_i[15: 8]};
|
8'b00000010: wData <= {{56{dat_i[15]}},dat_i[15: 8]};
|
8'b00000100: wData <= {{56{dat_i[23]}},dat_i[23:16]};
|
8'b00000100: wData <= {{56{dat_i[23]}},dat_i[23:16]};
|
8'b00001000: wData <= {{56{dat_i[31]}},dat_i[31:24]};
|
8'b00001000: wData <= {{56{dat_i[31]}},dat_i[31:24]};
|
8'b00010000: wData <= {{56{dat_i[39]}},dat_i[39:32]};
|
8'b00010000: wData <= {{56{dat_i[39]}},dat_i[39:32]};
|
8'b00100000: wData <= {{56{dat_i[47]}},dat_i[47:40]};
|
8'b00100000: wData <= {{56{dat_i[47]}},dat_i[47:40]};
|
8'b01000000: wData <= {{56{dat_i[55]}},dat_i[55:48]};
|
8'b01000000: wData <= {{56{dat_i[55]}},dat_i[55:48]};
|
8'b10000000: wData <= {{56{dat_i[63]}},dat_i[63:56]};
|
8'b10000000: wData <= {{56{dat_i[63]}},dat_i[63:56]};
|
default: wData <= 64'hDEADDEADDEADDEAD;
|
default: wData <= 64'hDEADDEADDEADDEAD;
|
endcase
|
endcase
|
end
|
end
|
`LBU:
|
`LBU:
|
begin
|
begin
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
sel_o <= 8'h00;
|
sel_o <= 8'h00;
|
case(sel_o)
|
case(sel_o)
|
8'b00000001: wData <= dat_i[ 7: 0];
|
8'b00000001: wData <= dat_i[ 7: 0];
|
8'b00000010: wData <= dat_i[15: 8];
|
8'b00000010: wData <= dat_i[15: 8];
|
8'b00000100: wData <= dat_i[23:16];
|
8'b00000100: wData <= dat_i[23:16];
|
8'b00001000: wData <= dat_i[31:24];
|
8'b00001000: wData <= dat_i[31:24];
|
8'b00010000: wData <= dat_i[39:32];
|
8'b00010000: wData <= dat_i[39:32];
|
8'b00100000: wData <= dat_i[47:40];
|
8'b00100000: wData <= dat_i[47:40];
|
8'b01000000: wData <= dat_i[55:48];
|
8'b01000000: wData <= dat_i[55:48];
|
8'b10000000: wData <= dat_i[63:56];
|
8'b10000000: wData <= dat_i[63:56];
|
default: wData <= 64'hDEADDEADDEADDEAD;
|
default: wData <= 64'hDEADDEADDEADDEAD;
|
endcase
|
endcase
|
end
|
end
|
default: ;
|
default: ;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
wrhit <= 1'b0;
|
wrhit <= 1'b0;
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
// MEMORY:
|
// MEMORY:
|
// - I/O instructions are finished
|
// - I/O instructions are finished
|
// - store instructions are started
|
// - store instructions are started
|
// - missed loads are started
|
// - missed loads are started
|
// On a data cache hit for a load, the load is essentially
|
// On a data cache hit for a load, the load is essentially
|
// finished in this stage. We switch the opcode to 'NOPI'
|
// finished in this stage. We switch the opcode to 'NOPI'
|
// to cause the pipeline to advance as if a NOPs were
|
// to cause the pipeline to advance as if a NOPs were
|
// present.
|
// present.
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
if (advanceM1) begin
|
if (advanceM1) begin
|
m2Opcode <= m1Opcode;
|
m2Opcode <= m1Opcode;
|
m2Func <= m1Func;
|
m2Func <= m1Func;
|
m2Addr <= pea;
|
m2Addr <= pea;
|
m2Data <= m1Data;
|
m2Data <= m1Data;
|
m2hwxtype <= m1hwxtype;
|
m2hwxtype <= m1hwxtype;
|
m2extype <= m1extype;
|
m2extype <= m1extype;
|
m2Rt <= m1Rt;
|
m2Rt <= m1Rt;
|
m2pc <= m1pc;
|
m2pc <= m1pc;
|
m2pcv <= m1pcv;
|
m2pcv <= m1pcv;
|
m2clkoff <= m1clkoff;
|
m2clkoff <= m1clkoff;
|
m2Fip <= m1Fip;
|
m2Fip <= m1Fip;
|
|
|
m1Rt <= 9'd0;
|
m1Rt <= 9'd0;
|
m1Opcode <= `NOPI;
|
m1Opcode <= `NOPI;
|
m1Func <= 7'd0;
|
m1Func <= 7'd0;
|
m1Data <= 64'd0;
|
m1Data <= 64'd0;
|
m1clkoff <= 1'b0;
|
m1clkoff <= 1'b0;
|
m1pc <= 64'd0;
|
m1pc <= 64'd0;
|
m1IsCacheElement <= 1'b0;
|
m1IsCacheElement <= 1'b0;
|
m1extype <= `EX_NON;
|
m1extype <= `EX_NON;
|
|
|
if (m1extype == `EX_NON) begin
|
if (m1extype == `EX_NON) begin
|
case(m1Opcode)
|
case(m1Opcode)
|
`MISC:
|
`MISC:
|
case(m1Func)
|
case(m1Func)
|
`ifdef TLB
|
`ifdef TLB
|
`TLBP:
|
`TLBP:
|
begin
|
begin
|
Index[63] <= ~|DMatch;
|
Index[63] <= ~|DMatch;
|
end
|
end
|
`TLBR:
|
`TLBR:
|
begin
|
begin
|
TLBPageMask <= ITLBPageMask[i];
|
TLBPageMask <= ITLBPageMask[i];
|
TLBVirtPage <= ITLBVirtPage[i];
|
TLBVirtPage <= ITLBVirtPage[i];
|
TLBPhysPage0 <= ITLBPhysPage0[i];
|
TLBPhysPage0 <= ITLBPhysPage0[i];
|
TLBPhysPage1 <= ITLBPhysPage1[i];
|
TLBPhysPage1 <= ITLBPhysPage1[i];
|
TLBASID <= ITLBASID[i];
|
TLBASID <= ITLBASID[i];
|
TLBG <= ITLBG[i];
|
TLBG <= ITLBG[i];
|
TLBD <= ITLBD[i];
|
TLBD <= ITLBD[i];
|
TLBValid <= ITLBValid[i];
|
TLBValid <= ITLBValid[i];
|
end
|
end
|
`TLBWI,`TLBWR:
|
`TLBWI,`TLBWR:
|
begin
|
begin
|
ITLBValid[i] <= TLBValid;
|
ITLBValid[i] <= TLBValid;
|
ITLBVirtPage[i] <= TLBVirtPage;
|
ITLBVirtPage[i] <= TLBVirtPage;
|
ITLBPhysPage0[i] <= TLBPhysPage0;
|
ITLBPhysPage0[i] <= TLBPhysPage0;
|
ITLBPhysPage1[i] <= TLBPhysPage1;
|
ITLBPhysPage1[i] <= TLBPhysPage1;
|
ITLBPageMask[i] <= TLBPageMask;
|
ITLBPageMask[i] <= TLBPageMask;
|
ITLBASID[i] <= TLBASID;
|
ITLBASID[i] <= TLBASID;
|
ITLBD[i] <= TLBD;
|
ITLBD[i] <= TLBD;
|
ITLBG[i] <= TLBG;
|
ITLBG[i] <= TLBG;
|
end
|
end
|
`endif
|
`endif
|
endcase
|
endcase
|
`INW:
|
`INW:
|
begin
|
begin
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
sel_o <= 8'h00;
|
sel_o <= 8'h00;
|
m2Data <= dat_i;
|
m2Data <= dat_i;
|
m2Opcode <= `NOPI;
|
m2Opcode <= `NOPI;
|
end
|
end
|
`INH:
|
`INH:
|
begin
|
begin
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
sel_o <= 8'h00;
|
sel_o <= 8'h00;
|
m2Data <= sel_o[7] ? {{32{dat_i[63]}},dat_i[63:32]}:{{32{dat_i[31]}},dat_i[31: 0]};
|
m2Data <= sel_o[7] ? {{32{dat_i[63]}},dat_i[63:32]}:{{32{dat_i[31]}},dat_i[31: 0]};
|
m2Opcode <= `NOPI;
|
m2Opcode <= `NOPI;
|
end
|
end
|
`INHU:
|
`INHU:
|
begin
|
begin
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
sel_o <= 8'h00;
|
sel_o <= 8'h00;
|
m2Data <= sel_o[7] ? dat_i[63:32] : dat_i[31: 0];
|
m2Data <= sel_o[7] ? dat_i[63:32] : dat_i[31: 0];
|
m2Opcode <= `NOPI;
|
m2Opcode <= `NOPI;
|
end
|
end
|
`INCH:
|
`INCH:
|
begin
|
begin
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
sel_o <= 8'h00;
|
sel_o <= 8'h00;
|
case(sel_o)
|
case(sel_o)
|
8'b00000011: m2Data <= {{48{dat_i[15]}},dat_i[15: 0]};
|
8'b00000011: m2Data <= {{48{dat_i[15]}},dat_i[15: 0]};
|
8'b00001100: m2Data <= {{48{dat_i[31]}},dat_i[31:16]};
|
8'b00001100: m2Data <= {{48{dat_i[31]}},dat_i[31:16]};
|
8'b00110000: m2Data <= {{48{dat_i[47]}},dat_i[47:32]};
|
8'b00110000: m2Data <= {{48{dat_i[47]}},dat_i[47:32]};
|
8'b11000000: m2Data <= {{48{dat_i[63]}},dat_i[63:48]};
|
8'b11000000: m2Data <= {{48{dat_i[63]}},dat_i[63:48]};
|
default: m2Data <= 64'hDEADDEADDEADDEAD;
|
default: m2Data <= 64'hDEADDEADDEADDEAD;
|
endcase
|
endcase
|
m2Opcode <= `NOPI;
|
m2Opcode <= `NOPI;
|
end
|
end
|
`INCU:
|
`INCU:
|
begin
|
begin
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
sel_o <= 8'h00;
|
sel_o <= 8'h00;
|
case(sel_o)
|
case(sel_o)
|
8'b00000011: m2Data <= dat_i[15: 0];
|
8'b00000011: m2Data <= dat_i[15: 0];
|
8'b00001100: m2Data <= dat_i[31:16];
|
8'b00001100: m2Data <= dat_i[31:16];
|
8'b00110000: m2Data <= dat_i[47:32];
|
8'b00110000: m2Data <= dat_i[47:32];
|
8'b11000000: m2Data <= dat_i[63:48];
|
8'b11000000: m2Data <= dat_i[63:48];
|
default: m2Data <= 64'hDEADDEADDEADDEAD;
|
default: m2Data <= 64'hDEADDEADDEADDEAD;
|
endcase
|
endcase
|
m2Opcode <= `NOPI;
|
m2Opcode <= `NOPI;
|
end
|
end
|
`INB:
|
`INB:
|
begin
|
begin
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
sel_o <= 8'h00;
|
sel_o <= 8'h00;
|
case(sel_o)
|
case(sel_o)
|
8'b00000001: m2Data <= {{56{dat_i[ 7]}},dat_i[ 7: 0]};
|
8'b00000001: m2Data <= {{56{dat_i[ 7]}},dat_i[ 7: 0]};
|
8'b00000010: m2Data <= {{56{dat_i[15]}},dat_i[15: 8]};
|
8'b00000010: m2Data <= {{56{dat_i[15]}},dat_i[15: 8]};
|
8'b00000100: m2Data <= {{56{dat_i[23]}},dat_i[23:16]};
|
8'b00000100: m2Data <= {{56{dat_i[23]}},dat_i[23:16]};
|
8'b00001000: m2Data <= {{56{dat_i[31]}},dat_i[31:24]};
|
8'b00001000: m2Data <= {{56{dat_i[31]}},dat_i[31:24]};
|
8'b00010000: m2Data <= {{56{dat_i[39]}},dat_i[39:32]};
|
8'b00010000: m2Data <= {{56{dat_i[39]}},dat_i[39:32]};
|
8'b00100000: m2Data <= {{56{dat_i[47]}},dat_i[47:40]};
|
8'b00100000: m2Data <= {{56{dat_i[47]}},dat_i[47:40]};
|
8'b01000000: m2Data <= {{56{dat_i[55]}},dat_i[55:48]};
|
8'b01000000: m2Data <= {{56{dat_i[55]}},dat_i[55:48]};
|
8'b10000000: m2Data <= {{56{dat_i[63]}},dat_i[63:56]};
|
8'b10000000: m2Data <= {{56{dat_i[63]}},dat_i[63:56]};
|
default: m2Data <= 64'hDEADDEADDEADDEAD;
|
default: m2Data <= 64'hDEADDEADDEADDEAD;
|
endcase
|
endcase
|
m2Opcode <= `NOPI;
|
m2Opcode <= `NOPI;
|
end
|
end
|
`INBU:
|
`INBU:
|
begin
|
begin
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
sel_o <= 8'h00;
|
sel_o <= 8'h00;
|
case(sel_o)
|
case(sel_o)
|
8'b00000001: m2Data <= dat_i[ 7: 0];
|
8'b00000001: m2Data <= dat_i[ 7: 0];
|
8'b00000010: m2Data <= dat_i[15: 8];
|
8'b00000010: m2Data <= dat_i[15: 8];
|
8'b00000100: m2Data <= dat_i[23:16];
|
8'b00000100: m2Data <= dat_i[23:16];
|
8'b00001000: m2Data <= dat_i[31:24];
|
8'b00001000: m2Data <= dat_i[31:24];
|
8'b00010000: m2Data <= dat_i[39:32];
|
8'b00010000: m2Data <= dat_i[39:32];
|
8'b00100000: m2Data <= dat_i[47:40];
|
8'b00100000: m2Data <= dat_i[47:40];
|
8'b01000000: m2Data <= dat_i[55:48];
|
8'b01000000: m2Data <= dat_i[55:48];
|
8'b10000000: m2Data <= dat_i[63:56];
|
8'b10000000: m2Data <= dat_i[63:56];
|
default: m2Data <= 64'hDEADDEADDEADDEAD;
|
default: m2Data <= 64'hDEADDEADDEADDEAD;
|
endcase
|
endcase
|
m2Opcode <= `NOPI;
|
m2Opcode <= `NOPI;
|
end
|
end
|
`OUTW,`OUTH,`OUTC,`OUTB:
|
`OUTW,`OUTH,`OUTC,`OUTB:
|
begin
|
begin
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
we_o <= 1'b0;
|
we_o <= 1'b0;
|
sel_o <= 8'h00;
|
sel_o <= 8'h00;
|
m2Opcode <= `NOPI;
|
m2Opcode <= `NOPI;
|
end
|
end
|
|
|
`LW:
|
`LW,`LM,`LFD:
|
if (!m1IsCacheElement) begin
|
if (!m1IsCacheElement) begin
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
sel_o <= 8'hFF;
|
sel_o <= 8'hFF;
|
adr_o <= {pea[63:3],3'b000};
|
adr_o <= {pea[63:3],3'b000};
|
m2Addr <= {pea[63:3],3'b000};
|
m2Addr <= {pea[63:3],3'b000};
|
end
|
end
|
else if (dhit) begin
|
else if (dhit) begin
|
m2Opcode <= `NOPI;
|
m2Opcode <= `NOPI;
|
m2Data <= cdat;
|
m2Data <= cdat;
|
end
|
end
|
|
`ifdef ADDRESS_RESERVATION
|
`LWR:
|
`LWR:
|
if (!m1IsCacheElement) begin
|
if (!m1IsCacheElement) begin
|
rsv_o <= 1'b1;
|
rsv_o <= 1'b1;
|
resv_address <= pea[63:5];
|
resv_address <= pea[63:5];
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
sel_o <= 8'hFF;
|
sel_o <= 8'hFF;
|
adr_o <= {pea[63:3],3'b000};
|
adr_o <= {pea[63:3],3'b000};
|
m2Addr <= {pea[63:3],3'b000};
|
m2Addr <= {pea[63:3],3'b000};
|
end
|
end
|
else if (dhit) begin
|
else if (dhit) begin
|
m2Opcode <= `NOPI;
|
m2Opcode <= `NOPI;
|
m2Data <= cdat;
|
m2Data <= cdat;
|
rsv_o <= 1'b1;
|
rsv_o <= 1'b1;
|
resv_address <= pea[63:5];
|
resv_address <= pea[63:5];
|
end
|
end
|
|
`endif
|
`LH:
|
`LH,`LF:
|
if (!m1IsCacheElement) begin
|
if (!m1IsCacheElement) begin
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
sel_o <= pea[2] ? 8'b11110000 : 8'b00001111;
|
sel_o <= pea[2] ? 8'b11110000 : 8'b00001111;
|
adr_o <= {pea[63:2],2'b00};
|
adr_o <= {pea[63:2],2'b00};
|
m2Addr <= {pea[63:2],2'b00};
|
m2Addr <= {pea[63:2],2'b00};
|
end
|
end
|
else if (dhit) begin
|
else if (dhit) begin
|
m2Opcode <= `NOPI;
|
m2Opcode <= `NOPI;
|
if (pea[1])
|
if (pea[1])
|
m2Data <= {{32{cdat[31]}},cdat[31:0]};
|
m2Data <= {{32{cdat[31]}},cdat[31:0]};
|
else
|
else
|
m2Data <= {{32{cdat[63]}},cdat[63:32]};
|
m2Data <= {{32{cdat[63]}},cdat[63:32]};
|
end
|
end
|
|
|
`LHU:
|
`LHU:
|
if (!m1IsCacheElement) begin
|
if (!m1IsCacheElement) begin
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
sel_o <= pea[2] ? 8'b11110000 : 8'b00001111;
|
sel_o <= pea[2] ? 8'b11110000 : 8'b00001111;
|
adr_o <= {pea[63:2],2'b00};
|
adr_o <= {pea[63:2],2'b00};
|
m2Addr <= {pea[63:2],2'b00};
|
m2Addr <= {pea[63:2],2'b00};
|
end
|
end
|
else if (dhit) begin
|
else if (dhit) begin
|
m2Opcode <= `NOPI;
|
m2Opcode <= `NOPI;
|
if (pea[1])
|
if (pea[1])
|
m2Data <= {32'd0,cdat};
|
m2Data <= {32'd0,cdat};
|
else
|
else
|
m2Data <= {32'd0,cdat[63:32]};
|
m2Data <= {32'd0,cdat[63:32]};
|
end
|
end
|
|
|
`LC:
|
`LC:
|
if (!m1IsCacheElement) begin
|
if (!m1IsCacheElement) begin
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
case(pea[2:1])
|
case(pea[2:1])
|
2'b00: sel_o <= 8'b00000011;
|
2'b00: sel_o <= 8'b00000011;
|
2'b01: sel_o <= 8'b00001100;
|
2'b01: sel_o <= 8'b00001100;
|
2'b10: sel_o <= 8'b00110000;
|
2'b10: sel_o <= 8'b00110000;
|
2'b11: sel_o <= 8'b11000000;
|
2'b11: sel_o <= 8'b11000000;
|
endcase
|
endcase
|
adr_o <= {pea[63:1],1'b0};
|
adr_o <= {pea[63:1],1'b0};
|
m2Addr <= {pea[63:1],1'b0};
|
m2Addr <= {pea[63:1],1'b0};
|
end
|
end
|
else if (dhit) begin
|
else if (dhit) begin
|
|
$display("dhit=1, cdat=%h",cdat);
|
m2Opcode <= `NOPI;
|
m2Opcode <= `NOPI;
|
case(pea[2:1])
|
case(pea[2:1])
|
2'd0: m2Data <= {{48{cdat[15]}},cdat[15:0]};
|
2'd0: m2Data <= {{48{cdat[15]}},cdat[15:0]};
|
2'd1: m2Data <= {{48{cdat[31]}},cdat[31:16]};
|
2'd1: m2Data <= {{48{cdat[31]}},cdat[31:16]};
|
2'd2: m2Data <= {{48{cdat[47]}},cdat[47:32]};
|
2'd2: m2Data <= {{48{cdat[47]}},cdat[47:32]};
|
2'd3: m2Data <= {{48{cdat[63]}},cdat[63:48]};
|
2'd3: m2Data <= {{48{cdat[63]}},cdat[63:48]};
|
endcase
|
endcase
|
end
|
end
|
|
|
`LCU:
|
`LCU:
|
if (!m1IsCacheElement) begin
|
if (!m1IsCacheElement) begin
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
case(pea[2:1])
|
case(pea[2:1])
|
2'b00: sel_o <= 8'b00000011;
|
2'b00: sel_o <= 8'b00000011;
|
2'b01: sel_o <= 8'b00001100;
|
2'b01: sel_o <= 8'b00001100;
|
2'b10: sel_o <= 8'b00110000;
|
2'b10: sel_o <= 8'b00110000;
|
2'b11: sel_o <= 8'b11000000;
|
2'b11: sel_o <= 8'b11000000;
|
endcase
|
endcase
|
adr_o <= {pea[63:1],1'b0};
|
adr_o <= {pea[63:1],1'b0};
|
m2Addr <= {pea[63:1],1'b0};
|
m2Addr <= {pea[63:1],1'b0};
|
end
|
end
|
else if (dhit) begin
|
else if (dhit) begin
|
m2Opcode <= `NOPI;
|
m2Opcode <= `NOPI;
|
case(pea[2:1])
|
case(pea[2:1])
|
2'd0: m2Data <= {48'd0,cdat[15: 0]};
|
2'd0: m2Data <= {48'd0,cdat[15: 0]};
|
2'd1: m2Data <= {48'd0,cdat[31:16]};
|
2'd1: m2Data <= {48'd0,cdat[31:16]};
|
2'd2: m2Data <= {48'd0,cdat[47:32]};
|
2'd2: m2Data <= {48'd0,cdat[47:32]};
|
2'd3: m2Data <= {48'd0,cdat[63:48]};
|
2'd3: m2Data <= {48'd0,cdat[63:48]};
|
endcase
|
endcase
|
end
|
end
|
|
|
`LB:
|
`LB:
|
if (!m1IsCacheElement) begin
|
if (!m1IsCacheElement) begin
|
$display("Load byte:");
|
$display("Load byte:");
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
case(pea[2:0])
|
case(pea[2:0])
|
3'b000: sel_o <= 8'b00000001;
|
3'b000: sel_o <= 8'b00000001;
|
3'b001: sel_o <= 8'b00000010;
|
3'b001: sel_o <= 8'b00000010;
|
3'b010: sel_o <= 8'b00000100;
|
3'b010: sel_o <= 8'b00000100;
|
3'b011: sel_o <= 8'b00001000;
|
3'b011: sel_o <= 8'b00001000;
|
3'b100: sel_o <= 8'b00010000;
|
3'b100: sel_o <= 8'b00010000;
|
3'b101: sel_o <= 8'b00100000;
|
3'b101: sel_o <= 8'b00100000;
|
3'b110: sel_o <= 8'b01000000;
|
3'b110: sel_o <= 8'b01000000;
|
3'b111: sel_o <= 8'b10000000;
|
3'b111: sel_o <= 8'b10000000;
|
endcase
|
endcase
|
adr_o <= pea;
|
adr_o <= pea;
|
m2Addr <= pea;
|
m2Addr <= pea;
|
end
|
end
|
else if (dhit) begin
|
else if (dhit) begin
|
m2Opcode <= `NOPI;
|
m2Opcode <= `NOPI;
|
case(pea[2:0])
|
case(pea[2:0])
|
3'b000: m2Data <= {{56{cdat[ 7]}},cdat[ 7: 0]};
|
3'b000: m2Data <= {{56{cdat[ 7]}},cdat[ 7: 0]};
|
3'b001: m2Data <= {{56{cdat[15]}},cdat[15: 8]};
|
3'b001: m2Data <= {{56{cdat[15]}},cdat[15: 8]};
|
3'b010: m2Data <= {{56{cdat[23]}},cdat[23:16]};
|
3'b010: m2Data <= {{56{cdat[23]}},cdat[23:16]};
|
3'b011: m2Data <= {{56{cdat[31]}},cdat[31:24]};
|
3'b011: m2Data <= {{56{cdat[31]}},cdat[31:24]};
|
3'b100: m2Data <= {{56{cdat[39]}},cdat[39:32]};
|
3'b100: m2Data <= {{56{cdat[39]}},cdat[39:32]};
|
3'b101: m2Data <= {{56{cdat[47]}},cdat[47:40]};
|
3'b101: m2Data <= {{56{cdat[47]}},cdat[47:40]};
|
3'b110: m2Data <= {{56{cdat[55]}},cdat[55:48]};
|
3'b110: m2Data <= {{56{cdat[55]}},cdat[55:48]};
|
3'b111: m2Data <= {{56{cdat[63]}},cdat[63:56]};
|
3'b111: m2Data <= {{56{cdat[63]}},cdat[63:56]};
|
endcase
|
endcase
|
end
|
end
|
|
|
`LBU:
|
`LBU:
|
if (!m1IsCacheElement) begin
|
if (!m1IsCacheElement) begin
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
case(pea[2:0])
|
case(pea[2:0])
|
3'b000: sel_o <= 8'b00000001;
|
3'b000: sel_o <= 8'b00000001;
|
3'b001: sel_o <= 8'b00000010;
|
3'b001: sel_o <= 8'b00000010;
|
3'b010: sel_o <= 8'b00000100;
|
3'b010: sel_o <= 8'b00000100;
|
3'b011: sel_o <= 8'b00001000;
|
3'b011: sel_o <= 8'b00001000;
|
3'b100: sel_o <= 8'b00010000;
|
3'b100: sel_o <= 8'b00010000;
|
3'b101: sel_o <= 8'b00100000;
|
3'b101: sel_o <= 8'b00100000;
|
3'b110: sel_o <= 8'b01000000;
|
3'b110: sel_o <= 8'b01000000;
|
3'b111: sel_o <= 8'b10000000;
|
3'b111: sel_o <= 8'b10000000;
|
endcase
|
endcase
|
adr_o <= pea;
|
adr_o <= pea;
|
m2Addr <= pea;
|
m2Addr <= pea;
|
end
|
end
|
else if (dhit) begin
|
else if (dhit) begin
|
m2Opcode <= `NOPI;
|
m2Opcode <= `NOPI;
|
case(pea[2:0])
|
case(pea[2:0])
|
3'b000: m2Data <= {56'd0,cdat[ 7: 0]};
|
3'b000: m2Data <= {56'd0,cdat[ 7: 0]};
|
3'b001: m2Data <= {56'd0,cdat[15: 8]};
|
3'b001: m2Data <= {56'd0,cdat[15: 8]};
|
3'b010: m2Data <= {56'd0,cdat[23:16]};
|
3'b010: m2Data <= {56'd0,cdat[23:16]};
|
3'b011: m2Data <= {56'd0,cdat[31:23]};
|
3'b011: m2Data <= {56'd0,cdat[31:23]};
|
3'b100: m2Data <= {56'd0,cdat[39:32]};
|
3'b100: m2Data <= {56'd0,cdat[39:32]};
|
3'b101: m2Data <= {56'd0,cdat[47:40]};
|
3'b101: m2Data <= {56'd0,cdat[47:40]};
|
3'b110: m2Data <= {56'd0,cdat[55:48]};
|
3'b110: m2Data <= {56'd0,cdat[55:48]};
|
3'b111: m2Data <= {56'd0,cdat[63:56]};
|
3'b111: m2Data <= {56'd0,cdat[63:56]};
|
endcase
|
endcase
|
end
|
end
|
|
|
`SW:
|
`SW,`SM,`SFD:
|
begin
|
begin
|
|
$display("SW/SM");
|
m2Addr <= {pea[63:3],3'b000};
|
m2Addr <= {pea[63:3],3'b000};
|
wrhit <= dhit;
|
wrhit <= dhit;
|
`ifdef TLB
|
`ifdef TLB
|
if (!m1UnmappedDataArea & !q[3])
|
if (!m1UnmappedDataArea & !q[3])
|
ITLBD[{q[2:0],pea[15:13]}] <= 1'b1;
|
ITLBD[{q[2:0],pea[15:13]}] <= 1'b1;
|
`endif
|
`endif
|
|
`ifdef ADDRESS_RESERVATION
|
if (resv_address==pea[63:5])
|
if (resv_address==pea[63:5])
|
resv_address <= 59'd0;
|
resv_address <= 59'd0;
|
|
`endif
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
we_o <= 1'b1;
|
we_o <= 1'b1;
|
sel_o <= 8'hFF;
|
sel_o <= 8'hFF;
|
adr_o <= {pea[63:3],3'b000};
|
adr_o <= {pea[63:3],3'b000};
|
dat_o <= m1Data;
|
dat_o <= m1Data;
|
end
|
end
|
|
|
`SH:
|
`SH,`SF:
|
begin
|
begin
|
wrhit <= dhit;
|
wrhit <= dhit;
|
m2Addr <= {pea[63:2],2'b00};
|
m2Addr <= {pea[63:2],2'b00};
|
`ifdef TLB
|
`ifdef TLB
|
if (!m1UnmappedDataArea & !q[3])
|
if (!m1UnmappedDataArea & !q[3])
|
ITLBD[{q[2:0],pea[15:13]}] <= 1'b1;
|
ITLBD[{q[2:0],pea[15:13]}] <= 1'b1;
|
`endif
|
`endif
|
|
`ifdef ADDRESS_RESERVATION
|
if (resv_address==pea[63:5])
|
if (resv_address==pea[63:5])
|
resv_address <= 59'd0;
|
resv_address <= 59'd0;
|
|
`endif
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
we_o <= 1'b1;
|
we_o <= 1'b1;
|
sel_o <= pea[2] ? 8'b11110000 : 8'b00001111;
|
sel_o <= pea[2] ? 8'b11110000 : 8'b00001111;
|
adr_o <= {pea[63:2],2'b00};
|
adr_o <= {pea[63:2],2'b00};
|
dat_o <= {2{m1Data[31:0]}};
|
dat_o <= {2{m1Data[31:0]}};
|
end
|
end
|
|
|
`SC:
|
`SC:
|
begin
|
begin
|
$display("Storing char to %h, ea=%h",pea,ea);
|
$display("Storing char to %h, ea=%h",pea,ea);
|
wrhit <= dhit;
|
wrhit <= dhit;
|
m2Addr <= {pea[63:2],2'b00};
|
m2Addr <= {pea[63:2],2'b00};
|
`ifdef TLB
|
`ifdef TLB
|
if (!m1UnmappedDataArea & !q[3])
|
if (!m1UnmappedDataArea & !q[3])
|
ITLBD[{q[2:0],pea[15:13]}] <= 1'b1;
|
ITLBD[{q[2:0],pea[15:13]}] <= 1'b1;
|
`endif
|
`endif
|
|
`ifdef ADDRESS_RESERVATION
|
if (resv_address==pea[63:5])
|
if (resv_address==pea[63:5])
|
resv_address <= 59'd0;
|
resv_address <= 59'd0;
|
|
`endif
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
we_o <= 1'b1;
|
we_o <= 1'b1;
|
case(pea[2:1])
|
case(pea[2:1])
|
2'b00: sel_o <= 8'b00000011;
|
2'b00: sel_o <= 8'b00000011;
|
2'b01: sel_o <= 8'b00001100;
|
2'b01: sel_o <= 8'b00001100;
|
2'b10: sel_o <= 8'b00110000;
|
2'b10: sel_o <= 8'b00110000;
|
2'b11: sel_o <= 8'b11000000;
|
2'b11: sel_o <= 8'b11000000;
|
endcase
|
endcase
|
adr_o <= {pea[63:1],1'b0};
|
adr_o <= {pea[63:1],1'b0};
|
dat_o <= {4{m1Data[15:0]}};
|
dat_o <= {4{m1Data[15:0]}};
|
end
|
end
|
|
|
`SB:
|
`SB:
|
begin
|
begin
|
wrhit <= dhit;
|
wrhit <= dhit;
|
m2Addr <= {pea[63:2],2'b00};
|
m2Addr <= {pea[63:2],2'b00};
|
|
`ifdef ADDRESS_RESERVATION
|
if (resv_address==pea[63:5])
|
if (resv_address==pea[63:5])
|
resv_address <= 59'd0;
|
resv_address <= 59'd0;
|
|
`endif
|
`ifdef TLB
|
`ifdef TLB
|
if (!m1UnmappedDataArea & !q[3])
|
if (!m1UnmappedDataArea & !q[3])
|
ITLBD[{q[2:0],pea[15:13]}] <= 1'b1;
|
ITLBD[{q[2:0],pea[15:13]}] <= 1'b1;
|
`endif
|
`endif
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
we_o <= 1'b1;
|
we_o <= 1'b1;
|
case(pea[2:0])
|
case(pea[2:0])
|
3'b000: sel_o <= 8'b00000001;
|
3'b000: sel_o <= 8'b00000001;
|
3'b001: sel_o <= 8'b00000010;
|
3'b001: sel_o <= 8'b00000010;
|
3'b010: sel_o <= 8'b00000100;
|
3'b010: sel_o <= 8'b00000100;
|
3'b011: sel_o <= 8'b00001000;
|
3'b011: sel_o <= 8'b00001000;
|
3'b100: sel_o <= 8'b00010000;
|
3'b100: sel_o <= 8'b00010000;
|
3'b101: sel_o <= 8'b00100000;
|
3'b101: sel_o <= 8'b00100000;
|
3'b110: sel_o <= 8'b01000000;
|
3'b110: sel_o <= 8'b01000000;
|
3'b111: sel_o <= 8'b10000000;
|
3'b111: sel_o <= 8'b10000000;
|
endcase
|
endcase
|
adr_o <= {pea[63:2],2'b00};
|
adr_o <= {pea[63:2],2'b00};
|
dat_o <= {8{m1Data[7:0]}};
|
dat_o <= {8{m1Data[7:0]}};
|
end
|
end
|
|
|
|
`ifdef ADDRESS_RESERVATION
|
`SWC:
|
`SWC:
|
begin
|
begin
|
rsf <= 1'b0;
|
rsf <= 1'b0;
|
if (resv_address==pea[63:5]) begin
|
if (resv_address==pea[63:5]) begin
|
`ifdef TLB
|
`ifdef TLB
|
if (!m1UnmappedDataArea & !q[3])
|
if (!m1UnmappedDataArea & !q[3])
|
ITLBD[{q[2:0],pea[15:13]}] <= 1'b1;
|
ITLBD[{q[2:0],pea[15:13]}] <= 1'b1;
|
`endif
|
`endif
|
wrhit <= dhit;
|
wrhit <= dhit;
|
m2Addr <= {pea[63:3],3'b00};
|
m2Addr <= {pea[63:3],3'b00};
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
we_o <= 1'b1;
|
we_o <= 1'b1;
|
sel_o <= 8'hFF;
|
sel_o <= 8'hFF;
|
adr_o <= {pea[63:3],3'b000};
|
adr_o <= {pea[63:3],3'b000};
|
dat_o <= m1Data;
|
dat_o <= m1Data;
|
resv_address <= 59'd0;
|
resv_address <= 59'd0;
|
rsf <= 1'b1;
|
rsf <= 1'b1;
|
end
|
end
|
else
|
else
|
m2Opcode <= `NOPI;
|
m2Opcode <= `NOPI;
|
end
|
end
|
|
`endif
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
// EXECUTE:
|
// EXECUTE:
|
// - perform datapath operation
|
// - perform datapath operation
|
// - perform virtual to physical address translation.
|
// - perform virtual to physical address translation.
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
if (advanceX) begin
|
if (advanceX) begin
|
m1hwxtype <= xhwxtype;
|
m1hwxtype <= xhwxtype;
|
m1Fip <= xFip;
|
m1Fip <= xFip;
|
m1extype <= xextype;
|
m1extype <= xextype;
|
m1Opcode <= xOpcode;
|
m1Opcode <= xOpcode;
|
m1Func <= xFunc;
|
m1Func <= xFunc;
|
m1Rt <= xRt;
|
m1Rt <= xRt;
|
m1Data <= xData;
|
m1Data <= xData;
|
m1IsCacheElement <= xisCacheElement;
|
m1IsCacheElement <= xisCacheElement;
|
if (xOpcode==`MOVZ && !aeqz) begin
|
if (xOpcode==`MOVZ && !aeqz) begin
|
m1Rt <= 9'd0;
|
m1Rt <= 9'd0;
|
m1Data <= 64'd0;
|
m1Data <= 64'd0;
|
end
|
end
|
if (xOpcode==`MOVNZ && aeqz) begin
|
if (xOpcode==`MOVNZ && aeqz) begin
|
m1Rt <= 9'd0;
|
m1Rt <= 9'd0;
|
m1Data <= 64'd0;
|
m1Data <= 64'd0;
|
end
|
end
|
m1pc <= xpc;
|
m1pc <= xpc;
|
m1pcv <= xpcv;
|
m1pcv <= xpcv;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
a <= 64'd0;
|
a <= 64'd0;
|
b <= 64'd0;
|
b <= 64'd0;
|
imm <= 64'd0;
|
imm <= 64'd0;
|
xextype <= `EX_NON;
|
xextype <= `EX_NON;
|
if (xOpcode[6:4]!=`IMM) begin
|
if (xOpcode[6:4]!=`IMM) begin
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
end
|
end
|
// xpc <= 64'd0;
|
// xpc <= 64'd0;
|
case(xOpcode)
|
case(xOpcode)
|
`MISC:
|
`MISC:
|
case(xFunc)
|
case(xFunc)
|
`WAIT: m1clkoff <= 1'b1;
|
`WAIT: m1clkoff <= 1'b1;
|
`ICACHE_ON: ICacheOn <= 1'b1;
|
`ICACHE_ON: ICacheOn <= 1'b1;
|
`ICACHE_OFF: ICacheOn <= 1'b0;
|
`ICACHE_OFF: ICacheOn <= 1'b0;
|
|
`DCACHE_ON: dcache_on <= 1'b1;
|
|
`DCACHE_OFF: dcache_on <= 1'b0;
|
`ifdef TLB
|
`ifdef TLB
|
`TLBP: ea <= TLBVirtPage;
|
`TLBP: ea <= TLBVirtPage;
|
`TLBR,`TLBWI:
|
`TLBR,`TLBWI:
|
begin
|
begin
|
i <= {Index[2:0],TLBVirtPage[15:13]};
|
i <= {Index[2:0],TLBVirtPage[15:13]};
|
end
|
end
|
`TLBWR:
|
`TLBWR:
|
begin
|
begin
|
i <= {Random,TLBVirtPage[15:13]};
|
i <= {Random,TLBVirtPage[15:13]};
|
end
|
end
|
`endif
|
`endif
|
default: ;
|
default: ;
|
endcase
|
endcase
|
`R:
|
`R:
|
case(xFunc)
|
case(xFunc)
|
`MTSPR:
|
`MTSPR:
|
case(xIR[12:7])
|
case(xIR[12:7])
|
`ifdef TLB
|
`ifdef TLB
|
`Wired: Wired <= a[2:0];
|
`Wired: Wired <= a[2:0];
|
`TLBIndex: Index <= a[2:0];
|
`TLBIndex: Index <= a[2:0];
|
`TLBVirtPage: TLBVirtPage <= a[63:13];
|
`TLBVirtPage: TLBVirtPage <= a[63:13];
|
`TLBPhysPage0: TLBPhysPage0 <= a[63:13];
|
`TLBPhysPage0: TLBPhysPage0 <= a[63:13];
|
`TLBPhysPage1: TLBPhysPage1 <= a[63:13];
|
`TLBPhysPage1: TLBPhysPage1 <= a[63:13];
|
`TLBPageMask: TLBPageMask <= a[24:13];
|
`TLBPageMask: TLBPageMask <= a[24:13];
|
`TLBASID: begin
|
`TLBASID: begin
|
TLBValid <= a[0];
|
TLBValid <= a[0];
|
TLBD <= a[1];
|
TLBD <= a[1];
|
TLBG <= a[2];
|
TLBG <= a[2];
|
TLBASID <= a[15:8];
|
TLBASID <= a[15:8];
|
end
|
end
|
`PageTableAddr: PageTableAddr <= a[63:13];
|
`PageTableAddr: PageTableAddr <= a[63:13];
|
`BadVAddr: BadVAddr <= a[63:13];
|
`BadVAddr: BadVAddr <= a[63:13];
|
`endif
|
`endif
|
`ASID: ASID <= a[7:0];
|
`ASID: ASID <= a[7:0];
|
`EPC: EPC <= a;
|
`EPC: EPC <= a;
|
`TBA: TBA <= {a[63:12],12'h000};
|
`TBA: TBA <= {a[63:12],12'h000};
|
`AXC: AXC <= a[3:0];
|
`AXC: AXC <= a[3:0];
|
`NON_ICACHE_SEG: nonICacheSeg <= a[63:32];
|
`NON_ICACHE_SEG: nonICacheSeg <= a[63:32];
|
|
`FPCR: rm <= a[31:30];
|
|
`IPC: IPC <= a;
|
default: ;
|
default: ;
|
endcase
|
endcase
|
`OMG: mutex_gate[a[5:0]] <= 1'b1;
|
`OMG: mutex_gate[a[5:0]] <= 1'b1;
|
`CMG: mutex_gate[a[5:0]] <= 1'b0;
|
`CMG: mutex_gate[a[5:0]] <= 1'b0;
|
`OMGI: mutex_gate[xIR[12:7]] <= 1'b1;
|
`OMGI: mutex_gate[xIR[12:7]] <= 1'b1;
|
`CMGI: mutex_gate[xIR[12:7]] <= 1'b0;
|
`CMGI: mutex_gate[xIR[12:7]] <= 1'b0;
|
default: ;
|
default: ;
|
endcase
|
endcase
|
`CALL: m1Data <= fnIncPC(xpc);
|
`CALL: m1Data <= fnIncPC(xpc);
|
`INW:
|
`INW:
|
begin
|
begin
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
sel_o <= 8'hFF;
|
sel_o <= 8'hFF;
|
adr_o <= {xData[63:3],3'b000};
|
adr_o <= {xData[63:3],3'b000};
|
end
|
end
|
`INH,`INHU:
|
`INH,`INHU:
|
begin
|
begin
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
sel_o <= xData[2] ? 8'b11110000 : 8'b00001111;
|
sel_o <= xData[2] ? 8'b11110000 : 8'b00001111;
|
adr_o <= {xData[63:2],2'b00};
|
adr_o <= {xData[63:2],2'b00};
|
end
|
end
|
`INCH,`INCU:
|
`INCH,`INCU:
|
begin
|
begin
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
case(xData[2:1])
|
case(xData[2:1])
|
2'b00: sel_o <= 8'b00000011;
|
2'b00: sel_o <= 8'b00000011;
|
2'b01: sel_o <= 8'b00001100;
|
2'b01: sel_o <= 8'b00001100;
|
2'b10: sel_o <= 8'b00110000;
|
2'b10: sel_o <= 8'b00110000;
|
2'b11: sel_o <= 8'b11000000;
|
2'b11: sel_o <= 8'b11000000;
|
endcase
|
endcase
|
adr_o <= {xData[63:1],1'b0};
|
adr_o <= {xData[63:1],1'b0};
|
end
|
end
|
`INB,`INBU:
|
`INB,`INBU:
|
begin
|
begin
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
case(xData[2:0])
|
case(xData[2:0])
|
3'b000: sel_o <= 8'b00000001;
|
3'b000: sel_o <= 8'b00000001;
|
3'b001: sel_o <= 8'b00000010;
|
3'b001: sel_o <= 8'b00000010;
|
3'b010: sel_o <= 8'b00000100;
|
3'b010: sel_o <= 8'b00000100;
|
3'b011: sel_o <= 8'b00001000;
|
3'b011: sel_o <= 8'b00001000;
|
3'b100: sel_o <= 8'b00010000;
|
3'b100: sel_o <= 8'b00010000;
|
3'b101: sel_o <= 8'b00100000;
|
3'b101: sel_o <= 8'b00100000;
|
3'b110: sel_o <= 8'b01000000;
|
3'b110: sel_o <= 8'b01000000;
|
3'b111: sel_o <= 8'b10000000;
|
3'b111: sel_o <= 8'b10000000;
|
endcase
|
endcase
|
adr_o <= xData;
|
adr_o <= xData;
|
end
|
end
|
`OUTW:
|
`OUTW:
|
begin
|
begin
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
we_o <= 1'b1;
|
we_o <= 1'b1;
|
sel_o <= 8'hFF;
|
sel_o <= 8'hFF;
|
adr_o <= {xData[63:3],3'b000};
|
adr_o <= {xData[63:3],3'b000};
|
dat_o <= b;
|
dat_o <= b;
|
end
|
end
|
`OUTH:
|
`OUTH:
|
begin
|
begin
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
we_o <= 1'b1;
|
we_o <= 1'b1;
|
sel_o <= xData[2] ? 8'b11110000 : 8'b00001111;
|
sel_o <= xData[2] ? 8'b11110000 : 8'b00001111;
|
adr_o <= {xData[63:2],2'b00};
|
adr_o <= {xData[63:2],2'b00};
|
dat_o <= {2{b[31:0]}};
|
dat_o <= {2{b[31:0]}};
|
end
|
end
|
`OUTC:
|
`OUTC:
|
begin
|
begin
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
we_o <= 1'b1;
|
we_o <= 1'b1;
|
case(xData[2:1])
|
case(xData[2:1])
|
2'b00: sel_o <= 8'b00000011;
|
2'b00: sel_o <= 8'b00000011;
|
2'b01: sel_o <= 8'b00001100;
|
2'b01: sel_o <= 8'b00001100;
|
2'b10: sel_o <= 8'b00110000;
|
2'b10: sel_o <= 8'b00110000;
|
2'b11: sel_o <= 8'b11000000;
|
2'b11: sel_o <= 8'b11000000;
|
endcase
|
endcase
|
adr_o <= {xData[63:1],1'b0};
|
adr_o <= {xData[63:1],1'b0};
|
dat_o <= {4{b[15:0]}};
|
dat_o <= {4{b[15:0]}};
|
end
|
end
|
`OUTB:
|
`OUTB:
|
begin
|
begin
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
we_o <= 1'b1;
|
we_o <= 1'b1;
|
case(xData[2:0])
|
case(xData[2:0])
|
3'b000: sel_o <= 8'b00000001;
|
3'b000: sel_o <= 8'b00000001;
|
3'b001: sel_o <= 8'b00000010;
|
3'b001: sel_o <= 8'b00000010;
|
3'b010: sel_o <= 8'b00000100;
|
3'b010: sel_o <= 8'b00000100;
|
3'b011: sel_o <= 8'b00001000;
|
3'b011: sel_o <= 8'b00001000;
|
3'b100: sel_o <= 8'b00010000;
|
3'b100: sel_o <= 8'b00010000;
|
3'b101: sel_o <= 8'b00100000;
|
3'b101: sel_o <= 8'b00100000;
|
3'b110: sel_o <= 8'b01000000;
|
3'b110: sel_o <= 8'b01000000;
|
3'b111: sel_o <= 8'b10000000;
|
3'b111: sel_o <= 8'b10000000;
|
endcase
|
endcase
|
adr_o <= xData;
|
adr_o <= xData;
|
dat_o <= {8{b[7:0]}};
|
dat_o <= {8{b[7:0]}};
|
end
|
end
|
`LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`LWR,`SW,`SH,`SC,`SB,`SWC:
|
`LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`LWR,`LF,`LFD,`LM,
|
|
`SW,`SH,`SC,`SB,`SWC,`SF,`SFD,`SM:
|
begin
|
begin
|
m1Data <= b;
|
m1Data <= b;
|
ea <= xData;
|
ea <= xData;
|
end
|
end
|
`MEMNDX:
|
`MEMNDX:
|
begin
|
begin
|
m1Opcode <= xFunc;
|
m1Opcode <= xFunc;
|
m1Data <= c;
|
m1Data <= c;
|
ea <= xData;
|
ea <= xData;
|
end
|
end
|
`DIVSI,`DIVUI:
|
`DIVSI,`DIVUI:
|
if (b==64'd0) begin
|
if (b==64'd0) begin
|
xextype <= `EX_DBZ;
|
xextype <= `EX_DBZ;
|
end
|
end
|
default: ;
|
default: ;
|
endcase
|
endcase
|
`ifndef BRANCH_PREDICTION_SIMPLE
|
`ifndef BRANCH_PREDICTION_SIMPLE
|
// Update the branch history
|
// Update the branch history
|
if (isxBranch) begin
|
if (isxBranch) begin
|
gbl_branch_hist <= {gbl_branch_hist,takb};
|
gbl_branch_hist <= {gbl_branch_hist,takb};
|
branch_history_table[bht_wa] <= xbits_new;
|
branch_history_table[bht_wa] <= xbits_new;
|
end
|
end
|
`endif
|
`endif
|
end
|
end
|
|
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
// RFETCH:
|
// RFETCH:
|
// Register fetch stage
|
// Register fetch stage
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
if (advanceR) begin
|
if (advanceR) begin
|
xAXC <= dAXC;
|
xAXC <= dAXC;
|
xhwxtype <= dhwxtype;
|
xhwxtype <= dhwxtype;
|
xFip <= dFip;
|
xFip <= dFip;
|
xextype <= dextype;
|
xextype <= dextype;
|
|
if (dOpcode==`R && dFunc==`MYST)
|
|
xIR <= nxt_c;
|
|
else
|
xIR <= dIR;
|
xIR <= dIR;
|
xpc <= dpc;
|
xpc <= dpc;
|
xpcv <= dpcv;
|
xpcv <= dpcv;
|
xbranch_taken <= dbranch_taken;
|
xbranch_taken <= dbranch_taken;
|
dbranch_taken <= 1'b0;
|
dbranch_taken <= 1'b0;
|
dextype <= `EX_NON;
|
dextype <= `EX_NON;
|
if (dOpcode[6:4]!=`IMM) // IMM is "sticky"
|
if (dOpcode[6:4]!=`IMM && dOpcode!=`LM && dOpcode!=`SM) // IMM is "sticky"
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
dRa <= 9'd0;
|
dRa <= 9'd0;
|
dRb <= 9'd0;
|
dRb <= 9'd0;
|
|
|
// Result forward muxes
|
// Result forward muxes
|
casex(dRa)
|
casex(dRa)
|
9'bxxxx00000: a <= 64'd0;
|
9'bxxxx00000: a <= 64'd0;
|
xRt: a <= xData;
|
xRt: a <= xData;
|
m1Rt: a <= m1Data;
|
m1Rt: a <= m1Data;
|
m2Rt: a <= m2Data;
|
m2Rt: a <= m2Data;
|
wRt: a <= wData;
|
wRt: a <= wData;
|
tRt: a <= tData;
|
tRt: a <= tData;
|
default: a <= rfoa;
|
default: a <= rfoa;
|
endcase
|
endcase
|
casex(dRb)
|
casex(dRb)
|
9'bxxxx00000: b <= 64'd0;
|
9'bxxxx00000: b <= 64'd0;
|
xRt: b <= disRightShift ? -xData[5:0] : xData;
|
xRt: b <= disRightShift ? -xData[5:0] : xData;
|
m1Rt: b <= disRightShift ? -m1Data[5:0] : m1Data;
|
m1Rt: b <= disRightShift ? -m1Data[5:0] : m1Data;
|
m2Rt: b <= disRightShift ? -m2Data[5:0] : m2Data;
|
m2Rt: b <= disRightShift ? -m2Data[5:0] : m2Data;
|
wRt: b <= disRightShift ? -wData[5:0] : wData;
|
wRt: b <= disRightShift ? -wData[5:0] : wData;
|
tRt: b <= disRightShift ? -tData[5:0] : tData;
|
tRt: b <= disRightShift ? -tData[5:0] : tData;
|
default: b <= disRightShift ? -rfob[5:0] : rfob;
|
default: b <= disRightShift ? -rfob[5:0] : rfob;
|
endcase
|
endcase
|
if (dOpcode==`SHFTI)
|
if (dOpcode==`SHFTI)
|
case(dFunc)
|
case(dFunc)
|
`RORI: b <= {58'd0,~dIR[24:19]+6'd1};
|
`RORI: b <= {58'd0,~dIR[24:19]+6'd1};
|
default: b <= {58'd0,dIR[24:19]};
|
default: b <= {58'd0,dIR[24:19]};
|
endcase
|
endcase
|
casex(dRc)
|
c <= nxt_c;
|
9'bxxxx00000: c <= 64'd0;
|
|
xRt: c <= xData;
|
|
m1Rt: c <= m1Data;
|
|
m2Rt: c <= m2Data;
|
|
wRt: c <= wData;
|
|
tRt: c <= tData;
|
|
default: c <= rfoc;
|
|
endcase
|
|
|
|
// Set the target register
|
// Set the target register
|
casex(dOpcode)
|
casex(dOpcode)
|
|
`R:
|
|
case(dFunc)
|
|
`MYST: xRt <= {dAXC,dIR[19:15]};
|
|
default: xRt <= {dAXC,dIR[29:25]};
|
|
endcase
|
`SETLO: xRt <= {dAXC,dIR[36:32]};
|
`SETLO: xRt <= {dAXC,dIR[36:32]};
|
`SETHI: xRt <= {dAXC,dIR[36:32]};
|
`SETHI: xRt <= {dAXC,dIR[36:32]};
|
`RR: xRt <= {dAXC,dIR[24:20]};
|
`RR: xRt <= {dAXC,dIR[24:20]};
|
`BTRI: xRt <= 9'd0;
|
`BTRI: xRt <= 9'd0;
|
`BTRR: xRt <= 9'd0;
|
`BTRR:
|
|
case(dIR[4:0])
|
|
`LOOP: xRt <= {AXC,dIR[29:25]};
|
|
default: xRt <= 9'd0;
|
|
endcase
|
`TRAPcc: xRt <= 9'd0;
|
`TRAPcc: xRt <= 9'd0;
|
`TRAPcci: xRt <= 9'd0;
|
`TRAPcci: xRt <= 9'd0;
|
`JMP: xRt <= 9'd00;
|
`JMP: xRt <= 9'd00;
|
`CALL: xRt <= {dAXC,5'd31};
|
`CALL: xRt <= {dAXC,5'd31};
|
`RET: xRt <= {dAXC,dIR[24:20]};
|
`RET: xRt <= {dAXC,dIR[24:20]};
|
`MEMNDX:
|
`MEMNDX:
|
case(dFunc)
|
case(dFunc)
|
`SW,`SH,`SC,`SB,`OUTW,`OUTH,`OUTC,`OUTB:
|
`SW,`SH,`SC,`SB,`SF,`SFD,
|
|
`OUTW,`OUTH,`OUTC,`OUTB:
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
default: xRt <= {dAXC,dIR[24:20]};
|
default: xRt <= {dAXC,dIR[24:20]};
|
endcase
|
endcase
|
`SW,`SH,`SC,`SB,`OUTW,`OUTH,`OUTC,`OUTB:
|
`SW,`SH,`SC,`SB,`SF,`SFD, // but not SWC!
|
|
`OUTW,`OUTH,`OUTC,`OUTB:
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
`NOPI: xRt <= 9'd0;
|
`NOPI: xRt <= 9'd0;
|
`BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
|
`BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
|
`SM: xRt <= 9'd0;
|
|
`LM:
|
|
casex(dIR[30:0])
|
|
31'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1: xRt <= {AXC,5'd1};
|
|
31'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxx10: xRt <= {AXC,5'd2};
|
|
31'bxxxxxxxxxxxxxxxxxxxxxxxxxxxx100: xRt <= {AXC,5'd3};
|
|
31'bxxxxxxxxxxxxxxxxxxxxxxxxxxx1000: xRt <= {AXC,5'd4};
|
|
31'bxxxxxxxxxxxxxxxxxxxxxxxxxx10000: xRt <= {AXC,5'd5};
|
|
31'bxxxxxxxxxxxxxxxxxxxxxxxxx100000: xRt <= {AXC,5'd6};
|
|
31'bxxxxxxxxxxxxxxxxxxxxxxxx1000000: xRt <= {AXC,5'd7};
|
|
31'bxxxxxxxxxxxxxxxxxxxxxxx10000000: xRt <= {AXC,5'd8};
|
|
31'bxxxxxxxxxxxxxxxxxxxxxx100000000: xRt <= {AXC,5'd9};
|
|
31'bxxxxxxxxxxxxxxxxxxxxx1000000000: xRt <= {AXC,5'd10};
|
|
31'bxxxxxxxxxxxxxxxxxxxx10000000000: xRt <= {AXC,5'd11};
|
|
31'bxxxxxxxxxxxxxxxxxxx100000000000: xRt <= {AXC,5'd12};
|
|
31'bxxxxxxxxxxxxxxxxxx1000000000000: xRt <= {AXC,5'd13};
|
|
31'bxxxxxxxxxxxxxxxxx10000000000000: xRt <= {AXC,5'd14};
|
|
31'bxxxxxxxxxxxxxxxx100000000000000: xRt <= {AXC,5'd15};
|
|
31'bxxxxxxxxxxxxxxx1000000000000000: xRt <= {AXC,5'd16};
|
|
31'bxxxxxxxxxxxxxx10000000000000000: xRt <= {AXC,5'd17};
|
|
31'bxxxxxxxxxxxxx100000000000000000: xRt <= {AXC,5'd18};
|
|
31'bxxxxxxxxxxxx1000000000000000000: xRt <= {AXC,5'd19};
|
|
31'bxxxxxxxxxxx10000000000000000000: xRt <= {AXC,5'd20};
|
|
31'bxxxxxxxxxx100000000000000000000: xRt <= {AXC,5'd21};
|
|
31'bxxxxxxxxx1000000000000000000000: xRt <= {AXC,5'd22};
|
|
31'bxxxxxxxx10000000000000000000000: xRt <= {AXC,5'd23};
|
|
31'bxxxxxxx100000000000000000000000: xRt <= {AXC,5'd24};
|
|
31'bxxxxxx1000000000000000000000000: xRt <= {AXC,5'd25};
|
|
31'bxxxxx10000000000000000000000000: xRt <= {AXC,5'd26};
|
|
31'bxxxx100000000000000000000000000: xRt <= {AXC,5'd27};
|
|
31'bxxx1000000000000000000000000000: xRt <= {AXC,5'd28};
|
|
31'bxx10000000000000000000000000000: xRt <= {AXC,5'd29};
|
|
31'bx100000000000000000000000000000: xRt <= {AXC,5'd30};
|
|
31'b1000000000000000000000000000000: xRt <= {AXC,5'd31};
|
|
default: xRt <= 9'h000;
|
|
endcase
|
|
|
default: xRt <= {dAXC,dIR[29:25]};
|
default: xRt <= {dAXC,dIR[29:25]};
|
endcase
|
endcase
|
if (dOpcode[6:4]==`IMM)
|
if (dOpcode[6:4]==`IMM)
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
|
|
// Set immediate value
|
// Set immediate value
|
if (xOpcode[6:4]==`IMM) begin
|
if (xOpcode[6:4]==`IMM) begin
|
imm <= {xIR[38:0],dIR[24:0]};
|
imm <= {xIR[38:0],dIR[24:0]};
|
end
|
end
|
else
|
else
|
case(dOpcode)
|
case(dOpcode)
|
`BTRI: imm <= {{44{dIR[19]}},dIR[19:0]};
|
`BTRI: imm <= {{44{dIR[19]}},dIR[19:0]};
|
`BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
|
`BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
|
imm <= {{46{dIR[17]}},dIR[17:0]};
|
imm <= {{46{dIR[17]}},dIR[17:0]};
|
`ANDI: imm <= {39'h7FFFFFFFFF,dIR[24:0]};
|
`ANDI: imm <= {39'h7FFFFFFFFF,dIR[24:0]};
|
`ORI: imm <= {39'h0000000000,dIR[24:0]};
|
`ORI: imm <= {39'h0000000000,dIR[24:0]};
|
`XORI: imm <= {39'h0000000000,dIR[24:0]};
|
`XORI: imm <= {39'h0000000000,dIR[24:0]};
|
`RET: imm <= {44'h00000000000,dIR[19:0]};
|
`RET: imm <= {41'h00000000,dIR[19:0],3'b000};
|
`MEMNDX: imm <= {{51{dIR[19]}},dIR[19:7]};
|
`MEMNDX: imm <= {{51{dIR[19]}},dIR[19:7]};
|
default: imm <= {{39{dIR[24]}},dIR[24:0]};
|
default: imm <= {{39{dIR[24]}},dIR[24:0]};
|
endcase
|
endcase
|
case(dOpcode)
|
case(dOpcode)
|
|
|
`MISC:
|
`MISC:
|
case(dFunc)
|
case(dFunc)
|
`SEI: im <= 1'b1;
|
`SEI: im <= 1'b1;
|
`CLI: im <= 1'b0;
|
`CLI: im <= 1'b0;
|
endcase
|
endcase
|
endcase
|
endcase
|
|
|
|
if ((dOpcode==`SM || dOpcode==`LM) && dIR[31:0]!=32'd0)
|
|
dIR <= ndIR;
|
end
|
end
|
|
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
// IFETCH:
|
// IFETCH:
|
// - check for external hardware interrupt
|
// - check for external hardware interrupt
|
// - fetch instruction
|
// - fetch instruction
|
// - increment PC
|
// - increment PC
|
// - set special register defaults for some instructions
|
// - set special register defaults for some instructions
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
if (advanceI) begin
|
if (advanceI) begin
|
dAXC <= AXC;
|
dAXC <= AXC;
|
dextype <= `EX_NON;
|
dextype <= `EX_NON;
|
if (nmi_edge & !StatusHWI) begin
|
if (nmi_edge & !StatusHWI & !im1) begin
|
$display("*****************");
|
$display("*****************");
|
$display("NMI edge detected");
|
$display("NMI edge detected");
|
$display("*****************");
|
$display("*****************");
|
StatusHWI <= 1'b1;
|
StatusHWI <= 1'b1;
|
nmi_edge <= 1'b0;
|
nmi_edge <= 1'b0;
|
dhwxtype <= 2'b01;
|
dhwxtype <= 2'b01;
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
dextype <= `EX_NMI;
|
dextype <= `EX_NMI;
|
end
|
end
|
else if (irq_i & !im & !StatusHWI) begin
|
else if (irq_i & !im & !StatusHWI & !im1) begin
|
im <= 1'b1;
|
im <= 1'b1;
|
StatusHWI <= 1'b1;
|
StatusHWI <= 1'b1;
|
dhwxtype <= 2'b10;
|
dhwxtype <= 2'b10;
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
dextype <= `EX_IRQ;
|
dextype <= `EX_IRQ;
|
end
|
end
|
// Are we filling the pipeline with NOP's as a result of a previous
|
// Are we filling the pipeline with NOP's as a result of a previous
|
// hardware interrupt ?
|
// hardware interrupt ?
|
else if (|dhwxtype|dFip) begin
|
else if (|dhwxtype|dFip) begin
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
end
|
end
|
`ifdef TLB
|
`ifdef TLB
|
else if (ITLBMiss)
|
else if (ITLBMiss)
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
`endif
|
`endif
|
else begin
|
else begin
|
|
if ((iOpcode==`SM || iOpcode==`LM) && insn[31:0]!=32'd0)
|
|
im1 <= 1'b1;
|
|
else
|
|
im1 <= 1'b0;
|
|
if ((iOpcode==`SM || iOpcode==`LM) && insn[31:0]==32'd0) begin
|
|
dIR <= `NOP_INSN;
|
|
pc <= fnIncPC(pc);
|
|
end
|
|
else
|
dIR <= insn;
|
dIR <= insn;
|
`include "insn_dumpsc.v"
|
`include "insn_dumpsc.v"
|
end
|
end
|
nopI <= 1'b0;
|
nopI <= 1'b0;
|
if (dOpcode[6:4]!=`IMM) begin
|
if (dOpcode[6:4]!=`IMM) begin
|
dpc <= pc;
|
dpc <= pc;
|
dpcv <= 1'b1;
|
dpcv <= 1'b1;
|
end
|
end
|
|
dRb <= {AXC,insn[29:25]};
|
|
dRc <= {AXC,insn[24:20]};
|
casex(iOpcode)
|
casex(iOpcode)
|
`SETLO: dRa <= {AXC,insn[36:32]};
|
`SETLO: dRa <= {AXC,insn[36:32]};
|
`SETHI: dRa <= {AXC,insn[36:32]};
|
`SETHI: dRa <= {AXC,insn[36:32]};
|
|
`SM,`LM:
|
|
begin
|
|
dRa <= {AXC,1'b1,insn[34:31]};
|
|
casex(insn[30:0])
|
|
31'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1: dRb <= {AXC,5'd1};
|
|
31'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxx10: dRb <= {AXC,5'd2};
|
|
31'bxxxxxxxxxxxxxxxxxxxxxxxxxxxx100: dRb <= {AXC,5'd3};
|
|
31'bxxxxxxxxxxxxxxxxxxxxxxxxxxx1000: dRb <= {AXC,5'd4};
|
|
31'bxxxxxxxxxxxxxxxxxxxxxxxxxx10000: dRb <= {AXC,5'd5};
|
|
31'bxxxxxxxxxxxxxxxxxxxxxxxxx100000: dRb <= {AXC,5'd6};
|
|
31'bxxxxxxxxxxxxxxxxxxxxxxxx1000000: dRb <= {AXC,5'd7};
|
|
31'bxxxxxxxxxxxxxxxxxxxxxxx10000000: dRb <= {AXC,5'd8};
|
|
31'bxxxxxxxxxxxxxxxxxxxxxx100000000: dRb <= {AXC,5'd9};
|
|
31'bxxxxxxxxxxxxxxxxxxxxx1000000000: dRb <= {AXC,5'd10};
|
|
31'bxxxxxxxxxxxxxxxxxxxx10000000000: dRb <= {AXC,5'd11};
|
|
31'bxxxxxxxxxxxxxxxxxxx100000000000: dRb <= {AXC,5'd12};
|
|
31'bxxxxxxxxxxxxxxxxxx1000000000000: dRb <= {AXC,5'd13};
|
|
31'bxxxxxxxxxxxxxxxxx10000000000000: dRb <= {AXC,5'd14};
|
|
31'bxxxxxxxxxxxxxxxx100000000000000: dRb <= {AXC,5'd15};
|
|
31'bxxxxxxxxxxxxxxx1000000000000000: dRb <= {AXC,5'd16};
|
|
31'bxxxxxxxxxxxxxx10000000000000000: dRb <= {AXC,5'd17};
|
|
31'bxxxxxxxxxxxxx100000000000000000: dRb <= {AXC,5'd18};
|
|
31'bxxxxxxxxxxxx1000000000000000000: dRb <= {AXC,5'd19};
|
|
31'bxxxxxxxxxxx10000000000000000000: dRb <= {AXC,5'd20};
|
|
31'bxxxxxxxxxx100000000000000000000: dRb <= {AXC,5'd21};
|
|
31'bxxxxxxxxx1000000000000000000000: dRb <= {AXC,5'd22};
|
|
31'bxxxxxxxx10000000000000000000000: dRb <= {AXC,5'd23};
|
|
31'bxxxxxxx100000000000000000000000: dRb <= {AXC,5'd24};
|
|
31'bxxxxxx1000000000000000000000000: dRb <= {AXC,5'd25};
|
|
31'bxxxxx10000000000000000000000000: dRb <= {AXC,5'd26};
|
|
31'bxxxx100000000000000000000000000: dRb <= {AXC,5'd27};
|
|
31'bxxx1000000000000000000000000000: dRb <= {AXC,5'd28};
|
|
31'bxx10000000000000000000000000000: dRb <= {AXC,5'd29};
|
|
31'bx100000000000000000000000000000: dRb <= {AXC,5'd30};
|
|
31'b1000000000000000000000000000000: dRb <= {AXC,5'd31};
|
|
default: dRb <= {AXC,5'd0};
|
|
endcase
|
|
end
|
default: dRa <= {AXC,insn[34:30]};
|
default: dRa <= {AXC,insn[34:30]};
|
endcase
|
endcase
|
dRb <= {AXC,insn[29:25]};
|
|
dRc <= {AXC,insn[24:20]};
|
|
`ifdef TLB
|
`ifdef TLB
|
if (ITLBMiss) begin
|
if (ITLBMiss) begin
|
$display("TLB miss on instruction fetch.");
|
$display("TLB miss on instruction fetch.");
|
CauseCode <= `EX_TLBI;
|
CauseCode <= `EX_TLBI;
|
StatusEXL <= 1'b1;
|
StatusEXL <= 1'b1;
|
BadVAddr <= pc[63:13];
|
BadVAddr <= pc[63:13];
|
pc <= `ITLB_MissHandler;
|
pc <= `ITLB_MissHandler;
|
EPC <= pc;
|
EPC <= pc;
|
end
|
end
|
else
|
else
|
`endif
|
`endif
|
begin
|
begin
|
dbranch_taken <= 1'b0;
|
dbranch_taken <= 1'b0;
|
|
if ((iOpcode==`LM || iOpcode==`SM) && insn[31:0]!=32'd0)
|
|
;
|
|
else begin
|
pc <= fnIncPC(pc);
|
pc <= fnIncPC(pc);
|
|
end
|
case(iOpcode)
|
case(iOpcode)
|
`MISC:
|
`MISC:
|
case(iFunc)
|
case(iFunc)
|
`FIP: dFip <= 1'b1;
|
`FIP: dFip <= 1'b1;
|
default: ;
|
default: ;
|
endcase
|
endcase
|
// We predict the return address by storing it in a return address stack
|
// We predict the return address by storing it in a return address stack
|
// during a call instruction, then popping it off the stack in a return
|
// during a call instruction, then popping it off the stack in a return
|
// instruction. The prediction will not always be correct, if it's wrong
|
// instruction. The prediction will not always be correct, if it's wrong
|
// it's corrected by the EX stage branching to the right address.
|
// it's corrected by the EX stage branching to the right address.
|
`CALL:
|
`CALL:
|
begin
|
begin
|
`ifdef RAS_PREDICTION
|
`ifdef RAS_PREDICTION
|
ras[ras_sp] <= fnIncPC(pc);
|
ras[ras_sp] <= fnIncPC(pc);
|
ras_sp <= ras_sp - 6'd1;
|
ras_sp <= ras_sp - 6'd1;
|
`endif
|
`endif
|
dbranch_taken <= 1'b1;
|
dbranch_taken <= 1'b1;
|
pc <= jmp_tgt;
|
pc <= jmp_tgt;
|
end
|
end
|
`RET:
|
`RET:
|
begin
|
begin
|
`ifdef RAS_PREDICTION
|
`ifdef RAS_PREDICTION
|
// $display("predicted return address=%h.%h",{ras[ras_sp + 6'd1][63:4],4'b0000},ras[ras_sp + 6'd1][3:2]);
|
// $display("predicted return address=%h.%h",{ras[ras_sp + 6'd1][63:4],4'b0000},ras[ras_sp + 6'd1][3:2]);
|
pc <= ras[ras_sp + 6'd1];
|
pc <= ras[ras_sp + 6'd1];
|
ras_sp <= ras_sp + 6'd1;
|
ras_sp <= ras_sp + 6'd1;
|
`endif
|
`endif
|
end
|
end
|
`JMP:
|
`JMP:
|
begin
|
begin
|
dbranch_taken <= 1'b1;
|
dbranch_taken <= 1'b1;
|
pc <= jmp_tgt;
|
pc <= jmp_tgt;
|
end
|
end
|
`BTRR:
|
`BTRR:
|
case(insn[4:0])
|
case(insn[4:0])
|
`BEQ,`BNE,`BLT,`BLE,`BGT,`BGE,`BLTU,`BLEU,`BGTU,`BGEU,`BAND,`BOR,`BNR:
|
`BEQ,`BNE,`BLT,`BLE,`BGT,`BGE,`BLTU,`BLEU,`BGTU,`BGEU,`BAND,`BOR,`BRA,`BNR,`BRN,`LOOP:
|
if (predict_taken) begin
|
if (predict_taken) begin
|
// $display("Taking predicted branch: %h",{pc[63:4] + {{42{insn[24]}},insn[24:7]},insn[6:5],2'b00});
|
// $display("Taking predicted branch: %h",{pc[63:4] + {{42{insn[24]}},insn[24:7]},insn[6:5],2'b00});
|
dbranch_taken <= 1'b1;
|
dbranch_taken <= 1'b1;
|
pc <= {pc[63:4] + {{42{insn[24]}},insn[24:7]},insn[6:5],2'b00};
|
pc <= {pc[63:4] + {{42{insn[24]}},insn[24:7]},insn[6:5],2'b00};
|
end
|
end
|
default: ;
|
default: ;
|
endcase
|
endcase
|
`ifdef BTB
|
`ifdef BTB
|
`BTRI:
|
`BTRI:
|
if (predict_taken) begin
|
if (predict_taken) begin
|
dbranch_taken <= 1'b1;
|
dbranch_taken <= 1'b1;
|
pc <= btb[pc[7:2]];
|
pc <= btb[pc[7:2]];
|
end
|
end
|
`endif
|
`endif
|
`BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
|
`BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
|
begin
|
begin
|
if (predict_taken) begin
|
if (predict_taken) begin
|
dbranch_taken <= 1'b1;
|
dbranch_taken <= 1'b1;
|
pc <= {pc[63:4] + {{50{insn[29]}},insn[29:20]},insn[19:18],2'b00};
|
pc <= {pc[63:4] + {{50{insn[29]}},insn[29:20]},insn[19:18],2'b00};
|
end
|
end
|
end
|
end
|
`TRAPcc: if (predict_taken) begin pc <= {TBA[63:13],`GEN_TRAP_OFFSET}; dbranch_taken <= 1'b1; end
|
`TRAPcc: if (predict_taken) begin pc <= {TBA[63:13],`GEN_TRAP_OFFSET}; dbranch_taken <= 1'b1; end
|
`TRAPcci: if (predict_taken) begin pc <= {TBA[63:13],`GEN_TRAP_OFFSET}; dbranch_taken <= 1'b1; end
|
`TRAPcci: if (predict_taken) begin pc <= {TBA[63:13],`GEN_TRAP_OFFSET}; dbranch_taken <= 1'b1; end
|
default: ;
|
default: ;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
//`include "RPSTAGE.v"
|
//`include "RPSTAGE.v"
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
// EXECUTE - part two:
|
// EXECUTE - part two:
|
// - override the default program counter increment for
|
// - override the default program counter increment for
|
// control flow instructions
|
// control flow instructions
|
// - NOP out the instructions following a branch in the
|
// - NOP out the instructions following a branch in the
|
// pipeline
|
// pipeline
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
if (advanceX) begin
|
if (advanceX) begin
|
case(xOpcode)
|
case(xOpcode)
|
`MISC:
|
`MISC:
|
case(xFunc)
|
case(xFunc)
|
`IRET:
|
`IRET:
|
if (StatusHWI) begin
|
if (StatusHWI) begin
|
StatusHWI <= 1'b0;
|
StatusHWI <= 1'b0;
|
im <= 1'b0;
|
im <= 1'b0;
|
pc <= IPC;
|
pc <= IPC;
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
xpcv <= 1'b0;
|
xpcv <= 1'b0;
|
dpcv <= 1'b0;
|
dpcv <= 1'b0;
|
end
|
end
|
`ERET:
|
`ERET:
|
if (StatusEXL) begin
|
if (StatusEXL) begin
|
StatusEXL <= 1'b0;
|
StatusEXL <= 1'b0;
|
pc <= EPC;
|
pc <= EPC;
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
xpcv <= 1'b0;
|
xpcv <= 1'b0;
|
dpcv <= 1'b0;
|
dpcv <= 1'b0;
|
end
|
end
|
default: ;
|
default: ;
|
endcase
|
endcase
|
`R:
|
`R:
|
case(xFunc)
|
case(xFunc)
|
`EXEC:
|
`EXEC:
|
begin
|
begin
|
pc <= fnIncPC(xpc);
|
pc <= fnIncPC(xpc);
|
|
dRa <= b[34:30];
|
|
dRb <= b[29:25];
|
|
dRc <= b[24:20];
|
dIR <= b;
|
dIR <= b;
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
xpcv <= 1'b0;
|
xpcv <= 1'b0;
|
dpcv <= 1'b0;
|
dpcv <= 1'b0;
|
end
|
end
|
default: ;
|
default: ;
|
endcase
|
endcase
|
`BTRR:
|
`BTRR:
|
case(xIR[4:0])
|
case(xIR[4:0])
|
// BEQ r1,r2,label
|
// BEQ r1,r2,label
|
`BEQ,`BNE,`BLT,`BLE,`BGT,`BGE,`BLTU,`BLEU,`BGTU,`BGEU,`BAND,`BOR,`BNR:
|
`BEQ,`BNE,`BLT,`BLE,`BGT,`BGE,`BLTU,`BLEU,`BGTU,`BGEU,`BAND,`BOR,`BNR,`LOOP,`BRA,`BRN:
|
if (!takb & xbranch_taken) begin
|
if (!takb & xbranch_taken) begin
|
$display("Taking mispredicted branch %h",fnIncPC(xpc));
|
$display("Taking mispredicted branch %h",fnIncPC(xpc));
|
pc <= fnIncPC(xpc);
|
pc <= fnIncPC(xpc);
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
xpcv <= 1'b0;
|
xpcv <= 1'b0;
|
dpcv <= 1'b0;
|
dpcv <= 1'b0;
|
end
|
end
|
else if (takb & !xbranch_taken) begin
|
else if (takb & !xbranch_taken) begin
|
$display("Taking branch %h.%h",{xpc[63:4] + {{42{xIR[24]}},xIR[24:7]},4'b0000},xIR[6:5]);
|
$display("Taking branch %h.%h",{xpc[63:4] + {{42{xIR[24]}},xIR[24:7]},4'b0000},xIR[6:5]);
|
pc[63:4] <= xpc[63:4] + {{42{xIR[24]}},xIR[24:7]};
|
pc[63:4] <= xpc[63:4] + {{42{xIR[24]}},xIR[24:7]};
|
pc[3:2] <= xIR[6:5];
|
pc[3:2] <= xIR[6:5];
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
xpcv <= 1'b0;
|
xpcv <= 1'b0;
|
dpcv <= 1'b0;
|
dpcv <= 1'b0;
|
end
|
end
|
// BEQ r1,r2,r10
|
// BEQ r1,r2,r10
|
`BEQR,`BNER,`BLTR,`BLER,`BGTR,`BGER,`BLTUR,`BLEUR,`BGTUR,`BGEUR://,`BANDR,`BORR,`BNRR:
|
`BEQR,`BNER,`BLTR,`BLER,`BGTR,`BGER,`BLTUR,`BLEUR,`BGTUR,`BGEUR://,`BANDR,`BORR,`BNRR:
|
if (takb) begin
|
if (takb) begin
|
pc[63:2] <= c[63:2];
|
pc[63:2] <= c[63:2];
|
pc[1:0] <= 2'b00;
|
pc[1:0] <= 2'b00;
|
`ifdef BTB
|
`ifdef BTB
|
btb[xpc[7:2]] <= c;
|
btb[xpc[7:2]] <= c;
|
`endif
|
`endif
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
xpcv <= 1'b0;
|
xpcv <= 1'b0;
|
dpcv <= 1'b0;
|
dpcv <= 1'b0;
|
end
|
end
|
default: ;
|
default: ;
|
endcase
|
endcase
|
// JMP and CALL change the program counter immediately in the IF stage.
|
// JMP and CALL change the program counter immediately in the IF stage.
|
// There's no work to do here. The pipeline does not need to be cleared.
|
// There's no work to do here. The pipeline does not need to be cleared.
|
`JMP: ;
|
`JMP: ;
|
`CALL: ;
|
`CALL: ;
|
`JAL:
|
`JAL:
|
begin
|
begin
|
pc[63:2] <= a[63:2] + imm[63:2];
|
pc[63:2] <= a[63:2] + imm[63:2];
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
xpcv <= 1'b0;
|
xpcv <= 1'b0;
|
dpcv <= 1'b0;
|
dpcv <= 1'b0;
|
end
|
end
|
|
|
// Check the pc of the instruction after the RET instruction (the dpc), to
|
// Check the pc of the instruction after the RET instruction (the dpc), to
|
// see if it's equal to the RET target. If it's the same as the target then
|
// see if it's equal to the RET target. If it's the same as the target then
|
// we predicted the RET return correctly, so there's nothing to do. Otherwise
|
// we predicted the RET return correctly, so there's nothing to do. Otherwise
|
// we need to branch to the RET location.
|
// we need to branch to the RET location.
|
`RET:
|
`RET:
|
`ifdef RAS_PREDICTION
|
`ifdef RAS_PREDICTION
|
if (dpc[63:2]!=b[63:2]) begin
|
if (dpc[63:2]!=b[63:2]) begin
|
`else
|
`else
|
begin
|
begin
|
`endif
|
`endif
|
// $display("returning to: %h.%h", {b[63:4],4'b0},b[3:2]);
|
// $display("returning to: %h.%h", {b[63:4],4'b0},b[3:2]);
|
pc[63:2] <= b[63:2];
|
pc[63:2] <= b[63:2];
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
xpcv <= 1'b0;
|
xpcv <= 1'b0;
|
dpcv <= 1'b0;
|
dpcv <= 1'b0;
|
end
|
end
|
// else
|
// else
|
// $display("RET address %h predicted correctly.", {b[63:4],4'b0},b[3:2]);
|
// $display("RET address %h predicted correctly.", {b[63:4],4'b0},b[3:2]);
|
// BEQ r1,#3,r10
|
// BEQ r1,#3,r10
|
`BTRI:
|
`BTRI:
|
`ifdef BTB
|
`ifdef BTB
|
if (takb) begin
|
if (takb) begin
|
if ((xbranch_taken && b!=btb[xpc[7:2]]) || // took branch, but not to right target
|
if ((xbranch_taken && b!=btb[xpc[7:2]]) || // took branch, but not to right target
|
!xbranch_taken) begin // didn't take branch, and were supposed to
|
!xbranch_taken) begin // didn't take branch, and were supposed to
|
pc[63:2] <= b[63:2];
|
pc[63:2] <= b[63:2];
|
pc[1:0] <= 2'b00;
|
pc[1:0] <= 2'b00;
|
btb[xpc[7:2]] <= b;
|
btb[xpc[7:2]] <= b;
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
xpcv <= 1'b0;
|
xpcv <= 1'b0;
|
dpcv <= 1'b0;
|
dpcv <= 1'b0;
|
end
|
end
|
end
|
end
|
else if (xbranch_taken) begin // took the branch, and weren't supposed to
|
else if (xbranch_taken) begin // took the branch, and weren't supposed to
|
pc <= fnIncPC(xpc);
|
pc <= fnIncPC(xpc);
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
xpcv <= 1'b0;
|
xpcv <= 1'b0;
|
dpcv <= 1'b0;
|
dpcv <= 1'b0;
|
end
|
end
|
`else
|
`else
|
if (takb) begin
|
if (takb) begin
|
pc[63:2] <= b[63:2];
|
pc[63:2] <= b[63:2];
|
pc[1:0] <= 2'b00;
|
pc[1:0] <= 2'b00;
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
xpcv <= 1'b0;
|
xpcv <= 1'b0;
|
dpcv <= 1'b0;
|
dpcv <= 1'b0;
|
end
|
end
|
`endif
|
`endif
|
// BEQI r1,#3,label
|
// BEQI r1,#3,label
|
`BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
|
`BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
|
if (takb) begin
|
if (takb) begin
|
if (!xbranch_taken) begin
|
if (!xbranch_taken) begin
|
pc[63:4] <= xpc[63:4] + {{50{xIR[29]}},xIR[29:20]};
|
pc[63:4] <= xpc[63:4] + {{50{xIR[29]}},xIR[29:20]};
|
pc[3:2] <= xIR[19:18];
|
pc[3:2] <= xIR[19:18];
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
xpcv <= 1'b0;
|
xpcv <= 1'b0;
|
dpcv <= 1'b0;
|
dpcv <= 1'b0;
|
end
|
end
|
end
|
end
|
else begin
|
else begin
|
if (xbranch_taken) begin
|
if (xbranch_taken) begin
|
// $display("Taking mispredicted branch %h",fnIncPC(xpc));
|
// $display("Taking mispredicted branch %h",fnIncPC(xpc));
|
pc <= fnIncPC(xpc);
|
pc <= fnIncPC(xpc);
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
xpcv <= 1'b0;
|
xpcv <= 1'b0;
|
dpcv <= 1'b0;
|
dpcv <= 1'b0;
|
end
|
end
|
end
|
end
|
`TRAPcc,`TRAPcci:
|
`TRAPcc,`TRAPcci:
|
if (takb) begin
|
if (takb) begin
|
StatusEXL <= 1'b1;
|
StatusEXL <= 1'b1;
|
CauseCode <= `EX_TRAP;
|
CauseCode <= `EX_TRAP;
|
EPC <= xpc;
|
EPC <= xpc;
|
if (!xbranch_taken) begin
|
if (!xbranch_taken) begin
|
pc <= {TBA[63:13],`GEN_TRAP_OFFSET};
|
pc <= {TBA[63:13],`GEN_TRAP_OFFSET};
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
xpcv <= 1'b0;
|
xpcv <= 1'b0;
|
dpcv <= 1'b0;
|
dpcv <= 1'b0;
|
end
|
end
|
end
|
end
|
else begin
|
else begin
|
if (xbranch_taken) begin
|
if (xbranch_taken) begin
|
// $display("Taking mispredicted branch %h",fnIncPC(xpc));
|
// $display("Taking mispredicted branch %h",fnIncPC(xpc));
|
pc <= fnIncPC(xpc);
|
pc <= fnIncPC(xpc);
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
xpcv <= 1'b0;
|
xpcv <= 1'b0;
|
dpcv <= 1'b0;
|
dpcv <= 1'b0;
|
end
|
end
|
end
|
end
|
default: ;
|
default: ;
|
endcase
|
endcase
|
|
|
if (dbz_error) begin
|
if (dbz_error) begin
|
$display("Divide by zero error");
|
$display("Divide by zero error");
|
CauseCode <= `EX_DBZ;
|
CauseCode <= `EX_DBZ;
|
StatusEXL <= 1'b1;
|
StatusEXL <= 1'b1;
|
EPC <= xpc;
|
EPC <= xpc;
|
pc <= {TBA[63:13],`DBZ_TRAP_OFFSET};
|
pc <= {TBA[63:13],`DBZ_TRAP_OFFSET};
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
xpcv <= 1'b0;
|
xpcv <= 1'b0;
|
dpcv <= 1'b0;
|
dpcv <= 1'b0;
|
end
|
end
|
else if (ovr_error) begin
|
else if (ovr_error) begin
|
$display("Overflow error");
|
$display("Overflow error");
|
CauseCode <= `EX_OFL;
|
CauseCode <= `EX_OFL;
|
StatusEXL <= 1'b1;
|
StatusEXL <= 1'b1;
|
EPC <= xpc;
|
EPC <= xpc;
|
pc <= {TBA[63:13],`OFL_TRAP_OFFSET};
|
pc <= {TBA[63:13],`OFL_TRAP_OFFSET};
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
xpcv <= 1'b0;
|
xpcv <= 1'b0;
|
dpcv <= 1'b0;
|
dpcv <= 1'b0;
|
end
|
end
|
else if (priv_violation) begin
|
else if (priv_violation) begin
|
$display("Priviledge violation");
|
$display("Priviledge violation");
|
CauseCode <= `EX_PRIV;
|
CauseCode <= `EX_PRIV;
|
StatusEXL <= 1'b1;
|
StatusEXL <= 1'b1;
|
EPC <= xpc;
|
EPC <= xpc;
|
pc <= {TBA[63:13],`PRIV_OFFSET};
|
pc <= {TBA[63:13],`PRIV_OFFSET};
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
xpcv <= 1'b0;
|
xpcv <= 1'b0;
|
dpcv <= 1'b0;
|
dpcv <= 1'b0;
|
end
|
end
|
end
|
end
|
|
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
// MEMORY1 (M1') - part two:
|
// MEMORY1 (M1') - part two:
|
// Check for a TLB miss.
|
// Check for a TLB miss.
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
`ifdef TLB
|
`ifdef TLB
|
if (advanceM1) begin
|
if (advanceM1) begin
|
if (m1IsLoad|m1IsStore) begin
|
if (m1IsLoad|m1IsStore) begin
|
if (DTLBMiss) begin
|
if (DTLBMiss) begin
|
$display("DTLB miss on address: %h",ea);
|
$display("DTLB miss on address: %h",ea);
|
m1extype <= `EX_TLBD;
|
m1extype <= `EX_TLBD;
|
CauseCode <= `EX_TLBD;
|
CauseCode <= `EX_TLBD;
|
StatusEXL <= 1'b1;
|
StatusEXL <= 1'b1;
|
BadVAddr <= ea[63:13];
|
BadVAddr <= ea[63:13];
|
EPC <= m1pc;
|
EPC <= m1pc;
|
pc <= `DTLB_MissHandler;
|
pc <= `DTLB_MissHandler;
|
m1Opcode <= `NOPI;
|
m1Opcode <= `NOPI;
|
m1Rt <= 9'd0;
|
m1Rt <= 9'd0;
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
m1pcv <= 1'b0;
|
m1pcv <= 1'b0;
|
xpcv <= 1'b0;
|
xpcv <= 1'b0;
|
dpcv <= 1'b0;
|
dpcv <= 1'b0;
|
end
|
end
|
end
|
end
|
end
|
end
|
`endif
|
`endif
|
|
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
// MEMORY2 (M2')
|
// MEMORY2 (M2')
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
if (advanceM2) begin
|
if (advanceM2) begin
|
end
|
end
|
|
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
// WRITEBACK (WB') - part two:
|
// WRITEBACK (WB') - part two:
|
// - vector to exception handler address
|
// - vector to exception handler address
|
// In the case of a hardware interrupt (NMI/IRQ) we know
|
// In the case of a hardware interrupt (NMI/IRQ) we know
|
// the pipeline following the interrupt is filled with
|
// the pipeline following the interrupt is filled with
|
// NOP instructions. This means there is no need to
|
// NOP instructions. This means there is no need to
|
// invalidate the pipeline.
|
// invalidate the pipeline.
|
// Also, we have to wait until the WB stage before
|
// Also, we have to wait until the WB stage before
|
// vectoring so that the pc setting doesn't get trashed
|
// vectoring so that the pc setting doesn't get trashed
|
// by a branch or other exception.
|
// by a branch or other exception.
|
// Tricky because we have to find the first valid
|
// Tricky because we have to find the first valid
|
// PC to record in the IPC register. The interrupt might
|
// PC to record in the IPC register. The interrupt might
|
// have occurred in a branch shadow, in which case the
|
// have occurred in a branch shadow, in which case the
|
// current PC isn't valid.
|
// current PC isn't valid.
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
if (advanceW) begin
|
if (advanceW) begin
|
case(wextype)
|
case(wextype)
|
`EX_RST: begin
|
`EX_RST: begin
|
pc <= `RESET_VECTOR;
|
pc <= `RESET_VECTOR;
|
case(1'b1)
|
case(1'b1)
|
wpcv: IPC <= wpc;
|
wpcv: IPC <= wpc;
|
m2pcv: IPC <= m2pc;
|
m2pcv: IPC <= m2pc;
|
m1pcv: IPC <= m1pc;
|
m1pcv: IPC <= m1pc;
|
xpcv: IPC <= xpc;
|
xpcv: IPC <= xpc;
|
dpcv: IPC <= dpc;
|
dpcv: IPC <= dpc;
|
default: IPC <= pc;
|
default: IPC <= pc;
|
endcase
|
endcase
|
end
|
end
|
`EX_NMI: begin
|
`EX_NMI: begin
|
pc <= `NMI_VECTOR;
|
pc <= `NMI_VECTOR;
|
case(1'b1)
|
case(1'b1)
|
wpcv: IPC <= wpc;
|
wpcv: IPC <= wpc;
|
m2pcv: IPC <= m2pc;
|
m2pcv: IPC <= m2pc;
|
m1pcv: IPC <= m1pc;
|
m1pcv: IPC <= m1pc;
|
xpcv: IPC <= xpc;
|
xpcv: IPC <= xpc;
|
dpcv: IPC <= dpc;
|
dpcv: IPC <= dpc;
|
default: IPC <= pc;
|
default: IPC <= pc;
|
endcase
|
endcase
|
end
|
end
|
`EX_IRQ: begin
|
`EX_IRQ: begin
|
pc <= `IRQ_VECTOR;
|
pc <= `IRQ_VECTOR;
|
case(1'b1)
|
case(1'b1)
|
wpcv: IPC <= wpc;
|
wpcv: IPC <= wpc;
|
m2pcv: IPC <= m2pc;
|
m2pcv: IPC <= m2pc;
|
m1pcv: IPC <= m1pc;
|
m1pcv: IPC <= m1pc;
|
xpcv: IPC <= xpc;
|
xpcv: IPC <= xpc;
|
dpcv: IPC <= dpc;
|
dpcv: IPC <= dpc;
|
default: IPC <= pc;
|
default: IPC <= pc;
|
endcase
|
endcase
|
end
|
end
|
default: ;
|
default: ;
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
// Trailer (TR')
|
// Trailer (TR')
|
// - no exceptions
|
// - no exceptions
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
if (advanceT) begin
|
if (advanceT) begin
|
end
|
end
|
|
|
|
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
// Cache loader
|
// Cache loader
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
if (rst_i) begin
|
if (rst_i) begin
|
cstate <= IDLE;
|
cstate <= IDLE;
|
end
|
end
|
else begin
|
else begin
|
case(cstate)
|
case(cstate)
|
IDLE:
|
IDLE:
|
if (triggerDCacheLoad) begin
|
if (triggerDCacheLoad) begin
|
dcaccess <= 1'b1;
|
dcaccess <= 1'b1;
|
bte_o <= 2'b00; // linear burst
|
bte_o <= 2'b00; // linear burst
|
cti_o <= 3'b010; // burst access
|
cti_o <= 3'b010; // burst access
|
bl_o <= 5'd8;
|
bl_o <= 5'd8;
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
adr_o <= {pea[63:6],6'h00};
|
adr_o <= {pea[63:6],6'h00};
|
cstate <= DCACT;
|
cstate <= DCACT;
|
end
|
end
|
else if (triggerICacheLoad) begin
|
else if (triggerICacheLoad) begin
|
icaccess <= 1'b1;
|
icaccess <= 1'b1;
|
bte_o <= 2'b00; // linear burst
|
bte_o <= 2'b00; // linear burst
|
cti_o <= 3'b010; // burst access
|
cti_o <= 3'b010; // burst access
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
if (ICacheAct) begin
|
if (ICacheAct) begin
|
bl_o <= 5'd8;
|
bl_o <= 5'd8;
|
adr_o <= {ppc[63:6],6'h00};
|
adr_o <= {ppc[63:6],6'h00};
|
cstate <= ICACT1;
|
cstate <= ICACT1;
|
end
|
end
|
else begin
|
else begin
|
bl_o <= 5'd2;
|
bl_o <= 5'd2;
|
adr_o <= {ppc[63:4],4'b0000};
|
adr_o <= {ppc[63:4],4'b0000};
|
cstate <= ICACT2;
|
cstate <= ICACT2;
|
end
|
end
|
end
|
end
|
// WISHBONE burst accesses
|
// WISHBONE burst accesses
|
//
|
//
|
ICACT1:
|
ICACT1:
|
if (ack_i) begin
|
if (ack_i) begin
|
adr_o[5:3] <= adr_o[5:3] + 3'd1;
|
adr_o[5:3] <= adr_o[5:3] + 3'd1;
|
if (adr_o[5:3]==3'd6)
|
if (adr_o[5:3]==3'd6)
|
cti_o <= 3'b111; // Last cycle ahead
|
cti_o <= 3'b111; // Last cycle ahead
|
else if (adr_o[5:3]==3'd7) begin
|
else if (adr_o[5:3]==3'd7) begin
|
cti_o <= 3'b000; // back to non-burst mode
|
cti_o <= 3'b000; // back to non-burst mode
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
tmem[adr_o[12:6]] <= {1'b1,adr_o[63:13]}; // This will cause ihit to go high
|
tmem[adr_o[12:6]] <= {1'b1,adr_o[63:13]}; // This will cause ihit to go high
|
tvalid[adr_o[12:6]] <= 1'b1;
|
tvalid[adr_o[12:6]] <= 1'b1;
|
icaccess <= 1'b0;
|
icaccess <= 1'b0;
|
cstate <= IDLE;
|
cstate <= IDLE;
|
end
|
end
|
end
|
end
|
ICACT2:
|
ICACT2:
|
if (ack_i) begin
|
if (ack_i) begin
|
adr_o <= adr_o + 64'd8;
|
adr_o <= adr_o + 64'd8;
|
if (adr_o[3]==1'b0) begin
|
if (adr_o[3]==1'b0) begin
|
cti_o <= 3'b111; // Last cycle ahead
|
cti_o <= 3'b111; // Last cycle ahead
|
tmpbuf <= dat_i;
|
tmpbuf <= dat_i;
|
end
|
end
|
else begin
|
else begin
|
insnbuf <= {dat_i,tmpbuf};
|
if (tick[0]) begin
|
|
insnbuf0 <= {dat_i,tmpbuf};
|
|
ibuftag0 <= adr_o[63:4];
|
|
end
|
|
else begin
|
|
insnbuf1 <= {dat_i,tmpbuf};
|
|
ibuftag1 <= adr_o[63:4];
|
|
end
|
cti_o <= 3'b000; // back to non-burst mode
|
cti_o <= 3'b000; // back to non-burst mode
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
icaccess <= 1'b0;
|
icaccess <= 1'b0;
|
ibuftag <= adr_o[63:4];
|
|
cstate <= IDLE;
|
cstate <= IDLE;
|
end
|
end
|
end
|
end
|
|
|
DCACT:
|
DCACT:
|
if (ack_i) begin
|
if (ack_i) begin
|
adr_o[5:3] <= adr_o[5:3] + 3'd1;
|
adr_o[5:3] <= adr_o[5:3] + 3'd1;
|
if (adr_o[5:3]==3'h6)
|
if (adr_o[5:3]==3'h6)
|
cti_o <= 3'b111; // Last cycle ahead
|
cti_o <= 3'b111; // Last cycle ahead
|
if (adr_o[5:3]==3'h7) begin
|
if (adr_o[5:3]==3'h7) begin
|
cti_o <= 3'b000; // back to non-burst mode
|
cti_o <= 3'b000; // back to non-burst mode
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
dcaccess <= 1'b0;
|
dcaccess <= 1'b0;
|
cstate <= IDLE;
|
cstate <= IDLE;
|
end
|
end
|
end
|
end
|
|
|
endcase
|
endcase
|
end
|
end
|
|
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
