--! @file arithblock.vhd
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--! @file arithblock.vhd
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--! @brief Bloque Aritmético de 4 sumadores y 6 multiplicadores.
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--! @brief Bloque Aritmético de 4 sumadores y 6 multiplicadores.
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--! @author Julián Andrés Guarín Reyes
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--! @author Julián Andrés Guarín Reyes
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--------------------------------------------------------------
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--------------------------------------------------------------
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-- RAYTRAC
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-- RAYTRAC
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-- Author Julian Andres Guarin
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-- Author Julian Andres Guarin
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-- memblock.vhd
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-- memblock.vhd
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-- This file is part of raytrac.
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-- This file is part of raytrac.
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--
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--
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-- raytrac is free software: you can redistribute it and/or modify
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-- raytrac is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- (at your option) any later version.
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--
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--
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-- raytrac is distributed in the hope that it will be useful,
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-- raytrac is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- GNU General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU General Public License
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-- You should have received a copy of the GNU General Public License
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.arithpack.all;
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use work.arithpack.all;
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entity arithblock is
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entity arithblock is
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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dpc : in std_logic;
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dpc : in std_logic;
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f : in std_logic_vector (12*32-1 downto 0);
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f : in vectorblock12;
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a : in std_logic_vector (8*32-1 downto 0);
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a : in vectorblock08;
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s : out std_logic_vector (4*32-1 downto 0);
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s : out vectorblock04;
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p : out std_logic_vector (6*32-1 downto 0)
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p : out vectorblock06
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);
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);
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end entity;
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end entity;
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architecture arithblock_arch of arithblock is
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architecture arithblock_arch of arithblock is
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begin
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begin
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--! 4 sumadores.
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--! 4 sumadores.
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-- arithblock:
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-- arithblock:
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-- for i in 3 downto 0 generate
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-- for i in 3 downto 0 generate
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-- adder_i : fadd32
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-- adder_i : fadd32
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-- port map (
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-- port map (
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-- clk => clk,
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-- clk => clk,
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-- dpc => dpc,
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-- dpc => dpc,
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-- a32 => a( ((i*2)+1)*32-1 downto (i*2)*32),
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-- a32 => a( ((i*2)+1)*32-1 downto (i*2)*32),
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-- b32 => a( ((i*2)+2)*32-1 downto ((i*2)+1)*32),
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-- b32 => a( ((i*2)+2)*32-1 downto ((i*2)+1)*32),
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-- c32 => s( (i+1)*32-1 downto 32*i)
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-- c32 => s( (i+1)*32-1 downto 32*i)
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-- );
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-- );
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-- end generate arithblock;
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-- end generate arithblock;
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--! 6 multiplicadores.
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--! 6 multiplicadores.
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-- mulblock:
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-- mulblock:
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-- for i in 5 downto 0 generate
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-- for i in 5 downto 0 generate
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-- mul_i : fmul32
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-- mul_i : fmul32
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-- port map (
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-- port map (
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-- clk => clk,
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-- clk => clk,
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-- a32 => f( ((i*2)+1)*32-1 downto (i*2)*32),
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-- a32 => f( ((i*2)+1)*32-1 downto (i*2)*32),
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-- b32 => f( ((i*2)+2)*32-1 downto ((i*2)+1)*32),
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-- b32 => f( ((i*2)+2)*32-1 downto ((i*2)+1)*32),
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-- p32 => p( (i+1)*32-1 downto 32*i)
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-- p32 => p( (i+1)*32-1 downto 32*i)
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-- );
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-- );
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-- end generate mulblock;
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-- end generate mulblock;
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--!TBXINSTANCESTART
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--!TBXINSTANCESTART
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adder_i_0 : fadd32
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adder_i_0 : fadd32
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port map (
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port map (
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clk => clk,
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clk => clk,
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dpc => dpc,
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dpc => dpc,
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a32 => a( 31 downto 0),
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a32 => a(0),
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b32 => a( 63 downto 32),
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b32 => a(1),
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c32 => s( 31 downto 0)
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c32 => s(0)
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);
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);
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--!TBXINSTANCESTART
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--!TBXINSTANCESTART
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adder_i_1 : fadd32
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adder_i_1 : fadd32
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port map (
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port map (
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clk => clk,
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clk => clk,
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dpc => dpc,
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dpc => dpc,
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a32 => a( 95 downto 64),
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a32 => a(2),
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b32 => a( 127 downto 96),
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b32 => a(3),
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c32 => s( 63 downto 32)
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c32 => s(1)
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);
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);
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--!TBXINSTANCESTART
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--!TBXINSTANCESTART
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adder_i_2 : fadd32
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adder_i_2 : fadd32
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port map (
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port map (
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clk => clk,
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clk => clk,
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dpc => dpc,
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dpc => dpc,
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a32 => a( 159 downto 128),
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a32 => a(4),
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b32 => a( 191 downto 160),
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b32 => a(5),
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c32 => s( 95 downto 64)
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c32 => s(2)
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);
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);
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--!TBXINSTANCESTART
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--!TBXINSTANCESTART
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adder_i_3 : fadd32
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adder_i_3 : fadd32
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port map (
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port map (
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clk => clk,
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clk => clk,
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dpc => dpc,
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dpc => dpc,
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a32 => a( 223 downto 192),
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a32 => a(6),
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b32 => a( 255 downto 224),
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b32 => a(7),
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c32 => s( 127 downto 96)
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c32 => s(3)
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);
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);
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--!TBXINSTANCESTART
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--!TBXINSTANCESTART
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mul_i_0 : fmul32
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mul_i_0 : fmul32
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port map (
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port map (
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clk => clk,
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clk => clk,
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a32 => f( 31 downto 0),
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a32 => f(0),
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b32 => f( 63 downto 32),
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b32 => f(1),
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p32 => p( 31 downto 0)
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p32 => p(0)
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);
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);
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--!TBXINSTANCESTART
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--!TBXINSTANCESTART
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mul_i_1 : fmul32
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mul_i_1 : fmul32
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port map (
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port map (
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clk => clk,
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clk => clk,
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a32 => f( 95 downto 64),
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a32 => f(2),
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b32 => f( 127 downto 96),
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b32 => f(3),
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p32 => p( 63 downto 32)
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p32 => p(1)
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);
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);
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--!TBXINSTANCESTART
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--!TBXINSTANCESTART
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mul_i_2 : fmul32
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mul_i_2 : fmul32
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port map (
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port map (
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clk => clk,
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clk => clk,
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a32 => f( 159 downto 128),
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a32 => f(4),
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b32 => f( 191 downto 160),
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b32 => f(5),
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p32 => p( 95 downto 64)
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p32 => p(2)
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);
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);
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--!TBXINSTANCESTART
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--!TBXINSTANCESTART
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mul_i_3 : fmul32
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mul_i_3 : fmul32
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port map (
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port map (
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clk => clk,
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clk => clk,
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a32 => f( 223 downto 192),
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a32 => f(6),
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b32 => f( 255 downto 224),
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b32 => f(7),
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p32 => p( 127 downto 96)
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p32 => p(3)
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);
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);
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--!TBXINSTANCESTART
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--!TBXINSTANCESTART
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mul_i_4 : fmul32
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mul_i_4 : fmul32
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port map (
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port map (
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clk => clk,
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clk => clk,
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a32 => f( 287 downto 256),
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a32 => f(8),
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b32 => f( 319 downto 288),
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b32 => f(9),
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p32 => p( 159 downto 128)
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p32 => p(4)
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);
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);
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--!TBXINSTANCESTART
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--!TBXINSTANCESTART
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mul_i_5 : fmul32
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mul_i_5 : fmul32
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port map (
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port map (
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clk => clk,
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clk => clk,
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a32 => f( 351 downto 320),
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a32 => f(10),
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b32 => f( 383 downto 352),
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b32 => f(11),
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p32 => p( 191 downto 160)
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p32 => p(5)
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);
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);
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end architecture;
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end architecture;
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