library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.math_real.all;
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library std;
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use std.textio.all;
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--! Memory Compiler Library
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--! Memory Compiler Library
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library lpm;
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library lpm;
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use lpm.all;
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use lpm.all;
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package arithpack is
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package arithpack is
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--! Estados para la maquina de estados.
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--! Estados para la maquina de estados.
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type macState is (LOAD_INSTRUCTION,FLUSH_ARITH_PIPELINE,EXECUTE_INSTRUCTION);
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type macState is (LOAD_INSTRUCTION,FLUSH_ARITH_PIPELINE,EXECUTE_INSTRUCTION);
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--! Estados para el controlador de interrupciones.
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--! Estados para el controlador de interrupciones.
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type iCtrlState is (WAITING_FOR_AN_EVENT,FIRING_INTERRUPTIONS,SUSPEND);
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type iCtrlState is (WAITING_FOR_AN_EVENT,FIRING_INTERRUPTIONS,SUSPEND);
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--! Float data blocks
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--! Float data blocks
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constant floatwidth : integer := 32;
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constant floatwidth : integer := 32;
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constant widthadmemblock : integer := 9;
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constant widthadmemblock : integer := 9;
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type vectorblock12 is array (11 downto 0) of std_logic_vector(floatwidth-1 downto 0);
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type vectorblock12 is array (11 downto 0) of std_logic_vector(floatwidth-1 downto 0);
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type vectorblock08 is array (07 downto 0) of std_logic_vector(floatwidth-1 downto 0);
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type vectorblock08 is array (07 downto 0) of std_logic_vector(floatwidth-1 downto 0);
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type vectorblock06 is array (05 downto 0) of std_logic_vector(floatwidth-1 downto 0);
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type vectorblock06 is array (05 downto 0) of std_logic_vector(floatwidth-1 downto 0);
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type vectorblock04 is array (03 downto 0) of std_logic_vector(floatwidth-1 downto 0);
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type vectorblock04 is array (03 downto 0) of std_logic_vector(floatwidth-1 downto 0);
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type vectorblock03 is array (02 downto 0) of std_logic_vector(floatwidth-1 downto 0);
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type vectorblock03 is array (02 downto 0) of std_logic_vector(floatwidth-1 downto 0);
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type vectorblock02 is array (01 downto 0) of std_logic_vector(floatwidth-1 downto 0);
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type vectorblock02 is array (01 downto 0) of std_logic_vector(floatwidth-1 downto 0);
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type vectorblockadd02 is array (01 downto 0) of std_logic_vector(widthadmemblock-1 downto 0);
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type vectorblockadd02 is array (01 downto 0) of std_logic_vector(widthadmemblock-1 downto 0);
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type v3f is array(02 downto 0) of std_logic_vector(31 downto 0);
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--! Constante de reseteo
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--! Constante de reseteo
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constant rstMasterValue : std_logic :='0';
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constant rstMasterValue : std_logic :='0';
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--! Constantes periodicas.
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--! Constantes periodicas.
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constant tclk : time := 20 ns;
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constant tclk : time := 20 ns;
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constant tclk_2 : time := tclk/2;
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constant tclk_2 : time := tclk/2;
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constant tclk_4 : time := tclk/4;
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constant tclk_4 : time := tclk/4;
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component raytrac
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component raytrac
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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--! Señal de lectura de alguna de las colas de resultados.
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--! Señal de lectura de alguna de las colas de resultados.
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rd : in std_logic;
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rd : in std_logic;
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--! Señal de escritura en alguno de los bloques de memoria de operandos o en la cola de instrucciones.
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--! Señal de escritura en alguno de los bloques de memoria de operandos o en la cola de instrucciones.
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wr : in std_logic;
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wr : in std_logic;
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--! Direccion de escritura o lectura
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--! Direccion de escritura o lectura
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add : in std_logic_vector (12 downto 0);
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add : in std_logic_vector (12 downto 0);
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--! datos de entrada
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--! datos de entrada
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d : in std_logic_vector (31 downto 0);
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d : in std_logic_vector (31 downto 0);
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--! Interrupciones
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--! Interrupciones
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int : out std_logic_vector (7 downto 0);
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int : out std_logic_vector (7 downto 0);
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--! Salidas
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--! Salidas
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q : out std_logic_vector (31 downto 0)
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q : out std_logic_vector (31 downto 0)
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);
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);
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end component;
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end component;
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--! Componentes Aritméticos
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--! Componentes Aritméticos
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component fadd32
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component fadd32
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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dpc : in std_logic;
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dpc : in std_logic;
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a32 : in std_logic_vector (31 downto 0);
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a32 : in std_logic_vector (31 downto 0);
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b32 : in std_logic_vector (31 downto 0);
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b32 : in std_logic_vector (31 downto 0);
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c32 : out std_logic_vector (31 downto 0)
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c32 : out std_logic_vector (31 downto 0)
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);
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);
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end component;
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end component;
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component fmul32
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component fmul32
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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a32 : in std_logic_vector (31 downto 0);
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a32 : in std_logic_vector (31 downto 0);
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b32 : in std_logic_vector (31 downto 0);
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b32 : in std_logic_vector (31 downto 0);
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p32 : out std_logic_vector (31 downto 0)
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p32 : out std_logic_vector (31 downto 0)
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);
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);
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end component;
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end component;
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--! Contadores para la máquina de estados.
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--! Contadores para la máquina de estados.
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component customCounter
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component customCounter
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generic (
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generic (
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EOBFLAG : string ;
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EOBFLAG : string ;
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ZEROFLAG : string ;
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ZEROFLAG : string ;
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BACKWARDS : string ;
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BACKWARDS : string ;
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EQUALFLAG : string ;
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EQUALFLAG : string ;
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subwidth : integer;
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subwidth : integer;
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width : integer
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width : integer
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);
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);
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port (
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port (
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clk,rst,go,set : in std_logic;
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clk,rst,go,set : in std_logic;
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setValue,cmpBlockValue : in std_Logic_vector(width-1 downto subwidth);
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setValue,cmpBlockValue : in std_Logic_vector(width-1 downto subwidth);
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zero_flag,eob_flag,eq_flag : out std_logic;
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zero_flag,eob_flag,eq_flag : out std_logic;
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count : out std_logic_vector(width-1 downto 0)
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count : out std_logic_vector(width-1 downto 0)
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);
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);
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end component;
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end component;
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--! LPM Memory Compiler.
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--! LPM Memory Compiler.
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component scfifo
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component scfifo
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generic (
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generic (
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add_ram_output_register :string;
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add_ram_output_register :string;
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almost_full_value :natural;
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almost_full_value :natural;
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allow_wrcycle_when_full :string;
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allow_wrcycle_when_full :string;
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intended_device_family :string;
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intended_device_family :string;
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lpm_hint :string;
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lpm_hint :string;
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lpm_numwords :natural;
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lpm_numwords :natural;
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lpm_showahead :string;
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lpm_showahead :string;
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lpm_type :string;
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lpm_type :string;
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lpm_width :natural;
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lpm_width :natural;
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lpm_widthu :natural;
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lpm_widthu :natural;
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overflow_checking :string;
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overflow_checking :string;
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underflow_checking :string;
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underflow_checking :string;
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use_eab :string
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use_eab :string
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);
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);
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port(
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port(
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rdreq : in std_logic;
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rdreq : in std_logic;
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aclr : in std_logic;
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aclr : in std_logic;
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empty : out std_logic;
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empty : out std_logic;
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clock : in std_logic;
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clock : in std_logic;
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q : out std_logic_vector(lpm_width-1 downto 0);
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q : out std_logic_vector(lpm_width-1 downto 0);
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wrreq : in std_logic;
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wrreq : in std_logic;
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data : in std_logic_vector(lpm_width-1 downto 0);
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data : in std_logic_vector(lpm_width-1 downto 0);
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almost_full : out std_logic;
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almost_full : out std_logic;
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full : out std_logic
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full : out std_logic
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);
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);
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end component;
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end component;
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component altsyncram
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component altsyncram
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generic (
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generic (
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address_aclr_b : string;
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address_aclr_b : string;
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address_reg_b : string;
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address_reg_b : string;
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clock_enable_input_a : string;
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clock_enable_input_a : string;
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clock_enable_input_b : string;
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clock_enable_input_b : string;
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clock_enable_output_b : string;
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clock_enable_output_b : string;
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intended_device_family : string;
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intended_device_family : string;
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lpm_type : string;
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lpm_type : string;
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numwords_a : natural;
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numwords_a : natural;
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numwords_b : natural;
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numwords_b : natural;
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operation_mode : string;
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operation_mode : string;
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outdata_aclr_b : string;
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outdata_aclr_b : string;
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outdata_reg_b : string;
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outdata_reg_b : string;
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power_up_uninitialized : string;
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power_up_uninitialized : string;
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ram_block_type : string;
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ram_block_type : string;
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rdcontrol_reg_b : string;
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rdcontrol_reg_b : string;
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read_during_write_mode_mixed_ports : string;
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read_during_write_mode_mixed_ports : string;
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widthad_a : natural;
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widthad_a : natural;
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widthad_b : natural;
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widthad_b : natural;
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width_a : natural;
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width_a : natural;
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width_b : natural;
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width_b : natural;
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width_byteena_a : natural
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width_byteena_a : natural
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);
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);
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port (
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port (
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wren_a : in std_logic;
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wren_a : in std_logic;
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clock0 : in std_logic;
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clock0 : in std_logic;
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address_a : in std_logic_vector(8 downto 0);
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address_a : in std_logic_vector(8 downto 0);
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address_b : in std_logic_vector(8 downto 0);
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address_b : in std_logic_vector(8 downto 0);
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rden_b : in std_logic;
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rden_b : in std_logic;
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q_b : out std_logic_vector(31 downto 0);
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q_b : out std_logic_vector(31 downto 0);
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data_a : in std_logic_vector(31 downto 0)
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data_a : in std_logic_vector(31 downto 0)
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);
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);
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end component;
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end component;
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--! Maquina de Estados.
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--! Maquina de Estados.
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component sm
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component sm
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port (
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port (
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--! Señales normales de secuencia.
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--! Señales normales de secuencia.
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clk,rst: in std_logic;
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clk,rst: in std_logic;
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--! Vector con las instrucción codficada
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--! Vector con las instrucción codficada
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instrQq:in std_logic_vector(31 downto 0);
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instrQq:in std_logic_vector(31 downto 0);
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--! Señal de cola vacia.
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--! Señal de cola vacia.
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instrQ_empty:in std_logic;
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instrQ_empty:in std_logic;
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adda,addb:out std_logic_vector (8 downto 0);
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adda,addb:out std_logic_vector (8 downto 0);
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sync_chain_0,instrRdAckd:out std_logic;
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sync_chain_0,instrRdAckd:out std_logic;
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full_r: in std_logic; --! Indica que la cola de resultados no puede aceptar mas de 32 elementos.
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full_r: in std_logic; --! Indica que la cola de resultados no puede aceptar mas de 32 elementos.
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--! End Of Instruction Event
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--! End Of Instruction Event
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eoi : out std_logic;
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eoi : out std_logic;
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--! DataPath Control uca code.
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--! DataPath Control uca code.
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dpc_uca : out std_logic_vector (2 downto 0);
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dpc_uca : out std_logic_vector (2 downto 0);
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state : out macState
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state : out macState
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);
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);
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end component;
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end component;
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--! Maquina de Interrupciones
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--! Maquina de Interrupciones
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component im
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component im
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generic (
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generic (
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num_events : integer ;
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num_events : integer ;
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cycles_to_wait : integer
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cycles_to_wait : integer
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);
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);
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port (
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port (
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clk,rst: in std_logic;
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clk,rst: in std_logic;
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rfull_events: in std_logic_vector(num_events-1 downto 0); --! full results queue events
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rfull_events: in std_logic_vector(num_events-1 downto 0); --! full results queue events
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eoi_events: in std_logic_vector(num_events-1 downto 0); --! end of instruction related events
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eoi_events: in std_logic_vector(num_events-1 downto 0); --! end of instruction related events
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eoi_int: out std_logic_vector(num_events-1 downto 0);--! end of instruction related interruptions
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eoi_int: out std_logic_vector(num_events-1 downto 0);--! end of instruction related interruptions
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rfull_int: out std_logic_vector(num_events-1downto 0); --! full results queue related interruptions
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rfull_int: out std_logic_vector(num_events-1downto 0); --! full results queue related interruptions
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state: out iCtrlState
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state: out iCtrlState
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);
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);
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end component;
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end component;
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--! Bloque de memorias
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--! Bloque de memorias
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component memblock
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component memblock
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generic (
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generic (
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blocksize : integer;
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blocksize : integer;
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external_writeable_blocks : integer;
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external_writeable_blocks : integer;
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external_readable_blocks : integer;
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external_readable_blocks : integer;
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external_readable_widthad : integer;
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external_readable_widthad : integer;
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external_writeable_widthad : integer
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external_writeable_widthad : integer
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);
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);
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port (
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port (
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clk,rst,dpfifo_rd,normfifo_rd,dpfifo_wr,normfifo_wr : in std_logic;
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clk,rst,dpfifo_rd,normfifo_rd,dpfifo_wr,normfifo_wr : in std_logic;
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instrfifo_rd : in std_logic;
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instrfifo_rd : in std_logic;
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resultfifo_wr: in std_logic_vector(external_readable_blocks-1 downto 0);
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resultfifo_wr: in std_logic_vector(external_readable_blocks-1 downto 0);
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instrfifo_empty: out std_logic; ext_rd,ext_wr: in std_logic;
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instrfifo_empty: out std_logic; ext_rd,ext_wr: in std_logic;
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ext_wr_add : in std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
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ext_wr_add : in std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
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ext_rd_add : in std_logic_vector(external_readable_widthad-1 downto 0);
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ext_rd_add : in std_logic_vector(external_readable_widthad-1 downto 0);
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ext_d: in std_logic_vector(floatwidth-1 downto 0);
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ext_d: in std_logic_vector(floatwidth-1 downto 0);
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int_d : in std_logic_vector(external_readable_blocks*floatwidth-1 downto 0);
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int_d : in std_logic_vector(external_readable_blocks*floatwidth-1 downto 0);
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resultfifo_full : out std_logic_vector(3 downto 0);
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resultfifo_full : out std_logic_vector(3 downto 0);
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ext_q,instrfifo_q : out std_logic_vector(floatwidth-1 downto 0);
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ext_q,instrfifo_q : out std_logic_vector(floatwidth-1 downto 0);
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int_q : out std_logic_vector(external_writeable_blocks*floatwidth-1 downto 0);
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int_q : out std_logic_vector(external_writeable_blocks*floatwidth-1 downto 0);
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int_rd_add : in std_logic_vector(2*widthadmemblock-1 downto 0);
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int_rd_add : in std_logic_vector(2*widthadmemblock-1 downto 0);
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dpfifo_d : in std_logic_vector(floatwidth*2-1 downto 0);
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dpfifo_d : in std_logic_vector(floatwidth*2-1 downto 0);
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normfifo_d : in std_logic_vector(floatwidth*3-1 downto 0);
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normfifo_d : in std_logic_vector(floatwidth*3-1 downto 0);
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dpfifo_q : out std_logic_vector(floatwidth*2-1 downto 0);
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dpfifo_q : out std_logic_vector(floatwidth*2-1 downto 0);
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normfifo_q : out std_logic_vector(floatwidth*3-1 downto 0)
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normfifo_q : out std_logic_vector(floatwidth*3-1 downto 0)
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);
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);
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end component;
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end component;
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--! Bloque decodificacion DataPath Control.
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--! Bloque decodificacion DataPath Control.
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component dpc
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component dpc
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port (
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port (
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clk,rst : in std_logic;
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clk,rst : in std_logic;
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paraminput : in std_logic_vector ((12*floatwidth)-1 downto 0); --! Vectores A,B,C,D
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paraminput : in std_logic_vector ((12*floatwidth)-1 downto 0); --! Vectores A,B,C,D
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prd32blko : in std_logic_vector ((06*floatwidth)-1 downto 0); --! Salidas de los 6 multiplicadores.
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prd32blko : in std_logic_vector ((06*floatwidth)-1 downto 0); --! Salidas de los 6 multiplicadores.
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add32blko : in std_logic_vector ((04*floatwidth)-1 downto 0); --! Salidas de los 4 sumadores.
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add32blko : in std_logic_vector ((04*floatwidth)-1 downto 0); --! Salidas de los 4 sumadores.
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sqr32blko,inv32blko : in std_logic_vector (floatwidth-1 downto 0); --! Salidas de la raiz cuadradas y el inversor.
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sqr32blko,inv32blko : in std_logic_vector (floatwidth-1 downto 0); --! Salidas de la raiz cuadradas y el inversor.
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fifo32x23_q : in std_logic_vector (03*floatwidth-1 downto 0); --! Salida de la cola intermedia.
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fifo32x23_q : in std_logic_vector (03*floatwidth-1 downto 0); --! Salida de la cola intermedia.
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fifo32x09_q : in std_logic_vector (02*floatwidth-1 downto 0); --! Salida de las colas de producto punto.
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fifo32x09_q : in std_logic_vector (02*floatwidth-1 downto 0); --! Salida de las colas de producto punto.
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unary,crossprod,addsub : in std_logic; --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D).
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unary,crossprod,addsub : in std_logic; --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D).
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sync_chain_0 : in std_logic; --! Señal de dato valido que se va por toda la cadena de sincronizacion.
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sync_chain_0 : in std_logic; --! Señal de dato valido que se va por toda la cadena de sincronizacion.
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eoi_int : in std_logic; --! Señal de interrupción de final de instrucci&ocaute;n.
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eoi_int : in std_logic; --! Señal de interrupción de final de instrucci&ocaute;n.
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eoi_demuxed_int : out std_logic_vector (3 downto 0); --! Señal de interrup&ocaute;n de final de instrucción pero esta vez va asociada a la instruccón UCA.
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eoi_demuxed_int : out std_logic_vector (3 downto 0); --! Señal de interrup&ocaute;n de final de instrucción pero esta vez va asociada a la instruccón UCA.
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sqr32blki,inv32blki : out std_logic_vector (floatwidth-1 downto 0); --! Salidas de las 2 raices cuadradas y los 2 inversores.
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sqr32blki,inv32blki : out std_logic_vector (floatwidth-1 downto 0); --! Salidas de las 2 raices cuadradas y los 2 inversores.
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fifo32x26_d : out std_logic_vector (03*floatwidth-1 downto 0); --! Entrada a la cola intermedia para la normalización.
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fifo32x26_d : out std_logic_vector (03*floatwidth-1 downto 0); --! Entrada a la cola intermedia para la normalización.
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fifo32x09_d : out std_logic_vector (02*floatwidth-1 downto 0); --! Entrada a las colas intermedias del producto punto.
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fifo32x09_d : out std_logic_vector (02*floatwidth-1 downto 0); --! Entrada a las colas intermedias del producto punto.
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prd32blki : out std_logic_vector ((12*floatwidth)-1 downto 0); --! Entrada de los 12 factores en el bloque de multiplicación respectivamente.
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prd32blki : out std_logic_vector ((12*floatwidth)-1 downto 0); --! Entrada de los 12 factores en el bloque de multiplicación respectivamente.
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add32blki : out std_logic_vector ((08*floatwidth)-1 downto 0); --! Entrada de los 8 sumandos del bloque de 4 sumadores.
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add32blki : out std_logic_vector ((08*floatwidth)-1 downto 0); --! Entrada de los 8 sumandos del bloque de 4 sumadores.
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resw : out std_logic_vector (4 downto 0); --! Salidas de escritura y lectura en las colas de resultados.
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resw : out std_logic_vector (4 downto 0); --! Salidas de escritura y lectura en las colas de resultados.
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fifo32x09_w : out std_logic;
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fifo32x09_w : out std_logic;
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fifo32x23_w,fifo32x09_r : out std_logic;
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fifo32x23_w,fifo32x09_r : out std_logic;
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fifo32x23_r : out std_logic;
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fifo32x23_r : out std_logic;
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resf_vector : in std_logic_vector(3 downto 0); --! Entradas de la señal de full de las colas de resultados.
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resf_vector : in std_logic_vector(3 downto 0); --! Entradas de la señal de full de las colas de resultados.
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resf_event : out std_logic; --! Salida decodificada que indica que la cola de resultados de la operación que está en curso.
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resf_event : out std_logic; --! Salida decodificada que indica que la cola de resultados de la operación que está en curso.
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resultoutput : out std_logic_vector ((08*floatwidth)-1 downto 0) --! 8 salidas de resultados, pues lo máximo que podrá calcularse por cada clock son 2 vectores.
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resultoutput : out std_logic_vector ((08*floatwidth)-1 downto 0) --! 8 salidas de resultados, pues lo máximo que podrá calcularse por cada clock son 2 vectores.
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);
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);
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end component;
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end component;
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--! Bloque Aritmetico de Sumadores y Multiplicadores (madd)
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--! Bloque Aritmetico de Sumadores y Multiplicadores (madd)
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component arithblock
|
component arithblock
|
port (
|
port (
|
|
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
|
|
dpc : in std_logic;
|
dpc : in std_logic;
|
|
|
f : in std_logic_vector (12*32-1 downto 0);
|
f : in std_logic_vector (12*32-1 downto 0);
|
a : in std_logic_vector (8*32-1 downto 0);
|
a : in std_logic_vector (8*32-1 downto 0);
|
|
|
s : out std_logic_vector (4*32-1 downto 0);
|
s : out std_logic_vector (4*32-1 downto 0);
|
p : out std_logic_vector (6*32-1 downto 0)
|
p : out std_logic_vector (6*32-1 downto 0)
|
|
|
);
|
);
|
end component;
|
end component;
|
--! Bloque de Raiz Cuadrada
|
--! Bloque de Raiz Cuadrada
|
component sqrt32
|
component sqrt32
|
port (
|
port (
|
|
|
clk : in std_logic;
|
clk : in std_logic;
|
rd32: in std_logic_vector(31 downto 0);
|
rd32: in std_logic_vector(31 downto 0);
|
sq32: out std_logic_vector(31 downto 0)
|
sq32: out std_logic_vector(31 downto 0)
|
);
|
);
|
end component;
|
end component;
|
--! Bloque de Inversores.
|
--! Bloque de Inversores.
|
component invr32
|
component invr32
|
port (
|
port (
|
|
|
clk : in std_logic;
|
clk : in std_logic;
|
dvd32 : in std_logic_vector(31 downto 0);
|
dvd32 : in std_logic_vector(31 downto 0);
|
qout32 : out std_logic_vector(31 downto 0)
|
qout32 : out std_logic_vector(31 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
|
|
|
|
|
|
|
type apCamera is record
|
|
resx,resy : integer;
|
|
width,height : real;
|
|
dist : real;
|
|
end record;
|
|
|
|
--! Función que convierte un std_logic_vector en un numero entero
|
|
function ap_slv2int(sl:std_logic_vector) return integer;
|
|
|
|
--! Función que convierte un número flotante IEE754 single float, en un número std_logic_vector.
|
|
function ap_fp2slv (f:real) return std_logic_vector;
|
|
|
|
--! Función que convierte un número std_logic_vector en un ieee754 single float.
|
|
function ap_slv2fp (sl:std_logic_vector) return real;
|
|
|
|
--! Función que devuelve un vector en punto flotante IEEE754 a través de un
|
|
function ap_slv_calc_xyvec (x,y:integer; cam:apCamera) return v3f;
|
|
|
|
|
|
|
|
|
|
|
end package;
|
end package;
|
|
|
No newline at end of file
|
No newline at end of file
|
|
|
|
package body arithpack is
|
|
|
|
function ap_slv2int (sl:std_logic_vector) return integer is
|
|
alias s : std_logic_vector (sl'high downto sl'low) is sl;
|
|
variable i : integer;
|
|
begin
|
|
i:=0;
|
|
for index in s'high downto s'low loop
|
|
if s(index)='1' then
|
|
i:=i*2+1;
|
|
else
|
|
i:=i*2;
|
|
end if;
|
|
end loop;
|
|
return i;
|
|
|
|
end function;
|
|
function ap_fp2slv (f:real) return std_logic_vector is
|
|
variable faux : real;
|
|
variable sef : std_logic_vector (31 downto 0);
|
|
begin
|
|
--! Signo
|
|
if (f<0.0) then
|
|
sef(31) := '1';
|
|
else
|
|
sef(31) := '0';
|
|
end if;
|
|
|
|
--! Exponente
|
|
sef(30 downto 23) := conv_std_logic_vector(integer(floor(log(f,2.0))),8);
|
|
|
|
--! Fraction
|
|
faux :=f/floor(log(f,2.0));
|
|
faux := faux - 1.0;
|
|
|
|
sef(22 downto 0) := conv_std_logic_vector(integer(faux),23);
|
|
|
|
return sef;
|
|
|
|
end function;
|
|
|
|
function ap_slv2fp(sl:std_logic_vector) return real is
|
|
variable expo,frc:integer;
|
|
alias s: std_logic_vector(31 downto 0) is sl;
|
|
variable f: real;
|
|
|
|
begin
|
|
|
|
|
|
expo:=ap_slv2int(s(30 downto 23)) - 127;
|
|
expo:=2**expo;
|
|
frc:=ap_slv2int('1'&s(22 downto 0));
|
|
f:=real(frc)*(2.0**(-23.0));
|
|
f:=f*real(expo);
|
|
|
|
if s(31)='1' then
|
|
return -f;
|
|
else
|
|
return f;
|
|
end if;
|
|
|
|
|
|
end function;
|
|
|
|
function ap_slv_calc_xyvec (x,y:integer; cam:apCamera) return v3f is
|
|
|
|
|
|
variable dx,dy : real;
|
|
variable v : v3f;
|
|
begin
|
|
|
|
dx := cam.width/real(cam.resx);
|
|
dy := cam.height/real(cam.resy);
|
|
|
|
--! Eje X: Tomando el dedo índice de la mano derecha, este eje queda apuntando en la direcci&on en la que mira la cámara u observador siempre.
|
|
v(0):=ap_fp2slv(cam.dist);
|
|
|
|
--! Eje Y: Tomando el dedo corazón de la mano derecha, este eje queda apuntando a la izquierda del observador, desde el observador.
|
|
v(1):=ap_fp2slv(dx*real(cam.resx)*0.5-dx*0.5);
|
|
|
|
--! Eje Z: Tomando el dedo pulgar de la mano derecha, este eje queda apuntando hacia arriba del observador, desde el observador.
|
|
v(2):=ap_fp2slv(dy*real(cam.resy)*0.5-dy*0.5);
|
|
|
|
return v;
|
|
|
|
end function;
|
|
|
|
end package body;
|
No newline at end of file
|
No newline at end of file
|
