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--! @file mul2.vhd
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--! @file fmul32.vhd
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--! @brief RayTrac Mantissa Multiplier
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--! @brief RayTrac Mantissa Multiplier
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--! @author Julián Andrés Guarín Reyes
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--! @author Julián Andrés Guarín Reyes
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--------------------------------------------------
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--------------------------------------------------
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-- RAYTRAC (FP BRANCH)
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-- RAYTRAC (FP BRANCH)
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-- Author Julian Andres Guarin
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-- Author Julian Andres Guarin
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-- mmp.vhd
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-- fmul32.vhd
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-- This file is part of raytrac.
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-- This file is part of raytrac.
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--
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--
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-- raytrac is free software: you can redistribute it and/or modify
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-- raytrac is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- (at your option) any later version.
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--
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--
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-- raytrac is distributed in the hope that it will be useful,
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-- raytrac is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- GNU General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU General Public License
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-- You should have received a copy of the GNU General Public License
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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entity fmul32 is
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entity mul2 is
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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a32,b32 : in std_logic_vector(31 downto 0);
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a32,b32 : in std_logic_vector(31 downto 0);
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p32 : out std_logic_vector(31 downto 0)
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p32 : out std_logic_vector(31 downto 0)
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);
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);
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end mul2;
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end fmul32;
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architecture fmul32_arch of fmul32 is
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architecture mul2_arch of mul2 is
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component lpm_mult
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component lpm_mult
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generic (
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generic (
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lpm_hint : string;
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lpm_hint : string;
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lpm_pipeline : natural;
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lpm_pipeline : natural;
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lpm_representation : string;
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lpm_representation : string;
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lpm_type : string;
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lpm_type : string;
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lpm_widtha : natural;
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lpm_widtha : natural;
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lpm_widthb : natural;
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lpm_widthb : natural;
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lpm_widthp : natural
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lpm_widthp : natural
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);
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);
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port (
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port (
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dataa : in std_logic_vector ( lpm_widtha-1 downto 0 );
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dataa : in std_logic_vector ( lpm_widtha-1 downto 0 );
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datab : in std_logic_vector ( lpm_widthb-1 downto 0 );
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datab : in std_logic_vector ( lpm_widthb-1 downto 0 );
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result : out std_logic_vector ( lpm_widthp-1 downto 0 )
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result : out std_logic_vector ( lpm_widthp-1 downto 0 )
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);
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);
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end component;
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end component;
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--Stage 0 signals
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--Stage 0 signals
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signal s0sga,s0sgb,s0zrs,s1sgr,s2sgr:std_logic;
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signal s0sga,s0sgb,s0zrs,s1sgr,s2sgr:std_logic;
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signal s0exa,s0exb,s1exp,s2exp:std_logic_vector(7 downto 0);
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signal s0exa,s0exb,s1exp,s2exp:std_logic_vector(7 downto 0);
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signal s0exp : std_logic_vector(8 downto 0);
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signal s0exp : std_logic_vector(7 downto 0);
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signal s0uma,s0umb:std_logic_vector(22 downto 0);
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signal s0uma,s0umb:std_logic_vector(22 downto 0);
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signal s0ad,s0bc,s1ad,s1bc:std_logic_vector(23 downto 0);
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signal s0ad,s0bc,s1ad,s1bc:std_logic_vector(23 downto 0);
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signal s0ac:std_logic_vector(35 downto 0);
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signal s0ac:std_logic_vector(35 downto 0);
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signal s1ac,s1umu:std_logic_vector(35 downto 0);
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signal s1ac,s1umu:std_logic_vector(35 downto 0);
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signal s2umu:std_logic_vector(24 downto 0);
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signal s2umu:std_logic_vector(24 downto 0);
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begin
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begin
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process(clk)
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process(clk)
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begin
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begin
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if clk'event and clk='1' then
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if clk'event and clk='1' then
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--! Registro de entrada
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--! Registro de entrada
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s0sga <= a32(31);
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s0sga <= a32(31);
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s0sgb <= b32(31);
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s0sgb <= b32(31);
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s0exa <= a32(30 downto 23);
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s0exa <= a32(30 downto 23);
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s0exb <= b32(30 downto 23);
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s0exb <= b32(30 downto 23);
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s0uma <= a32(22 downto 0);
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s0uma <= a32(22 downto 0);
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s0umb <= b32(22 downto 0);
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s0umb <= b32(22 downto 0);
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--! Etapa 0 multiplicacion de la mantissa, suma de los exponentes y multiplicación de los signos.
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--! Etapa 0 multiplicacion de la mantissa, suma de los exponentes y multiplicación de los signos.
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s1sgr <= s0sga xor s0sgb;
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s1sgr <= s0sga xor s0sgb;
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s1ad <= s0ad;
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s1ad <= s0ad;
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s1bc <= s0bc;
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s1bc <= s0bc;
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s1ac <= s0ac;
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s1ac <= s0ac;
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s1exp <= s0exp(7 downto 0);
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s1exp <= s0exp;
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--! Etapa 1 Sumas parciales
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--! Etapa 1 Sumas parciales
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s2umu <= s1umu(35 downto 11);
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s2umu <= s1umu(35 downto 11);
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s2sgr <= s1sgr;
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s2sgr <= s1sgr;
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s2exp <= s1exp;
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s2exp <= s1exp;
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--! Etapa 2 entregar el resultado
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--! Etapa 2 entregar el resultado
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p32(31) <= s2sgr;
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p32(31) <= s2sgr;
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p32(30 downto 23) <= s2exp+s2umu(24);
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p32(30 downto 23) <= s2exp+s2umu(24);
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if s2umu(24) ='1' then
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if s2umu(24) ='1' then
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p32(22 downto 0) <= s2umu(23 downto 1);
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p32(22 downto 0) <= s2umu(23 downto 1);
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else
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else
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p32(22 downto 0) <= s2umu(22 downto 0);
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p32(22 downto 0) <= s2umu(22 downto 0);
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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--! Combinatorial Gremlin Etapa 0 : multiplicacion de la mantissa, suma de los exponentes y multiplicación de los signos.
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--! Combinatorial Gremlin Etapa 0 : multiplicacion de la mantissa, suma de los exponentes y multiplicación de los signos.
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--! Multipliers
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--! Multipliers
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mult18x18ac:lpm_mult
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mult18x18ac:lpm_mult
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generic map ("DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",0,"UNSIGNED","LPM_MULT",18,18,36)
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generic map ("DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",0,"UNSIGNED","LPM_MULT",18,18,36)
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port map (s0zrs&s0uma(22 downto 6),s0zrs&s0umb(22 downto 6),s0ac);
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port map (s0zrs&s0uma(22 downto 6),s0zrs&s0umb(22 downto 6),s0ac);
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mult18x6ad:lpm_mult
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mult18x6ad:lpm_mult
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generic map ("DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",0,"UNSIGNED","LPM_MULT",18,6,24)
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generic map ("DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",0,"UNSIGNED","LPM_MULT",18,6,24)
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port map (s0zrs&s0uma(22 downto 6),s0umb(5 downto 0),s0ad);
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port map (s0zrs&s0uma(22 downto 6),s0umb(5 downto 0),s0ad);
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mult18x6bc:lpm_mult
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mult18x6bc:lpm_mult
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generic map ("DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",0,"UNSIGNED","LPM_MULT",18,6,24)
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generic map ("DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",0,"UNSIGNED","LPM_MULT",18,6,24)
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port map (s0zrs&s0umb(22 downto 6),s0uma(5 downto 0),s0bc);
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port map (s0zrs&s0umb(22 downto 6),s0uma(5 downto 0),s0bc);
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--! Exponent Addition
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--! Exponent Addition
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process (s0sga,s0sgb,s0exa,s0exb)
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process (s0sga,s0sgb,s0exa,s0exb)
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variable i8s0exa,i8s0exb: integer range 0 to 255;
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begin
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begin
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i8s0exa:=conv_integer(s0exa);
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i8s0exb:=conv_integer(s0exb);
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if s0exa=x"00" or s0exb=x"00" then
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if i8s0exa = 0 or i8s0exb = 0 then
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s0exp <= (others => '0');
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s0exp <= (others => '0');
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s0zrs <= '0';
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s0zrs <= '0';
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else
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else
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s0zrs<='1';
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s0zrs<='1';
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s0exp <= conv_std_logic_vector(i8s0exb+i8s0exa+129,9);
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s0exp <= s0exa+s0exb+x"81";
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end if;
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end if;
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end process;
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end process;
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--! Etapa 1: Suma parcial de la multiplicacion. Suma del exponente
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--! Etapa 1: Suma parcial de la multiplicacion. Suma del exponente
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process(s1ac,s1ad,s1bc)
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process(s1ac,s1ad,s1bc)
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begin
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begin
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s1umu <= s1ac+s1ad(23 downto 6)+s1bc(23 downto 6);
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s1umu <= s1ac+s1ad(23 downto 6)+s1bc(23 downto 6);
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end process;
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end process;
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end mul2_arch;
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No newline at end of file
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No newline at end of file
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end fmul32_arch;
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No newline at end of file
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No newline at end of file
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