--! @file sm.vhd
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--! @file sm.vhd
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--! @brief Maquina de Estados. Controla la operación interna y genera los mecanismos de sincronización con el exterior (interrupciones).
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--! @brief Maquina de Estados. Controla la operación interna y genera los mecanismos de sincronización con el exterior (interrupciones).
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--! @author Julián Andrés Guarín Reyes
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--! @author Julián Andrés Guarín Reyes
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--------------------------------------------------------------
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--------------------------------------------------------------
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-- RAYTRAC
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-- RAYTRAC
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-- Author Julian Andres Guarin
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-- Author Julian Andres Guarin
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-- sm.vhd
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-- sm.vhd
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-- This file is part of raytrac.
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-- This file is part of raytrac.
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--
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--
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-- raytrac is free software: you can redistribute it and/or modify
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-- raytrac is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- (at your option) any later version.
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--
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--
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-- raytrac is distributed in the hope that it will be useful,
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-- raytrac is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- GNU General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU General Public License
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-- You should have received a copy of the GNU General Public License
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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entity sm is
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entity sm is
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generic (
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width : integer := 32;
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widthadmemblock : integer := 9
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--!external_readable_widthad :
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)
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port (
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port (
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clk,rst:in std_logic;
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clk,rst:in std_logic;
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add0,add1:out std_logic_vector (8 downto 0);
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iq:in std_logic_vector(31 downto 0);
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read_memory,ird_ack:out std_logic;
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ucsa:out std_logic(3 downto 0);
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iempty , rfull, opq_empty : in std_logic;
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);
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end entity;
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architecture sm_arch of sm is
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adda,addb:out std_logic_vector (widthadmemblock-1 downto 0);
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sync_chain_d:out std_logic;
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type macState is (IDLE,EXECUTING,FLUSHING);
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--! Instruction Q, instruction.
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signal state : macState;
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instrQq:in std_logic_vector(width-1 downto 0);
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constant rstMasterValue : std_logic:='0';
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--! apempty, arithmetical pipeline empty.
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arithPbusy, instrQempty ,resultQfull: in std_logic;
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signal sadd0,sadd1:std_logic_vector (8 downto 0);
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--! DataPath Control uca code.
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signal schunk0o,schunk0f,schunk1o,schunk1f: std_logic_vector (3 downto 0);
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dpc_uca : out std_logic_vector (2 downto 0);
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signal sadd0_now,sadd0_next,sadd0_reg:std_logic_vector(8 downto 0);
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signal sadd1_now,sadd1_next,sadd1_reg:std_logic_vector(8 downto 0);
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signal sadd0_adder_bit,sadd1_adder_bit,sena:std_logic;
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begin
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);
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end entity;
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architecture sm_arch of sm is
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schunk0o(3 downto 0) <= iq(19 downto 16);
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type macState is (FLUSH_TO_NEXT_INSTRUCTION,EXECUTE_INSTRUCTION);
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schunk0f(3 downto 0) <= iq(15 downto 12);
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signal state : macState;
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schunk1o(3 downto 0) <= iq(11 downto 8);
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constant rstMasterValue : std_logic:='0';
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schunk1f(3 downto 0) <= iq(7 downto 4);
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ucsa <= iq(3 downto 0);
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component customCounter
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generic (
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width : integer
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);
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port (
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clk,rst,go,set : in std_logic;
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setValue : in std_Logic_vector(width-1 downto 0);
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count : out std_logic_vector(width-1 downto 0)
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)
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signal addt0_blocka,addt0_blockb,set_Value_A,set_Value_B : std_logic_vector(widthadmemblock-1 downto 0);
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signal add_condition_a, add_condition_b,set_a,set_b : std_logic;
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signal s_dpc_uca, s_instrQ_uca : std_logic_vector(2 downto 0);
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signal s_block_start_a, s_block_start_b, s_block_end_a, s_block_end_b : std_logic_vector(4 downto 0);
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sadd0_next <= sadd0_now+sadd0_adder_bit;
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sadd1_next <= sadd1_now+sadd1_adder_bit;
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sm_comb:
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process (state)
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begin
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begin
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case state is
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when IDLE =>
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sadd0_now <= schunk0o(3 downto 0)&x"0";
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sadd1_now <= schunk1o(3 downto 0)&x"0";
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when others =>
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sadd0_now <= sadd0_next;
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sadd1_now <= sadd1_next;
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end case;
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end process;
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--! Bloques asignados
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s_block_start_a <= instrQq(width-4 downto width-8);
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s_block_start_b <= instrQq(width-14 downto width-18);
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s_block_end_a <= instrQq(width-9 downto width-13);
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s_block_end_b <= instrQq(width-19 downto width-)
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--! Address Counters
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counterA:customCounter
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port map (clk,rst,add_condition_a,set_a,instrQq(width-4 downto width-8)&x"0",addt0_blocka);
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counterB:customCounter
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port map (clk,rst,add_condition_b,set_b,instrQq(width-9 downto width-12)&x"0",addt0_blockb);
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adda <= addt0_blocka;
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addb <= addt0_blockb;
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--! uca code
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s_instrQ_uca <= instrQq(31 downto 29);
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sm_proc:
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sm_proc:
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process (clk,rst)
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process (clk,rst)
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begin
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begin
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if rst=rstMasterValue then
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if rst=rstMasterValue then
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state <= IDLE;
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state <= IDLE;
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ird_ack <= '0';
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ird_ack <= '0';
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elsif clk='1' and clk'event and sena='1' then
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elsif clk='1' and clk'event then
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case state is
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case state is
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when IDLE =>
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when FLUSH_TO_NEXT_INSTRUCTION =>
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if rfull='0' and iempty='0' then
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state <= EXECUTING;
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read_memory <= '1';
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end if;
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when EXCUTING =>
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if rfull='0' then
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if sadd1_now=schunk1f&"11111" then
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if sadd0_now=schunk0f&"11111" then
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state <= FLUSHING;
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end if;
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--! Chequear si hay una instruccion en la salida de la cola de instruccioens.
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end if;
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if instrQempty='0' then
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end if;
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when FLUSHING =>
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--! Chequear si la cola de resultados tiene espacio.
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if opq_empty='1' then
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if resultQfull='0' then
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--! Si el codigo de instruccion (uca) que se encuentra en el DPC es igual al que se encuentra en la instruccion de la salida de la cola de instrucciones, entonces no hay mas validaciones que hacer.
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--! Now check that arithmetic pipline is not busy
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if arithPbusy='0' then
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when EXECUTE_INSTRUCTION =>
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if addt1_blockb(4 downto 0)=x"1f" and addt1_blocka=x"1f" then
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if addt1_blockb(8 downto )
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else
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end if;
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end if;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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nxtadda_proc:
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process ()
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end architecture;
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end architecture;
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