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--! @file fsqrt32.vhd
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--! @file fsqrt32.vhd
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--! @brief RayTrac Floating Point Adder
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--! @brief RayTrac Floating Point Adder
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--! @author Julián Andrés Guarín Reyes
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--! @author Julián Andrés Guarín Reyes
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--------------------------------------------------
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--------------------------------------------------
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-- RAYTRAC (FP BRANCH)
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-- RAYTRAC (FP BRANCH)
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-- Author Julian Andres Guarin
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-- Author Julian Andres Guarin
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-- fsqrt32.vhd
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-- fsqrt32.vhd
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-- This file is part of raytrac.
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-- This file is part of raytrac.
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--
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--
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-- raytrac is free software: you can redistribute it and/or modify
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-- raytrac is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- (at your option) any later version.
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--
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--
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-- raytrac is distributed in the hope that it will be useful,
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-- raytrac is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- GNU General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU General Public License
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-- You should have received a copy of the GNU General Public License
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use work.arithpack.all;
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entity sqrt32 is
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entity sqrt32 is
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rd32: in std_logic_vector(31 downto 0);
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rd32: in xfloat32;
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sq32: out std_logic_vector(31 downto 0)
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sq32: out xfloat32
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);
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);
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end entity;
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end entity;
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architecture sqrt32_arch of sqrt32 is
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architecture sqrt32_arch of sqrt32 is
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component altsyncram
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component altsyncram
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generic (
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generic (
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address_aclr_a : string;
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address_aclr_a : string;
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clock_enable_input_a : string;
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clock_enable_input_a : string;
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clock_enable_output_a : string;
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clock_enable_output_a : string;
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init_file : string;
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init_file : string;
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intended_device_family : string;
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intended_device_family : string;
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lpm_hint : string;
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lpm_hint : string;
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lpm_type : string;
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lpm_type : string;
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numwords_a : natural;
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numwords_a : natural;
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operation_mode : string;
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operation_mode : string;
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outdata_aclr_a : string;
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outdata_aclr_a : string;
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outdata_reg_a : string;
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outdata_reg_a : string;
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widthad_a : natural;
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widthad_a : natural;
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width_a : natural;
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width_a : natural;
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width_byteena_a : natural
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width_byteena_a : natural
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);
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);
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port (
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port (
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clock0 : in std_logic;
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clock0 : in std_logic;
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rden_a : in std_logic;
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rden_a : in std_logic;
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address_a : in std_logic_vector (9 downto 0);
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address_a : in std_logic_vector (9 downto 0);
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q_a : out std_logic_vector (17 downto 0)
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q_a : out std_logic_vector (17 downto 0)
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);
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);
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end component;
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end component;
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signal s0sgn : std_logic;
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signal s0sgn : std_logic;
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signal s0uexp,s0e129 : std_logic_vector(7 downto 0);
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signal s0uexp,s0e129 : std_logic_vector(7 downto 0);
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signal s0q : std_logic_vector(17 downto 0);
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signal s0q : std_logic_vector(17 downto 0);
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signal sxprop : std_logic;
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signal sxprop : std_logic;
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begin
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begin
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--! SNAN?
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--! SNAN?
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process (clk)
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process (clk)
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begin
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begin
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if clk'event and clk='1' then
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if clk'event and clk='1' then
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--!Carga de Operando.
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--!Carga de Operando.
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s0sgn <= rd32(31);
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s0sgn <= rd32(31);
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s0uexp <= rd32(30 downto 23);
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s0uexp <= rd32(30 downto 23);
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end if;
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end if;
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end process;
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end process;
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--! Etapa 0: Calcular dirección a partir del exponente y el exponente.
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--! Etapa 0: Calcular dirección a partir del exponente y el exponente.
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sq32(31) <= s0sgn;
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sq32(31) <= s0sgn;
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sq32(30 downto 23) <= (s0e129(7)&s0e129(7 downto 1))+127;
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sq32(30 downto 23) <= (s0e129(7)&s0e129(7 downto 1))+127;
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sq32(22 downto 6) <= s0q(16 downto 0);
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sq32(22 downto 6) <= s0q(16 downto 0);
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--! Combinatorial Gremlin: Etapa 0, calculo del exponente.
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--! Combinatorial Gremlin: Etapa 0, calculo del exponente.
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s0e129<=s0uexp+("1000000"&s0uexp(0));
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s0e129<=s0uexp+("1000000"&s0uexp(0));
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sq32(5 downto 0) <= (others => '0');
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sq32(5 downto 0) <= (others => '0');
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--! Combinatorial Gremlin, Etapa 0, calcula la raíz cuadrada de la mantissa
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--! Combinatorial Gremlin, Etapa 0, calcula la raíz cuadrada de la mantissa
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--! Recuerde que aunque rd32(23) no pertenece a la mantissa indica si el exponente es par o impar, 1 (par) y 0 (impar)
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--! Recuerde que aunque rd32(23) no pertenece a la mantissa indica si el exponente es par o impar, 1 (par) y 0 (impar)
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altsyncram_component : altsyncram
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altsyncram_component : altsyncram
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generic map (
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generic map (
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address_aclr_a => "NONE",
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address_aclr_a => "NONE",
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clock_enable_input_a => "BYPASS",
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clock_enable_input_a => "BYPASS",
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clock_enable_output_a => "BYPASS",
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clock_enable_output_a => "BYPASS",
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--init_file => "X:/Code/Indigo/fp/fp/memsqrt.mif",
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--init_file => "X:/Code/Indigo/fp/fp/memsqrt.mif",
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init_file => "//IMACJULIAN/imac/Code/Indigo/fp/fp/memsqrt.mif",
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init_file => "//IMACJULIAN/imac/Code/Indigo/fp/fp/memsqrt.mif",
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intended_device_family => "Cyclone III",
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intended_device_family => "Cyclone III",
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lpm_hint => "ENABLE_RUNTIME_MOD=NO",
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lpm_hint => "ENABLE_RUNTIME_MOD=NO",
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lpm_type => "altsyncram",
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lpm_type => "altsyncram",
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numwords_a => 1024,
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numwords_a => 1024,
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operation_mode => "ROM",
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operation_mode => "ROM",
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outdata_aclr_a => "NONE",
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outdata_aclr_a => "NONE",
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outdata_reg_a => "UNREGISTERED",
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outdata_reg_a => "UNREGISTERED",
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widthad_a => 10,
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widthad_a => 10,
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width_a => 18,
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width_a => 18,
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width_byteena_a => 1
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width_byteena_a => 1
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)
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)
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port map (rden_a => '1', clock0 => clk, address_a => rd32(23 downto 14), q_a => s0q);
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port map (rden_a => '1', clock0 => clk, address_a => rd32(23 downto 14), q_a => s0q);
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